Gradual Channel Approximation Research Articles

Implementation of TFET SPICE Model for Ultra-Low Power Circuit Analysis

We proposed a compact model for tunneling field effect transistors (TFETs), which combines BSIM4. Our proposed model for tunneling current is based on a drift-diffusion model under the gradual-channel approximation. The total charge for the drain current has been described by a weighted sum of the tunneling charge and the oxide charge for gate-to-source overlap region. In order to obtain TFETs compact model for circuit simulation that operates in every voltage region, the operating current under the various gate-to-source voltage and drain-to-source voltage conditions are considered. Verilog-A description for our proposed model are implemented in the circuit simulator. Model parameters are extracted for conventional TFETs structure by comparing with in-house 2-D TCAD simulation results. After the transistor-level verification, the circuit-level simulation of 81-stage ring-oscillator using our proposed model has been performed.

A Compact SPICE Model for Organic TFTs and Applications to Logic Circuit Design

This work introduces a compact DC model developed for organic thin film transistors (OTFTs) and its SPICE implementation. The model relies on a modified version of the gradual channel approximation that takes into account the contact effects, occurring at nonohmic metal/organic semiconductor junctions, modeling them as reverse biased Schottky diodes. The model also comprises channel length modulation and scalability of drain current with respect to channel length. To show the suitability of the model, we used it to design an inverter and a ring oscillator circuit. Furthermore, an experimental validation of the OTFTs has been done at the level of the single device as well as with a discrete-component setup based on two OTFTs connected into an inverter configuration. The experimental tests were based on OTFTs that use small molecules in binder matrix as an active layer. The experimental data on the fabricated devices have been found in good agreement with SPICE simulation results, paving the way to the use of the model and the device for the design of OTFT-based integrated circuits.

Surface potential measurement on contact resistance of amorphous-InGaZnO thin film transistors by Kelvin probe force microscopy

Contact resistance plays an important role in amorphous InGaZnO (a-IGZO) thin film transistors (TFTs). In this paper, the surface potential distributions along the channel have been measured by using Kelvin probe force microscopy (KPFM) on operating a-IGZO TFTs, and sharp potential drops at the edges of source and drain were observed. The source and drain contact resistances can be extracted by dividing sharp potential drops with the corresponding drain to source current. It is found that the contact resistances could not be neglected compared with the whole channel resistances in the a-IGZO TFT, and the contact resistances decrease remarkably with increasing gate biased voltage. Our results suggest that the contact resistances can be controlled by tuning the gate biased voltage. Moreover, a transition from gradual channel approximation to space charge region was observed through the surface potential map directly when TFT operating from linear regime to saturation regime.

Analytic drain current model for III–V cylindrical nanowire transistors

An analytical model is proposed to determine the drain current of III–V cylindrical nanowires (NWs). The model uses the gradual channel approximation and takes into account the complete analytical solution of the Poisson and Schrödinger equations for the Γ-valley and for an arbitrary number of subbands. Fermi–Dirac statistics are considered to describe the 1D electron gas in the NWs, being the resulting recursive Fermi–Dirac integral of order −1/2 successfully integrated under reasonable assumptions. The model has been validated against numerical simulations showing excellent agreement for different semiconductor materials, diameters up to 40 nm, gate overdrive biases up to 0.7 V, and densities of interface states up to 1013eV−1cm−2.

Contact Effects in Amorphous InGaZnO Thin Film Transistors

Control of the source-drain contact properties in amorphous InGaZnO semiconductor active layer is relevant since a high series resistance in the source-drain contacts causes degradation of electrical performance, particularly affecting short channel devices. We developed a method to extract the current-voltage characteristics of the injection contact, assuming that contact effects are negligible in long channel devices and by introducing a modified gradual channel approximation (quasi-two-dimensional model), to take into account for short channel effects. The present method allows to extract the parasitic resistance by using devices with only two different channel lengths. Assuming a transmission line scheme for the contact resistance and SCLC transport for the current density flowing along the vertical direction though the IGZO bulk, we have been able to evaluate the variation with ${\rm V}_{{\rm ds}}$ of contact resistance at source and drain electrodes.

Full-Range Analytic Drain Current Model for Depletion-Mode Long-Channel Surrounding-Gate Nanowire Field-Effect Transistor

A full-range analytic drain current model for depletion-mode long-channel surrounding-gate nanowire field-effect transistor (SGNWFET) is proposed. The model is derived from the solution of the 1-D cylindrical Poisson equation which includes dopant and mobile charges, by using the Pao-Sah gradual channel approximation and the full-depletion approximation. The proposed model captures the phenomenon of the bulk conduction mechanism in all regions of device operation (subthreshold, linear, and saturation regions). It has been shown that the continuous model is in complete agreement with the numerical simulations.

Interface Trap Density of Gate-All-Around Silicon Nanowire Field-Effect Transistors With TiN Gate: Extraction and Compact Model

Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface trap charge distribution of cylindrical cross-sectioned gate-all-around silicon nanowire field-effect transistor is extracted by using three-dimensional simulation. While the interface chemistry of conventional gatestack ( Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> polysilicon) in conventional planar devices is well documented, not much work is available on interface trap distribution Dit of alternate gatestacks (gatestacks employing alternate gate materials) in silicon nanowire MOSFET devices. Furthermore, a compact drain current model with interface trap charge parameter is presented. The model is based on gradual channel approximation and uses self-consistent calculation of interface trap charge and surface potential to reproduce experimental current-voltage characteristics.

Three-terminal capacitance–voltage measurements of pentacene field-effect transistors during operation

We propose a modified measurement technique of capacitance for three-terminal devices and apply this method for the evaluation of the channel formation in pentacene field-effect transistors. An additional structure in the capacitance–voltage curves clearly shows the channel formation from the saturation to the linear region in an operating transistor which has not been directly observed in conventional methods. Based on the amount of accumulated charge in the channel region, the validity of the gradual channel approximation model and the usability of a buffer layer are discussed. This method enables the detailed investigation of carrier behaviors in organic transistors through appropriate evaluation of the channel formation process during operation.

A compact charge-based model to study the nanoscale undoped double gate MOSFETs for nanoelectronic circuit design using genetic algorithms

The analytical modeling of nanoscale devices is an important area of computer-aided design for fast and accurate nanoelectronic design and optimization. In the present paper, a new approach for modeling semiconductor devices, nanoscale double gate DG MOSFETs, by use of the gradual channel approximation (GC) approach and genetic algorithm optimization technique (GA) is presented. The proposed approach combines the universal optimization and fitting capability of GA and the cost-effective optimization concept of quantum correction, to achieve reliable, accurate and simple compact models for nanoelectronic circuit simulations. Our compact models give good predictions of the quantum capacitance, threshold voltage shift, quantum inversion charge density and drain current. These models have been verified with 2D self-consistent results from numerical calculations of the coupled Poisson-Schrödinger equations. The developed models can also be incorporated into nanoelectronic circuit simulators to study the nanoscale CMOS-based devices without impact on the computational time and data storage.

Physical compact modeling for threshold voltage of strained Si NMOSFET

The development of strained-Si physical compact threshold voltage model is based on Poisson's equation, using the gradual channel approximation (GCA) and coherent quasi-two-dimensional (2D) analysis, as well as taking into account the effects of short channel effect (SCE), narrow channel effect (NCE), non-uniform doping effect, and drain-induced barrier lowering (DIBL) effect. Moreover, the threshold voltage parameters are extracted from the experimental results by software. Finally, the validity of our model is derived from the comparison of our simulation results. The proposed model may be useful for the design and simulation of very large scale integrated circuits (VLSI) made of strained-Si.

Potential distribution in channel of thin-film transistors

Channel voltages of ZnO thin-film transistors during operation are precisely probed at two trisecting positions between the source and drain electrode, which exactly corresponds to characteristic transistor events, such as carrier injection, carrier accumulation, pinch-off formation, and drain current saturation. Furthermore, a simple numerical calculation based on the gradual channel approximation and the current continuity equation reveals that the channel voltages have a non-linear potential distribution and an intrinsic but significant potential drop in the region near to the drain electrode in most of the linear regime.

Analysis of contact effects in fully printed p-channel organic thin film transistors

Contact effects have been analyzed in fully printed p-channel OTFTs based on a pentacene derivative as organic semiconductor and with Au source–drain contacts. In these devices, contact effects lead to an apparent decrease of the field effect mobility with decreasing L and to a failure of the gradual channel approximation (GCA) in reproducing the output characteristics. Experimental data have been reproduced by two-dimensional numerical simulations that included a Schottky barrier (Φb=0.46eV) at both source and drain contacts and the effects of field-induced barrier lowering. The barrier lowering was found to be controlled by the Schottky effect for an electric field E<105V/cm, while for higher electric fields we found a stronger barrier lowering presumably due to other field-enhanced mechanisms. The analysis of numerical simulation results showed that three different operating regimes of the device can be identified: (1) low |Vds|, where the channel and the Schottky diodes at both source and drain behave as gate voltage dependent resistors and the partition between channel resistance and contact resistance depends upon the gate bias; (2) intermediate Vds, where the device characteristics are dominated by the reverse biased diode at the source contact, and (3) high |Vds|, where pinch-off of the channel occurs at the drain end and the transistor takes control of the current. We show that these three regimes are a general feature of the device characteristics when Schottky source and drain contacts are present, and therefore the same analysis could be extended to TFTs with different semiconductor active layers.

Gradual channel approximation models for organic field-effect transistors: The space-charge field effect

The gradual channel approximation is widely used for organic field-effect transistors with an assumption of linear potential profile across the channel. However, this is in contradiction with reported potential profiles. Here, we discuss linear and nonlinear potential profiles in the meaning of the space-charge field generated by injected carriers. The influence on current-voltage relation used for mobility evaluation in linear and saturated regions is proposed as well as transition between these states. In addition, the effect of the space-charge on the potential drop and field around the drain electrode in the saturation region is discussed.

Contact effects in high performance fully printed p-channel organic thin film transistors

Contact effects have been investigated in fully printed p-channel organic thin film transistors with field effect mobility up to 2 cm2/Vs. Electrical characteristics of the organic thin film transistors, with channel length &amp;lt;200 μm, are seriously influenced by contact effects with an anomalous increase of the contact resistance for increasing source-drain voltage. Assuming that contact effects are negligible in long channel transistors and using gradual channel approximation, we evaluated the current-voltage characteristics of the injection contact, showing that I-V characteristics can be modeled as a reverse biased Schottky diode, including barrier lowering induced by the Schottky effect.

A unified short-channel compact model for cylindrical surrounding-gate MOSFET

For the first time, a continuous and explicit model valid in all operating regions, for undoped short-channel cylindrical gate-all-around (GAA) MOSFETs, is presented in this study. From a two-dimensional analysis, the threshold voltage roll-off, the drain-induced barrier lowering (DIBL) and the subthreshold swing are explicitly modeled. Short-channel effects are then implemented into a continuous drain-current model based on an effective surface potential approach using the gradual channel approximation. Improving the model behavior in the saturation operating region by accounting the channel pinch-off displacement, channel length modulation is studied and implemented as well. Analytical results are compared to TCAD-Atlas numerical simulations and validate the short-channel model in all operating modes making it suitable for circuit design simulations.

Transconductance characteristics and plasma oscillations in nanometric InGaAs field effect transistors

AbstractBy Monte Carlo simulations we investigate the plasma spectrum in n-type InGaAs field effect transistors at 300K in the whole region of operating conditions from ohmic to saturation regime of the transconductance characteristics. The presence of a two dimensional (2D) plasma peak predicted within the gradual channel approximation is confirmed by the microscopic model and its properties are analyzed systematically. At the highest gate voltages the 2D peak is found to become practically independent of the channel width.

Drifting-Dipole Noise (DDN) Model of MOSFETs for Microwave Circuit Design

Physic-based formulations for the high-frequency noise characteristics of nanometer MOSFETs working at saturation are developed. In the derivation, field-dependent mobility, as well as carrier heating effect in the gradual channel approximation region, is taken into account. In addition, diffusion noise due to velocity saturation carriers in the high electric field region is calculated using Statz's drifting dipole theory. Excellent agreement between the proposed model and experimental noise data for 120-nm MOSFET technology was obtained over device sizes, biases, and frequencies up to 26 GHz. The analytical noise model can be incorporated into any compact model to enable first-pass silicon design of microwave circuit.

Novel Device Concepts for Nanotechnology: The Nanowire Pinch-Off FET and Graphene TunnelFET

We explain the basic operation of a nanowire pinch-off FET and graphene nanoribbon tunnelFET. For the nanowire pinch-off FET we construct an analytical model to obtain the threshold voltage as a function of radius and doping density. We use the gradual channel approximation to calculate the current-voltage characteristics of this device and we show that the nanowire pinch-off FET has a subthreshold slope of 60 mV/dec and good ION and ION/IOFF ratios. For the graphene nanoribbon tunnelFET we show that an improved analytical model yields more realistic results for the transmission probability and hence the tunneling current. The first simulation results for the graphene nanoribbon tunnelFET show promising subthreshold slopes.

A comprehensive analytical study of an undoped symmetrical double-gate MOSFET after considering quantum confinement parameter

This paper presents analytical models of threshold voltage, carrier concentration and drain current for undoped symmetrical double-gate (SDG) MOS devices. The analytical models are derived after solving the Poisson’s equation under Gradual Channel Approximation (GCA). Quantum mechanical effect in ultrathin silicon film is studied by introducing quantum confinement parameter and quantum corrected potential in the Poisson’s equation instead of solving complex Schrödinger–Poisson’s equation. The confinement parameter, which depends on film thickness, work function and gate bias decreases with film thickness. Quantum corrected potential attains its maximum value near the interface and minimum value at the centre of the silicon film. The mobile carrier density and surface potential are reduced due to quantum confinement effect. The simulation result of the threshold voltage shows excellent agreement with quantum numerical results.

Monte Carlo investigation of terahertz plasma oscillations in gated ultrathin channel of n-InGaAs

By numerical simulations we investigate the dispersion of the plasma frequency in a gated channel of n-type InGaAs layer of thickness W and submicron length L at T=300 K. In the presence of a source-drain voltage and for a carrier concentrations of 1018 cm−3 the spectra evidences a peaked shape with two main bumps, the former at high frequency corresponding to the three-dimensional plasma frequency and the latter at a low frequency. The frequency value of the latter peak exhibits a dispersion as the inverse of the channel length in agreement with the predictions of gradual channel approximation. At increasing drain voltages the instabilities associated with the presence of Gunn domains are responsible for a suppression of the plasma peak in favor of the onset of a peak in the subterahertz domain associated with transit time effects.