Scaling interconnects to increase device density is a critical bottle neck for a range of applications from complementary metal oxide semiconductor (CMOS) to microelectromechanical (MEMS) switches and other devices. Currently, Cu is the interconnect metal of choice to fill vias but comes with significant challenges. To perform the fill, first a diffusion barrier is applied to ensure Cu leakage does not cause electrical breakdown between vias, then a metal seed layer is used to ensure smooth and dense Cu electroplating. Uniform seed resistivity, which can be correlated to thickness, is critical to produce low resistivity interconnects, free of voids. Unfortunately, state-of-the-art processes for high quality metallic films are limited to line-of-site techniques like chemical vapor deposition (CVD) or physical vapor deposition (PVD), limiting possible device pitch and architectures. When the aspect ratio increases above ~8:1 or there is a shadow, typically one of the layers is missing, resulting in insufficiently thin seed for successful Cu electroplating nucleation. This deficiency creates a void or produces a thickness gradient, resulting in pinch-off at the top. Ultimately, the device fails due to high line resistance or full dielectric breakdown. Fortunately, atomic layer deposition (ALD) can produce high density and low resistivity metal films for both Cu diffusion barrier and Cu electroplating seed applications. Here we report on a total solution to this problem using only thermal ALD. Adoption of ALD of metals has been slow in the market as traditional ALD reactors can be too slow and inefficient for production requirements or require plasma for sufficient film quality. Plasma enhanced ALD (PEALD) can produce quality films at a reasonable thermal budget, unfortunately every plasma process will have a limit to the aspect ratio that can be coated conformally and there is additional risk of surface plasma damage. Forge Nano has demonstrated single wafer thermal ALD technology to improve the speed and efficiency of ALD metal films, enabling a production worthy process. In this work a complete Cu barrier-seed stack solution has been demonstrated on Si vias ranging from 4:1 to 25:1 aspect ratio, showing successful Cu electroplating. A SiO2 ALD film, with a deposition rate of 10 nm/min, is first deposited to provide a dielectric barrier, then a thin TiN layer is applied as a Cu diffusion barrier, followed by a low resistivity Ru film for Cu adhesion. A novel TiN thermal ALD process at 300°C has been developed which decreases the as-deposited resistivity from ~1200 to <300 uΩ·cm at a deposition rate >1 nm/min. In addition, a high-quality Ru film has been developed with resistivity values <20 uΩ·cm and can be deposited on SiO2, HfO2, Pt, and TiN. An example of success as a total Cu barrier/seed stack for Cu electroplating in Si trenches is shown in Figure 1. When compared to PVD Ti/W barrier and Cu seed, the ALD stack produces dense, void free nucleation of Cu that remains well adhered to the via. However, the PVD stack has voids at the bottom of the trench from poor adhesion of electroplated Cu and narrowing at the top from a resistivity gradient within the trench, resulting in eventual pinch-off. From this comparison, it can be observed that the ALD Ru provides sufficient adhesion for Cu electroplating and that resistivity of the ALD Ru/TiN stack is sufficiently low and consistent for conformal and dense Cu electroplating. We expect this work to open up higher aspect ratio interconnects and possible new device architecture to the market. Figure 1
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Nov 28, 2024
Hosseinali Ghari + 5
Open Access
