Good Speedup Research Articles

Parallel probabilistic relaxation labelling based on Markov random fields for spectral-spatial hyperspectral image classification

ABSTRACTThe large volume of data and computational complexity of algorithms limit the application of hyperspectral image classification to real-time operations. This work addresses the use of different parallel processing techniques to speed up the Markov random field (MRF)-based method to perform spectral-spatial classification of hyperspectral imagery. The Metropolis relaxation labelling approach is modified to take advantage of multi-core central processing units (CPUs) and to adapt it to massively parallel processing systems like graphics processing units (GPUs). The experiments on different hyperspectral data sets revealed that the implementation approach has a huge impact on the execution time of the algorithm. The results demonstrated that the modified MRF algorithm produced classification accuracy similar to conventional methods with greatly improved computational performance. With modern multi-core CPUs, good computational speed-up can be achieved even without additional hardware support. The CPU-GPU hybrid framework rendered the otherwise computationally expensive approach suitable for time-constrained applications.

Computational Algorithms for Solving Spectral/$hp$ Stabilized Incompressible Flow Problems

In this paper we implement the element-by-element preconditioner and inexact Newton-Krylov methods (developed in the past) for solving stabilized computational fluid dynamics (CFD) problems with spectral methods. Two different approaches are implemented for speeding up the process of solving both steady and unsteady incompressible Navier-Stokes equations. The first approach concerns the application of a scalable preconditioner namely the element by element LU preconditioner, while the second concerns the application of Newton-Krylov (NK) methods for solving non-linear problems. We obtain good agreement with benchmark results on standard CFD problems for various Reynolds numbers. We solve the Kovasznay flow and flow past a cylinder at Re-$100$ with this approach. We also utilize the Newton-Krylov algorithm to solve (in parallel) important model problems such as flow past a circular obstacle in a Newtonian flow field, three dimensional driven cavity, flow past a three dimensional cylinder with different immersion lengths. We explore the scalability and robustness of the formulations for both approaches and obtain very good speedup. Effective implementations of these procedures demonstrate for relatively coarse macro-meshes<br />the power of higher order methods in obtaining highly accurate results in CFD. While the procedures adopted in the paper have been explored in the past the novelty lies with applications with higher order methods which have been known to be computationally intensive.

A distributed approach for graph mining in massive networks

We propose a novel distributed algorithm for mining frequent subgraphs from a single, very large, labeled network. Our approach is the first distributed method to mine a massive input graph that is too large to fit in the memory of any individual compute node. The input graph thus has to be partitioned among the nodes, which can lead to potential false negatives. Furthermore, for scalable performance it is crucial to minimize the communication among the compute nodes. Our algorithm, DistGraph, ensures that there are no false negatives, and uses a set of optimizations and efficient collective communication operations to minimize information exchange. To our knowledge DistGraph is the first approach demonstrated to scale to graphs with over a billion vertices and edges. Scalability results on up to 2048 IBM Blue Gene/Q compute nodes, with 16 cores each, show very good speedup.

Partial Element Equivalent Circuit-Based Transient Analysis of Graphene-Based Interconnects

This paper presents a three-dimensional time-domain formulation of the partial element equivalent circuit (PEEC) method to model graphene-based interconnects. The frequency-dependent electrical conductivity is incorporated into the time-domain solver by resorting to a fitting process. It is proved that if only the intraband contribution to the electrical conductivity is considered, no additional unknowns are required with respect to a standard PEEC solver. If also the interband is to be modeled, auxiliaries unknowns are introduced to reproduce the dynamic of the material. Numerical examples are presented to validate and demonstrate the capabilities and advantages of the proposed approach. The comparison with a finite element method implementation and also with the frequency-domain PEEC solver shows a satisfactory agreement and a good speedup with respect to the frequency-domain counterpart.

Graphics processing unit-accelerated joint-bitplane belief propagation algorithm in DSC

The M-ary source with nonstationary correlation can be encoded with a single binary low-density parity-check (LDPC) code and decoded together in distributed source coding. The joint-bitplane belief propagation (JBBP) is a useful decoding algorithm for multiple bitplanes of an M-ary source. However, it suffers from the drawbacks of low computational efficiency and long execution time. Motivated by the evolution of the Graphics Processing Unit (GPU) and the inherent parallel characteristic of the JBBP, we propose a novel approach for the computationally intensive processing of the JBBP algorithm on GPU using the compute unified device architecture programming model. Two different parallel modes are utilized for the belief passing between different nodes of the JBBP. It is found that the bottlenecks of the JBBP lie in computing the overall probability mass functions (pmfs) of symbol nodes and the overall beliefs of bit nodes. Thus, a data partitioning method is leveraged to split a large array of pmfs into small pieces which can be loaded into L1 cache instead of global memory. The optimal block size is selected which not only assigns as large L1 cache as possible for individual thread, but also guarantees multiple active warps in each stream multiprocessor. Experimental results show that when the length-6336 (length-50,688, resp.) LDPC accumulate (LDPCA) code is used to compress the source, the JBBP decoder can achieve about 20$$\times $$× (41$$\times $$×, resp.) speedup on GPU compared with the original C code on CPU. Better performance would be further obtained with longer LDPCA codes. Moreover, the parallel JBBP is also applied in hyperspectral image compression and video coding and it shows good speedup performance.

Locating All Common Subsequences in Two DNA Sequences

Biological sequence comparison is one of the most important and basic problems in computational biology. Due to its high demands for computational power and memory, it is a very challenging task. The well-known algorithm proposed by Smith-Waterman obtains the best local alignments at the expense of very high computing power and huge memory requirements. This paper introduces a new efficient algorithm to locate the longest common subsequences (LCS) in two different DNA sequences. It is based on the convolution between the two DNA sequences: The major sequence is represented in the linked-list X while the minor one is represented in circular linked-list Y. An array of linked lists is established where each linked list is corresponding to an element of the linked-list X and a new node is added to it for each match between the two sequences. If two or more matches in different locations in string Y share the same location in string X, the corresponding nodes will construct a unique linked-list. Accordingly, by the end of processing, we obtain a group of linked-lists containing nodes that reflect all possible matches between the two sequences X and Y. The proposed algorithm has been implemented and tested using C# language. The benchmark test shows very good speedups and indicated that impressive improvements has been achieved.

Embedded Coprocessors for Native Execution of Geometric Algebra Operations

Clifford algebra or geometric algebra (GA) is a simple and intuitive way to model geometric objects and their transformations. Operating in high-dimensional vector spaces with significant computational costs, the practical use of GA requires dedicated software and/or hardware architectures to directly support Clifford data types and operators. In this paper, a family of embedded coprocessors for the native execution of GA operations is presented. The paper shows the evolution of the coprocessor family focusing on the latest two architectures that offer direct hardware support to up to five-dimensional Clifford operations. The proposed coprocessors exploit hardware-oriented representations of GA elements and operators properly conceived to obtain fast performing implementations. The coprocessor prototypes, implemented on field programmable gate arrays development boards, show significant speedups of about one order of magnitude with respect to the baseline software library Gaigen running on a general-purpose processor. The paper also presents an execution analysis of different GA-based applications, namely inverse kinematics of a robot, optical motion capture, raytracing, and medical image processing, showing good speedups with respect to the baseline general-purpose implementation.

Using the Xeon Phi Platform to Run Speculatively-Parallelized Codes

Intel Xeon Phi accelerators are one of the newest devices used in the field of parallel computing. However, there are comparatively few studies concerning their performance when using most of the existing parallelization techniques. One of them is thread-level speculation, a technique that optimistically tries to extract parallelism of loops without the need of a compile-time analysis that guarantees that the loop can be executed in parallel. In this article we evaluate the performance delivered by an Intel Xeon Phi coprocessor when using a software, state-of-the-art thread-level speculative parallelization library in the execution of well-known benchmarks. We describe both the internal characteristics of the Xeon Phi platform and the particularities of the thread-level speculation library being used as benchmark. Our results show that, although the Xeon Phi delivers a relatively good speedup in comparison with a shared-memory architecture in terms of scalability, the relatively low computing power of its computational units when specific vectorization and SIMD instructions are not fully exploited makes this first generation of Xeon Phi architectures not competitive (in terms of absolute performance) with respect to conventional multicore systems for the execution of speculatively parallelized code.

Measuring the Efficiency of Parallel Discrete Event Simulation in Heterogeneous Execution Environments

This paper deals with the experimental testing and verification of the earlier proposed load balancing and coupling factor criteria for the conservative parallel discrete event simulation in heterogeneous execution environments whether they can ensure a good speedup. The definition of the relative speedup is extended to the heterogeneous systems in a natural way. This definition is used to measure the efficiency of the parallel simulation executed by heterogeneous systems. A closed queueing network is used as the simulation model. It is demonstrated on the example of a heterogeneous system containing 134 CPU cores of 6 different types of computers that a good speedup can be achieved using the load balancing and coupling factor criteria. It is shown that the extension of the definition of the relative speedup to the heterogeneous systems made it easy to judge the speedup of parallel discrete event simulation in heterogeneous execution environments.

J2M: a Java to MapReduce translator for cloud computing

Cloud computing has gradually evolved into an infrastructural tool for a variety of scientific research and computing. It has become a trend that lots of products have been migrated from local servers to cloud by many institutions and organizations. One of the challenges in cloud computing now is how to run software efficiently on cloud platforms since lots of original codes are not capable of being executed in parallel on cloud contexts, resulting in that the power of clouds cannot be exerted well. It is costly to redesign and convert current sequential codes into cloud platform. Thus, automatic translation from sequential code to cloud code is one of the directions that could be taken to resolve the problem of code migration in cloud infrastructure. In this paper, a new Java to MapReduce (J2M) translator is developed to achieve the automatic translation from sequential Java to cloud for specific data-parallel code with large loops. This paper will provide details about the design of our translator and evaluate our performance through experiments. The experimental results not only indicate that the translator can precisely translate the sequential Java into cloud codes, but also show that it can achieve very good speedup in performance, and we expect that an almost linear speedup is possible if larger enough data is processed. It is believed that the J2M translator is an ideal stereotype for code migration and will play an important role in the transition era of cloud computing.

Parallel generation of meshes with cracks using binary spatial decomposition

This work describes a technique to generate tetrahedral meshes with cracks using parallel computers with distributed memory. This technique can be used for models without cracks as well. It employs a binary partitioning structure that uses axis-aligned planes to decompose the domain. Those decomposing planes are determined based on a refined octree that is built to estimate the amount of work necessary to generate the whole mesh, so that the amount of work in each subdomain is approximately the same. A serial advancing front technique is used in each subdomain concurrently, in such a way that the generated tetrahedra do not cross the decomposing planes. After local synchronizations, meshes are generated interfacing the subdomains. The results show that the prediction of the number of elements in each subdomain is accurate, leading to a well-balanced algorithm and to a good speed-up. Also, the meshes generated in parallel have very good quality, similar to the that of a serially generated mesh.

Concurrent hash tables

Concurrent hash tables are one of the most important concurrent data structures with numerous applications. Since hash table accesses can dominate the execution time of the overall application, we need implementations that achieve good speedup. Unfortunately, currently available concurrent hashing libraries turn out to be far away from this requirement in particular when contention on some elements occurs. Our starting point for better performing data structures is a fast and simple lock-free concurrent hash table based on linear probing that is limited to word-sized key-value types and does not support dynamic size adaptation. We explain how to lift these limitations in a provably scalable way and demonstrate that dynamic growing has a performance overhead comparable to the same generalization in sequential hash tables. We perform extensive experiments comparing the performance of our implementations with six of the most widely used concurrent hash tables. Ours are considerably faster than the best algorithms with similar restrictions and an order of magnitude faster than the best more general tables. In some extreme cases, the difference even approaches four orders of magnitude.

Distributed Global Function Model Finding for Wireless Sensor Network Data

Function model finding has become an important tool for analysis of data collected from wireless sensor networks (WSNs). With the development of WSNs, a large number of sensors have been widely deployed so that the collected data show the characteristics of distribution and mass. For distributed and massive sensor data, traditional centralized function model finding algorithms would lead to a significant decrease in performance. To solve this problem, this paper proposes a distributed global function model finding algorithm for wireless sensor network data (DGFMF-WSND). In DGFMF-WSND, on the basis of gene expression programming (GEP), an adaptive population generation strategy based on sub-population associated evolution is applied to improve the convergence speed of GEP. Secondly, to solve the generation of global function model in distributed wireless sensor networks data, this paper provides a global model generation algorithm based on unconstrained nonlinear least squares. Four representative datasets are used to evaluate the performance of the proposed algorithm. The comparative results show that the improved GEP with adaptive population generation strategy outperforms all other algorithms on the average convergence speed, time-consumption, value of R-square, and prediction accuracy. Meanwhile, experimental results also show that DGFMF-WSND has a clear advantage in terms of time-consumption and error of fitting. Moreover, with increasing of dataset size, DGFMF-WSND also demonstrates good speed-up ratio and scale-up ratio.

Multivariate Polynomial Multiplication on GPU

Multivariate polynomial multiplication is a fundamental operation which is used in many scientific domains, for example in the optics code for particle accelerator design at CERN. We present a novel and efficient multivariate polynomial multiplication algorithm for GPUs using floating-point double precision coefficients implemented using the CUDA parallel programming platform. We obtain very good speedups over another multivariate polynomial multiplication library for GPUs (up to 548x), and over the implementation of our algorithm for multi-core machines using OpenMP (up to 7.46x).

An Improved Backward SBR-PO/PTD Hybrid Method for the Backward Scattering Prediction of an Electrically Large Target

An improved hybrid method of backward shooting and bouncing ray (SBR) physical optics (PO)/physical theory of diffraction (PTD) is proposed to investigate the backward scattering from a three-dimensional electrically large target. The basic idea is to combine the forward-ray-tracing technique to accelerate the original backward-ray-tracing one. The proposed method significantly reduces the computational complexity while ensuring the same computational accuracy with the traditional backward SBR method. The accuracy and performance of our method are validated and evaluated by comparison with the exact computational electromagnetic method (FEKO-MLFMM) and experimental data for electrically small targets. The last case for the warship model illustrates that our method can enable good speedup for electrically large complex objects.

A high performance hardware accelerator for dynamic texture segmentation

The major contribution of this paper is the development of a hardware (FPGA) software (CPU) co-design architecture for accelerating the application of Dynamic Texture Segmentation.This work presents a FPGA implementation of FFT processing sub-system including FFT/IFFT processors, read/write control modules, and memory/FIFO modules, as well as memory optimization using local FIFOs to minimize external RAM access. Such FPGA implementation fully exploits the hardware acceleration technique. All FFT and related operations are executed in hardware which should run orders of magnitude faster than the software implementation.This paper demonstrates that the FPGA-CPU based solution is 37.3 times faster in data processing time and 5.9 times faster in total run time, compared to the CPU (CPU-GPU) based solution. Hardware accelerators such as general-purpose GPUs and FPGAs have been used as an alternative to conventional CPU architectures in scientific computing applications, and have achieved good speed-up results. Within this context, the present study presents a heterogeneous architecture for high-performance computing based on CPUs and FPGAs, which efficiently explores the maximum parallelism degree for processing video segmentation using the concept of dynamic textures. The video segmentation algorithm includes processing the 3-D FFT, calculating the phase spectrum and the 2-D IFFT operation. The performance of the proposed architecture based on CPU and FPGA is compared with the reference implementation of FFTW in CPU and with the cuFFT library in GPU. The performance report of the prototyped architecture in a single Stratix IV FPGA obtained an overall speedup of 37x over the FFTW software library.

An efficient approach to collaborative simulation of variable structure systems on multi-core machines

Complex variable-structure systems (CVSSs) are a common type of complex systems that exhibit changes both at structural and behavior levels. Simulations of CVSSs challenge current collaborative execution methods with increasingly big and complex models. The emergence of multi-core paradigm presents an exciting opportunity to address such challenge, so an advanced parallel simulator under multi-core environments is proposed. The simulator: (1) provides thread simulation kernels and five kinds of management services to support dynamic model structure flexibly; (2) can explore both inherent and dynamic parallelism among models based on interaction relations, and employ the multi-thread paradigm to gain good speedup; (3) adopts an efficient dynamic load-balancing method, which can migrate models among cores with very low cost and support dynamic core allocation on demand, to address evident load-imbalance problems brought by variable-structure. The experiments show that structure changes can be supported while up to 23 % performance increase can be gained.

Parallel improved quantum inspired evolutionary algorithm to solve large size Quadratic Knapsack Problems

Quadratic Knapsack Problem (QKP), an extension of the canonical simple Knapsack Problem, is NP Hard in the stronger sense. No pseudo-polynomial time algorithm is known to exist which can solve QKP instances. QKP has been studied intensively due to its simple structure yet challenging difficulty and numerous applications. A few attempts have been made to solve large size instances of QKP due to its complexity. Quantum Inspired Evolutionary Algorithm (QIEA) provides a generic framework that has often been carefully tailored for a given problem to obtain an effective implementation. In this work, an improved and parallelized QIEA, dubbed IQIEA-P is presented. Several additional features make it more balanced in exploration and exploitation and thus have better applicability. Computational experiments are presented on large QKP instances of 1000 and 2000 items. The improvements are inherently parallelizable and, therefore, good speedups are obtained on a multi-core machine. No parallel algorithm is available for QKP. The solutions provided by QIEA-P are competitive with those obtained from the state of the art algorithm.

Data decomposition method for parallel polygon rasterization considering load balancing

It is essential to adopt parallel computing technology to rapidly rasterize massive polygon data. In parallel rasterization, it is difficult to design an effective data decomposition method. Conventional methods ignore load balancing of polygon complexity in parallel rasterization and thus fail to achieve high parallel efficiency. In this paper, a novel data decomposition method based on polygon complexity (DMPC) is proposed. First, four factors that possibly affect the rasterization efficiency were investigated. Then, a metric represented by the boundary number and raster pixel number in the minimum bounding rectangle was developed to calculate the complexity of each polygon. Using this metric, polygons were rationally allocated according to the polygon complexity, and each process could achieve balanced loads of polygon complexity. To validate the efficiency of DMPC, it was used to parallelize different polygon rasterization algorithms and tested on different datasets. Experimental results showed that DMPC could effectively parallelize polygon rasterization algorithms. Furthermore, the implemented parallel algorithms with DMPC could achieve good speedup ratios of at least 15.69 and generally outperformed conventional decomposition methods in terms of parallel efficiency and load balancing. In addition, the results showed that DMPC exhibited consistently better performance for different spatial distributions of polygons.

Affine Parallelization Using Dependence and Cache Analysis in a Binary Rewriter

Today, nearly all general-purpose computers are parallel, but nearly all software running on them is serial. Bridging this disconnect by manually rewriting source code in parallel is prohibitively expensive. Hence, automatic parallelization is an attractive alternative. We present a method to perform automatic parallelization in a binary rewriter. The input to the binary rewriter is the serial binary executable program and the output is a parallel binary executable. The advantages of parallelization in a binary rewriter versus a compiler include: (i) applicability to legacy binaries whose source is not available; (ii) applicability to library code that is often distributed only as binary; (iii) usability by end-user of the software; and (iv) applicability to assembly-language programs. Adapting existing parallelizing compiler methods that work on source code to binaries is a significant challenge. This is primarily because symbolic and array index information used by existing parallelizing compilers to take parallelizing decisions is not available from a binary. We show how to adapt existing parallelization methods to binaries without using symbolic and array index information to achieve equivalent source parallelization from binaries. Results using our x86 binary rewriter called SecondWrite are presented in detail for the dense-matrix and regular Polybench benchmark suite. For these, the average speedup from our method for binaries is 27.95X versus 28.22X from source on 24 threads, compared to the input serial binary. Super-linear speedups are possible due to cache optimizations. In addition our results show that our method is robust and has correctly parallelized much larger binaries from the SPEC 2006 and OMP 2001 benchmark suites, totaling over 2 million source lines of code (SLOC). Good speedups result on the subset of those benchmarks that have affine parallelism in them; this subset exceeds 100,000 SLOC. This robustness is unusual even for the latest leading source parallelizers, many of which are famously fragile.