Globally Asynchronous Locally Synchronous Systems Research Articles

A GALS design based on multi-frequency clocking for digital switching noise reduction

In this paper, we investigate two design techniques to reduce the digital switching noise on the power supply lines: a multi-frequency clocking (MFC) and a globally asynchronous locally synchronous (GALS) design technique. By deploying an MFC design, we can spread the switching current peaks over a frequency band, which results in the supply noise reduction. With the use of a GALS technique, we partition a large synchronous design into some smaller locally synchronous modules (LSMs) which are clocked by their own local clocks. Each local clock signal can be different from the other in terms of frequency or phase. Thus, we can also distribute the digital switching activities inside circuits over time, which leads to the supply noise reductions. The experimental results on a commercial Field Programmable Gate Array (FPGA) Spartan-3 (XC3S400-TQ144) show that the noise reduction rates can be achieved up to 17.4 dB for a GALS system with 8 LSMs, and 19.2 dB for the joint use of the MFC and GALS techniques with 4 LSMs. Moreover, as a real design example, a DES crypto processor with the deployment of GALS design and multi-frequency clocking strategy is also implemented and evaluated. The noise reduction rate is achieved about 19.5 dB at the fundamental frequency.

A Multi-Synchronous Bi-Directional NoC (MBiNoC) architecture with dynamic self-reconfigurable channel for the GALS infrastructure

To enhance the performance of on-chip communications of Globally Asynchronous Locally Synchronous Systems (GALS), a dynamic reconfigurable multi-synchronous router architecture is proposed to increase network on chip (NoC) efficiency by changing the path of the communication link in the runtime traffic situation. In order to address GALS issues and bandwidth requirements, the proposed multi-synchronous bidirectional NoC’s router is developed and it guarantees higher packet consumption rate, better bandwidth utilization with lower packet delivery latency. All the input/output ports of the proposed router behave as a bi-directional ports and communicate through a novel multi-synchronous first-in first-out (FIFO) buffer. The bidirectional port is controlled by a dynamic channel control module which provides a dynamic reconfigurable channel to the router itself and associated sub-modules. This proposed multi-synchronous bidirectional router architecture is synthesized using Xilinx ISE 14.7 and FPGA Virtex 6 family device XC6VLX760 is considered as target technology and its performance is evaluated in terms of power, area and delay.

Formal modelling and verification of GALS systems using GRL and CADP

Abstract A GALS ( Globally Asynchronous, Locally Synchronous ) system consists of several synchronous components that evolve concurrently and interact with each other asynchronously. The design of GALS systems is tedious and error-prone due to the high degree of synchronous and asynchronous concurrency present in complex architectures. In this paper, we present GRL ( GALS Representation Language ), a formal language designed to model GALS systems, for the purpose of formal verification of the asynchronous aspects. GRL combines the synchronous reactive model underlying dataflow languages and the asynchronous concurrent model underlying process algebras. We propose a translation from GRL to LNT, a value-passing concurrent language with classical process algebra flavour. This makes possible the analysis of GRL specifications using all the state-of-the-art simulation and verification functionalities provided by the CADP toolbox.

Timed Behavioral Specification in Globally Asynchronous Locally Synchronous systems

In this paper, we propose a PolGALS language for safety critical GALS(Globally Asynchronous Locally Synchronous) systems. The formal syntax and semantics are given and its compilation and implementation are defined. The language is based on timed CSP(communicating sequential process) style rendezvous between clock domains, aiming at modelling the timed behavioral of safety critical GALS systems. PolGALS is used to design timed behavioral pattern to implement timing requirements, e.g. delay, timeout, deadline, timed interrupt,etc. PolGALS provides a mechanism for implementation of timed behavioral pattern and potential for their formal verification because it is based on a PolGALS model of computation and its formal semantics. DOI: http://dx.doi.org/10.11591/telkomnika.v11i9.3257 Full Text: PDF

An Asynchronous Interface with Robust Control for Globally-Asynchronous Locally-Synchronous Systems

Contemporary digital systems must necessarily be based on the System-on-Chip (SoC) concept. Especially in relation to the aerospace industry, these systems must overcome some additional engineering challenges concerning reliability, safety and low power. An interesting style for aerospace SoC design is the GALS (Globally Asynchronous, Locally Synchronous) paradigm, which can be used for Very Large Scale Integration - Deep-Sub-Micron (VLSI_DSM) design. Currently, the major drawback in the design of a GALS system is the asynchronous interface (asynchronous wrapper - AW) when being implemented in VLSI_DSM. There is a typical AW design style based on asynchronous controllers that provides communication between modules (called ports), but the port controllers are generally subjected to essential hazard, what decreases the reliability and safety of the full system. Concerning to this main drawback, this paper proposes an AW with robust port controller that shows to be free of essential hazard, besides allowing full autonomy for the locally synchronous modules, creating fault tolerant systems as much as possible. It follows the Delay Insensitive (DI) model interacting with the environment in the Generalized Fundamental Mode (GFM) without the need to insert any delay elements. Additional delay elements, although proposed by some previous work found in literature, are not desirable in aerospace applications. The proposed interface allows working on Ib/Ob mode, showing the DI model is more robust than the QDI model and, therefore, it does not need to meet isochronic fork requirements nor timing analysis. Once an interface presenting similar properties was not found in literature, the proposed architecture proved to have great potential of implementation in practical VLSI_DSM designs, including the aerospace ones, once it overcomes the main engineering challenges of this kind of industry.

Localities in systems with a/sync communication

Localities and a/sync places are two recent extensions to the Petri net model. Whereas localities have been introduced as a modelling tool for membrane systems and more general GALS (globally asynchronous locally synchronous) systems, a/sync places make it possible to model synchronous communication between transitions. We investigate the interaction between locally synchronous execution and synchronous communication. Our focus is in particular on the causalities in the concurrent runs of a new Petri net model combining these features.

A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors

A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous locally synchronous (GALS) clocking styles. To achieve a low area cost, the proposed statically-configurable asymmetric architecture assigns large buffer resources to only the nearest neighbor interconnect and much smaller buffer resources for long distance interconnect. To maintain flexible routing capability, each neighboring processor pair has multiple connecting links. The architecture supports long distance communication in GALS systems by transferring the source clock with the data signals along the entire path for write synchronization. Compared to a traditional dynamically-configurable interconnect architecture with symmetric buffer allocation and single-links between neighboring processor pairs, this implementation has approximately two times smaller communication circuitry area with a similar routing capability. Area and speed estimates are obtained with the physical design of seven chips in 0.18-¿m CMOS.

Minimal Regions of ENL-Transition Systems

One of the possible ways of constructing concurrent systems is their automated synthesis from behavioural specifications. In this paper, we look at a particular instance of this approach which aims at constructing GALS (globally asynchronous locally synchronous) systems from specifications given in terms of transition systems with arcs labelled by steps of executed actions. GALS systems are represented by Elementary Net Systems with Localities (ENL-systems), each locality defining a set of co-located actions. The synthesis procedure is based on the regions of transition systems and we provide a number of criteria aimed at generating a minimal set of regions (conditions) of an ENL-system generating a given transition system.

Low Static Powered Asynchronous Data Transfer for GALS System

For a globally asynchronous locally synchronous (GALS) system, data transfer mechanisms based on a current-mode multiple valued logic (CMMVL) has been studied to reduce complexity and power dissipation of wires. However, these schemes consume considerable amount of power even in idle states because of the static power caused by their inherent structure. In this paper, new encoder and decoder circuits using CMMVL are suggested to reduce the static power. The effectiveness of the proposed data transfer is validated by comparisons with the previous CMMVL scheme and conventional voltage-mode schemes such as dual-rail and 1-of-4 encodings through simulation with a 0.25-μm CMOS technology. Simulation results demonstrate that the proposed CMMVL scheme significantly reduces power consumption of the previous one and is superior to dual-rail and 1-of-4 schemes over wire length of 2 mm and 4 mm, respectively.

Combining synchronous and asynchronous timing schemes for high-performance systems

Globally asynchronous, locally synchronous (GALS) design is emerging as the architecture of choice for certain applications. In a GALS system, the circuitry in each timing domain is locally synchronized, and different clock domains are glued together according to asynchronous communication schemes. This issue of IEEE Design & Test introduces some basic design and validation issues of the GALS architecture. The editorial from the guest editors outlines the scope of this special theme. In addition to the special theme, this issue also includes a special section highlighting the International Test Conference (ITC). Finally, there is a short report of highlights from the 2007 Design Automation Conference held earlier this year.

A Pattern Recognition Approach for Speculative Firing Prediction in Distributed Saturation State-Space Generation

The saturation strategy for symbolic state-space generation is particularly effective for globally-asynchronous locally-synchronous systems. A distributed version of saturation, SaturationNOW, uses the overall memory available on a network of workstations to effectively spread the memory load, but its execution is essentially sequential. To achieve true parallelism, we explore a speculative firing prediction, where idle workstations work on predicted future event firing requests. A naïve approach where all possible firings may be explored a priori, given enough idle time, can result in excessive memory requirements. Thus, we introduce a history-based approach for firing prediction that recognizes firing patterns and explores only firings conforming to these patterns. Experiments show that our heuristic improves the runtime and has a small memory overhead.

Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test

This paper describes a novel deterministic globally-asynchronous locally-synchronous (GALS) methodology called synchro-tokens. Wrappers around the synchronous blocks keep the system globally asynchronous while ensuring that each transition, although arriving at a nondeterministic time, is sensed by the synchronous block during a deterministic cycle of the local clock. This determinism facilitates debug and test methodologies, such as the use of stored-pattern testers, which are effective only when the system behavior is predictable and repeatable. Applications of synchro-tokens to GALS systems with two or more synchronous blocks and one or more asynchronous data channels are shown. Synchro-tokens supports both pipelined and unpipelined channels and a variety of clock generation methodologies. Novel schematic level designs of the wrapper components in a 180-nm technology are used to compare the performance of several different deterministic GALS design styles.

ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems

Globally Asynchronous, Locally Synchronous (GALS) systems are now commonplace in many cost-critical and life-critical applications, thus motivating the need for a systematic approach to verify functionality. The complexity of the verification problem for large heterogeneous GALS systems necessitates the development of simulation-based validation approaches to uniformly validate hardware, software, and their interaction. GALS systems are comprised of several processes which may be mapped to different hardware and software components and communicate through asynchronous interfaces. Communication between these processes must be verified to ensure that the system is working correctly. Previous work focuses on checking the correctness of individual processes rather than communication between multiple processes. Timing errors may cause a signal to have an incorrect value for a short time period. Timing errors can cause a problem in GALS systems if the value of a signal with a timing error is used while is has an incorrect value. This paper presents an automatic test pattern generation (ATPG) tool to generate tests for timing-induced functional errors.

Clock synchronization through handshake signalling

We present a method for synchronizing pausible clocks in GALS (Globally Asynchronous, Locally Synchronous) systems. In contrast to most conventional GALS schemes the method is not based on including in each ring oscillator a synchronizing element (such as for instance an arbiter) which on one side can pause the clock and on the other side offers a handshake interface. Instead, we propose a scheme in which each synchronous module has both an incoming and an outgoing clock signal, which have been obtained by opening the module's ring oscillator. Since these clock signals also behave as handshake signals, handshake circuits can be used to synchronize the clocks. We demonstrate the technique in the context of processors and memories. All the designs have been simulated and proved to be functionally correct.