Global Shutter Pixel Research Articles

Investigation of the Global Shutter Operation of the Quantum-Dot Short-Wave Infrared Image Sensor

Quantum dot (QD) thin-film photodiodes (TFPDs) are studied extensively in the image sensor field as they can pave the way toward the cost-efficient implementation of short-wave infrared (SWIR) cameras. Interestingly, the QD TFPD image sensors can be operated in the global shutter (GS) mode by turning on the photodiode (PD) only during integration time and subsequently turning it off during the readout. This offers the substantial advantage of reducing the pixel size as it eliminates the need for additional transistors or capacitors that are otherwise typically used in conventional GS pixels. So far, no comprehensive study has yet been performed on this PD turn on/off operation mode. Therefore, in this work, we investigated the PD turn on/off GS operation mode in comparison with the conventional voltage domain (VD) GS operation—a first in-depth report of its kind. We confirm that the PD turn on/off GS mode has the advantage of a small pixel size but comes at the cost of an increasing nonlinearity as the integration time approaches the PD speed limitation. We report a parasitic light sensitivity (PLS) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 70 dB over the visible (VIS) and SWIR range and moreover demonstrate that the PLS has the potential to reach <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt;$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 100 dB based on the discrete PD measurement.

A Novel Low Dark Current 9T Global Shutter Pixel with Merged Active Area

There is an increasing demand for high-performance global shutter pixels for CMOS image sensor (CIS) in the high-end imaging field. The existing global pixels have disadvantages, such as low sensitivity, high dark current, and large pixel area. In the present work, we developed a novel 9T global shutter CIS pixel with a much smaller pixel pitch of 2.8 μm. To our knowledge, it is the most miniature reported 9T global shutter CIS pixel. The developed 9T global shutter CIS pixel shows an excellent low dark current by the strategy of merging active area, which is 38 e−/s. Moreover, the cross-talk, sensitivity, read noise, dynamic range and full well capacity show performance. The current strategy is expected to be helpful in further improving the performance of other kinds of CIS pixels.

Paper] 4.0 μm Stacked Voltage Mode Global Shutter Pixels with Single Exposure High Dynamic Range and Phase Detection Auto Focus Capability

In this paper, two types of 4.0 μm back side illuminated stacked voltage mode global shutter pixels implemented in a prototype CMOS image sensor are reported. One is a pixel with a lateral overflow integration capacitor (LOFIC) to expand the sensor dynamic range and the other is a pixel having dual photodiodes and dual conversion gains which enables the phase detection auto focus capability with single exposure high dynamic range (SEHDR). Thanks to the LOFIC and the dual conversion gain technologies, SEHDR of 90 dB and 77 dB has been achieved in the global shutter mode.

A 368 × 184 Optical Under-Display Fingerprint Sensor Comprising Hybrid Arrays of Global and Rolling Shutter Pixels With Shared Pixel-Level ADCs

This study proposes a $368\times184$ optical under-display fingerprint sensor designed and prototyped using the 0.11- $\mu \text{m}$ CIS technology. The prototype sensor includes a hybrid array of global and rolling shutter pixels and a shared pixel-level analog-to-digital converter (ADC) embedded in a 32-pixel subarray configuration. It features a fast response time and low power consumption. By directly coupling the ramp signal to a floating diffusion capacitor with shared pixels, the best compromise between full-well capacity (FWC) and conversion gain is achieved. Two sets of memory (184 $\times $ 92 bytes) are also embedded in the pixel array to save the costs of external memory. A dynamic range of 110 dB is achieved with eight-segment automatic exposure and a contrast enhancement scheme for black level correction. A pixel binning process is used to improve the sensor sensitivity. The measured FWC, sensitivity, and conversion gain are 95 ke-, 800 ke-/lux-s, and $340~\mu \text{V}$ /e-, respectively. The prototype fingerprint sensor consumes only 15 mW with a 3.3-V supply voltage. The sensor chip size is 9.74 mm $\times \,\, 4.6$ mm, and the sensing area is 8 mm $\times \,\, 4$ mm, which is 71.4% of the chip size. The resolutions of the sensor without and with the pixel binning process are 1154 and 572 dpi, respectively.

An Improved Global Shutter Pixel with Extended Output Range and Linearity of Compensation for CMOS Image Sensor

An improved global shutter pixel structure with extended output range and linearity of compensation is proposed for CMOS image sensor. The potential switching of the sample and hold capacitor bottom plate outside the array is used to solve the problem of the serious swing limitation, which will attenuate the dynamic range of the image sensor. The non-linear problem caused by the substrate bias effect in the output process of the pixel source follower is solved by using the mirror FD point negative feedback self-establishment technology outside the array. The approach proposed in this paper has been verified in a global shutter CMOS image sensor with a scale of 1024×1024 pixels. The test results show that the output range is expanded from 0.95V to 2V, and the error introduced by the nonlinearity is sharply reduced from 280mV to 0.3mV. Most importantly, the output range expansion circuit does not increase the additional pixel area and the power consumption. The power consumption of linearity correction circuit is only 23.1μW, accounting for less than 0.01% of the whole chip power consumption.

A 4-tap global shutter pixel with enhanced IR sensitivity for VGA time-of-flight CMOS image sensors

An indirect time-of-flight (ToF) CMOS image sensor has been designed with 4-tap 7 μm global shutter pixel in back-side illumination process. 15000 e- of high full-well capacity (FWC) per a tap of 3.5 μm pitch and 3.6 e- of read-noise has been realized by employing true correlated double sampling (CDS) structure with storage gates (SGs). Noble characteristics such as 86 % of demodulation contrast (DC) at 100MHz operation, 37 % of higher quantum efficiency (QE) and lower parasitic light sensitivity (PLS) at 940 nm have been achieved. As a result, the proposed ToF sensor shows depth noise less than 0.3 % with 940 nm illuminator in even long distance.

A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel †.

A backside-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor with 4.0 μm voltage domain global shutter (GS) pixels has been fabricated in a 45 nm/65 nm stacked CMOS process as a proof-of-concept vehicle. The pixel components for the photon-to-voltage conversion are formed on the top substrate (the first layer). Each voltage signal from the first layer pixel is stored in the sample-and-hold capacitors on the bottom substrate (the second layer) via micro-bump interconnection to achieve a voltage domain GS function. The two sets of voltage domain storage capacitor per pixel enable a multiple gain readout to realize single exposure high dynamic range (SEHDR) in the GS operation. As a result, an 80dB SEHDR GS operation without rolling shutter distortions and motion artifacts has been achieved. Additionally, less than −140dB parasitic light sensitivity, small noise floor, high sensitivity and good angular response have been achieved.

A VGA Indirect Time-of-Flight CMOS Image Sensor With 4-Tap 7-$\mu$ m Global-Shutter Pixel and Fixed-Pattern Phase Noise Self-Compensation

A video graphics array (VGA) (640 $\times $ 480) indirect time-of-flight (ToF) CMOS image sensor has been designed with 4-tap 7- $\mu \text{m}$ global-shutter pixel in 65-nm back-side illumination (BSI) process. With a 4-tap pixel structure, we achieved motion artifact-free depth map. Peak current during exposure time has been reduced by current spreading with constant delay chain in the photo-gate driver. Column fixed-pattern phase noise (FPPN) from the constant delay chain is self-compensated by the proposed time-interleaving technique with the two inversely directional clock chains in the photo-gate driver. Quantum efficiency (QE) and demodulation contrast (DC) have been optimized by using appropriate optical engineering techniques with an optimal silicon thickness. As a result, QE of 34% at 940-nm near-infrared and high DC of 86% at 100-MHz modulation frequency have been achieved. In addition, motion artifact and column FPPN are successfully removed in the depth map. The proposed ToF sensor shows depth noise less than 0.57% with 940-nm illuminator over the working distance up to 4 m, and consumes only 160 mW for VGA output at 60 frames/s.

A High-Performance 2.5 μm Charge Domain Global Shutter Pixel and Near Infrared Enhancement with Light Pipe Technology.

We developed a new 2.5 μm global shutter (GS) pixel using a 65 nm process with an advanced light pipe (LP) structure. This is the world’s smallest charge domain GS pixel reported so far. This new developed pixel platform is a key enabler for ultra-high resolution sensors, industrial cameras with wide aperture lenses, and low form factors optical modules for mobile applications. The 2.5 μm GS pixel showed excellent optical performances: 68% quantum efficiency (QE) at 530 nm, ±12.5 degrees angular response (AR), and quite low parasitic light sensitivity (PLS)—10,400 1/PLS with the F#2.8 lens. In addition, we achieved an extremely low memory node (MN) dark current 13 e−/s at 60 °C by fully pinned MN. Furthermore, we studied how the LP technology contributes to the improvement of the modulation transfer function (MTF) in near infrared (NIR) enhanced GS pixel. The 2.8 μm GS pixel using a p-substrate showed 109 lp/mm MTF@50% at 940 nm, which is 1.6 times better than that without an LP. The MTF can be more enhanced by the combination of the LP and the deep photodiode (PD) electrically isolated from the substrate. We demonstrated the advantage of using LP technology and our advanced stacked deep photodiode (SDP) technology together. This unique combination showed an improvement of more than 100% in NIR QE while maintaining an MTF that is close to the theoretical Nyquist limit (MTF @50% = 156 lp/mm).

Electrical Characterization of the Backside Interface on BSI Global Shutter Pixels with Tungsten-Shield Test Structures on CDTI Process.

A new methodology is presented using well known electrical characterization techniques on dedicated single devices in order to investigate backside interface contribution to the measured pixel dark current in BSI CMOS image sensors technologies. Extractions of interface states and charges within the dielectric densities are achieved. The results show that, in our case, the density of state is not directly the source of dark current excursions. The quality of the passivation of the backside interface appears to be the key factor. Thanks to the presented new test structures, it has been demonstrated that the backside interface contribution to dark current can be investigated separately from other sources of dark current, such as the frontside interface, DTI (deep trench isolation), etc.

Low Noise Global Shutter Image Sensor Working in the Charge Domain

In this letter, we present global shutter (GS) pixel using active deep trench isolation gate to transfer and store photodiode charge signal into a fully depleted pinned MOS capacitance. This architecture is compatible with conventional correlated double sampling. GS readout noise lower than 2e- is demonstrated. The fully depleted pinned capacitance is able to store 12ke- with dark current lower than 25e-/s at 60 °C. The GS efficiency, better than 99.96% at 550nm, is reported.

A Back-Illuminated Voltage-Domain Global Shutter Pixel With Dual In-Pixel Storage

A 3.75- $\mu \text{m}$ back-illuminated voltage-domain global shutter (GS) pixel is presented. The 10T pixel architecture presented contains two independently operable storage branches and supports dual-capture, high-dynamic-range (HDR) imaging and correlated double sampling functionality. Electronic shielding of the sample diffusions by the vertical photodiode is utilized to reach native and differential parasitic light sensitivities below −73.5 and −82.5 dB at 940 nm, respectively. A GS HDR image capture mode with minimal motion artifacts is also demonstrated.

Development of Low Parasitic Light Sensitivity and Low Dark Current 2.8 μm Global Shutter Pixel.

We developed a low parasitic light sensitivity (PLS) and low dark current 2.8 μm global shutter pixel. We propose a new inner lens design concept to realize both low PLS and high quantum efficiency (QE). 1/PLS is 7700 and QE is 62% at a wavelength of 530 nm. We also propose a new storage-gate based memory node for low dark current. P-type implants and negative gate biasing are introduced to suppress dark current at the surface of the memory node. This memory node structure shows the world smallest dark current of 9.5 e−/s at 60 °C.

Development of Gentle Slope Light Guide Structure in a 3.4 μm Pixel Pitch Global Shutter CMOS Image Sensor with Multiple Accumulation Shutter Technology.

CMOS image sensors (CISs) with global shutter (GS) function are strongly required in order to avoid image degradation. However, CISs with GS function have generally been inferior to the rolling shutter (RS) CIS in performance, because they have more components. This problem is remarkable in small pixel pitch. The newly developed 3.4 µm pitch GS CIS solves this problem by using multiple accumulation shutter technology and the gentle slope light guide structure. As a result, the developed GS pixel achieves 1.8 e− temporal noise and 16,200 e− full well capacity with charge domain memory in 120 fps operation. The sensitivity and parasitic light sensitivity are 28,000 e−/lx·s and −89 dB, respectively. Moreover, the incident light angle dependence of sensitivity and parasitic light sensitivity are improved by the gentle slope light guide structure.

8.3 M-Pixel 480-fps Global-Shutter CMOS Image Sensor with Gain-Adaptive Column ADCs and Chip-on-Chip Stacked Integration

This paper presents a 4K2K 480-fps global-shutter CMOS image sensor with a super 35-mm format for a highly realistic digital video system. The sensor employs newly developed gain-adaptive column analog-to-digital converters to obtain input-referred dark random noise of 140 $\mu \text{V}_{\mathrm {rms}}$ for an input-referred full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintained the nonlinearity of the output image within 0.18%. A chip-on-chip integration process realized a front-illuminated image sensor stacked with two diced logic chips through 38-K microbump interconnections. The global-shutter pixel achieved a parasitic light sensitivity of −99.6 dB. The 16-channel output interfaces with 4.752 Gbps/ch were implemented in the stacked logic chips.

Characterization of total ionizing dose damage in COTS pinned photodiode CMOS image sensors

The characterization of total ionizing dose (TID) damage in COTS pinned photodiode (PPD) CMOS image sensors (CISs) is investigated. The radiation experiments are carried out at a 60Co γ-ray source. The CISs are produced by 0.18-μm CMOS technology and the pixel architecture is 8T global shutter pixel with correlated double sampling (CDS) based on a 4T PPD front end. The parameters of CISs such as temporal domain, spatial domain, and spectral domain are measured at the CIS test system as the EMVA 1288 standard before and after irradiation. The dark current, random noise, dark signal non-uniformity (DSNU), photo response non-uniformity (PRNU), overall system gain, saturation output, dynamic range (DR), signal to noise ratio (SNR), quantum efficiency (QE), and responsivity versus the TID are reported. The behaviors of the tested CISs show remarkable degradations after radiation. The degradation mechanisms of CISs induced by TID damage are also analyzed.

A Polar Symmetric CMOS Image Sensor for Rotation Invariant Measurement

We present a CMOS image sensor for efficient capture of polar symmetric imaging targets. The array uses circular photodiodes, arranged in concentric rings to capture, for example, diffraction patterns generated by optically probing a revolving MEMS device. The chip is designed with a vacant, central spot to facilitate the easy single-axis alignment of the probing illumination, target device, and detector. Imaging of high-speed rotation (>1 kfps) is made possible by dividing the array into multiple concentric bands with sectorwise addressing control. We introduce a global shutter pixel reset scheme that reduces fixed pattern noise by being insensitive to parasitic capacitance from variable routing. We demonstrate the sensor’s capability to measure the rotation angle with a precision of 32 $\mu$ rad and the rotation rates up to 300 rpm. Finally, we demonstrate the concept of a compact optical metrology system for continuous inertial sensor calibration by imaging the diffraction pattern created by a commercial MEMS accelerometer probed by a red laser shone through the axis of symmetry of the image sensor.

CMOS Global Shutter Charge Storage Pixels With Improved Performance

We describe different charge-storage-based global shutter (GS) pixel architectures with improved performance resulting from low dark current and effective pixel pitch reduction from 6 to 2.8 $\mu \text{m}$ pixel size. Smaller pixels showed better image quality versus larger pixels at low exposures and higher temperatures. In addition to earlier disclosed work, we proposed and have developed novel high GS efficiency (GSE) pixel modules such as the improved tungsten buried light shield and the pixel light guide structures. The GS pixel simulation and measurements showed significant improvement in sensitivity, dark current, and GSE. These pixels and modules have been implemented in a variety of ON Semiconductor sensors. More than $1.2\times $ area-scaled sensitivity improvements, more than $20\times $ improvement in average storage dark current, and from $7\times $ to more than $38\times $ GSE improvement at different light wavelengths were demonstrated.

1-2 Topics (2); High-speed readout, ADC, stacked image sensors and global shutter pixel sensors

1-2 Topics (2); High-speed readout, ADC, stacked image sensors and global shutter pixel sensors

A low power global shutter pixel with extended FD voltage swing range for large format high speed CMOS image sensor

A low power 8T global shutter pixel with extended FD voltage swing range is proposed for large format high speed CMOS image sensor. The pixel has a negative threshold reset transistor, two in-pixel source followers, and a sample-and-hold circuit. The in-pixel first source follower is employed for reducing the pixel average current and maximum transient current. The negative threshold reset transistor is applied to extend the voltage swing of FD. Using pixel level sample-and-hold circuit, the kTC noise on FD node can be effectively nullified by correlated double sampling operation. A high speed 1000 fps 256×256 CMOS image sensor is implemented in 0.18 μm CMOS process. Two 10-bit cyclic ADC arrays are integrated in this prototype sensor chip. The active area of the chip is 10 mm×7 mm with a pixel size of 14 μm×14 μm. The developed sensor achieves an average current of 23 nA per pixel, a maximum transit current per pixel as low as 1113 nA, and a large FD voltage swing of 1.78 V. The sensor temporal noise level is 103 e- and full well capacity has 27000 e- which results in 48.3 dB signal dynamic range.