Abstract

A new methodology is presented using well known electrical characterization techniques on dedicated single devices in order to investigate backside interface contribution to the measured pixel dark current in BSI CMOS image sensors technologies. Extractions of interface states and charges within the dielectric densities are achieved. The results show that, in our case, the density of state is not directly the source of dark current excursions. The quality of the passivation of the backside interface appears to be the key factor. Thanks to the presented new test structures, it has been demonstrated that the backside interface contribution to dark current can be investigated separately from other sources of dark current, such as the frontside interface, DTI (deep trench isolation), etc.

Highlights

  • Backside illuminated (BSI) imager technologies are nowadays widely used thanks to their advantages, such as better fill factor and better light collection, compared to frontside technologies.As the frontside interface, the backside interface can be a source of dark current

  • A characterization method named COCOS [6] already exists which enables the extraction of the density of the interface states and the charges within the oxide just after the deposition of a material

  • A new methodology is presented that enables characterizing the backside interface at the very end of the process and so, in the final pixel environment, which cannot be done by COCOS because of the metal shield preventing the light needed for the measurement from reaching the interface

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Summary

Introduction

Backside illuminated (BSI) imager technologies are nowadays widely used thanks to their advantages, such as better fill factor and better light collection, compared to frontside technologies. A new methodology is presented that enables characterizing the backside interface at the very end of the process and so, in the final pixel environment, which cannot be done by COCOS because of the metal shield preventing the light needed for the measurement from reaching the interface. It is based on well-known and relatively simple electrical characterization techniques applied on new dedicated test structures that benefit from the tungsten (W) layer in the technology for light shielding purposes. Multiple structures are present for different tests important for charge within the oxide,unlike COCOS unpatterned wafers.

Cumulative
Wafer map showing showing the the dies dies used used for for Idark
Illustration
Interface
A ItisA the
Chronogram
Quality of the Passivation Characterization
16. Scatter
Charging Effect
12 V and then from
19. Hysteresis
21. Hysteresis
Conclusions
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