Global Clock Distribution Research Articles

The clock and control signal distribution system for the NA48 experiment

In the NA48 experiment at CERN, several detector subsystems located at distances of up to 200 m between each other produce data on a continuous basis and feed them into pipelines. Triggers are produced after variable delay times by two different systems for charged and for all-neutral kaon decays. To allow the retrieval of the corresponding data from the various subsystems and their merging into complex events by means of timestamps, a special, highly stable global clock distribution system has been developed. The design principles and the setup of the clock system are described and results for clock stability monitoring and automated correction of the signal transmission speed are reported.

Data-driven self-timed RSFQ digital integrated circuit and system

A novel asynchronous timing scheme, data-driven self-timing (DDST) is proposed and implemented in Rapid Single-Flux-Quantum (RSFQ) superconductive integrated circuits. In this asynchronous approach, the timing signals are generated from the data and no global clock is needed to drive the RSFQ circuit and system. The essence of the self-timing scheme is to localize the system timing in order to avoid the overhead of global clock distribution, and to minimize the timing uncertainty. The DDST scheme has been applied to the design of a shift register, a demultiplexor, and a self-timed high speed digital test system. In this paper, test results of a 4-bit DDST shift register and a high speed on-chip clock generator will be presented to demonstrate the successful DDST operation of RSFQ integrated circuits at a rate of 20 Gb/s.

Synchronous global clock distribution on multichip modules using optical waveguides

A novel optical waveguide H-tree design for synchronous global clock distribution on multichip modules, which has nearly zero clock skew, is developed for a distributed computer system environment. The optical waveguide H-tree design utilizes channel waveguides, curved sections, and directional couplers formed using silica glass and silicon oxynitride channel waveguide technologies. Design calculations are presented comparing these technologies that suggest a hybrid combination having the advantages of each. System performance analysis is carried out for both waveguide technologies and the hybrid combination. These calculations demonstrate the feasibility of this approach and show that the achievable clock speed is limited by the laser diode source and photodiode receiver at each chip module, and not by the optical waveguide distribution network.

Race-free clocking of CMOS pipelines using a single global clock

To ease global clock distribution in a synchronous system extending over several levels of interconnect (for example between logic blocks within a chip, chips mounted on a printed circuit board and boards of chips across a backplane), a race-free clocking scheme for CMOS VLSI requiring a single clock line is presented. Since the technique is race-free, the clock line may be driven by a sinusoid, thereby avoiding the transmission of the higher frequency components associated with fast clock edges. In this way, clock signal distortion due to transmission line effects will be kept to a minimum.

On RC line delays and scaling in VLSI systems

We propose that a special interconnection metal layer is introduced into the VLSI process and used for global clock distribution and communication. We show that by this method the interconnection delay will not be a limiting factor for the speed of synchronous circuits in CMOS down to 0.3 μm feature sizes and up to 20 mm chip sizes.