Global Clock Distribution Networks Research Articles

Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC

Automatic clock gating (ACG) is a clock-gating architecture with near zero waste on dynamic power dissipation on global clock distribution network. ACG models global clock structure as a graph with nodes and arcs representing clock components and their interconnections, respectively. Unlike conventional clock structure, where arcs are nothing more than clock nets, ACG adds control mechanism on the arc so that clock gating decision on each clock component can be automated. In this structure, each clock component can understand activities on its fan-outs and can be configured to cut off its output clock when there is no activity. The framework also allows clock consumers to define a period in time where their clock is guaranteed to be present. Combination of these features results in global clock structure, where unnecessary transition on any clock net is automatically avoided. The overall power benefit from this architecture is measured to be 17%–50%.

Decreasing the Power-Clock Resonant Signal Central Voltage as a Mean for Power Reduction in Integrated Power and Clock Distribution Networks

Background/Objectives: Density, performance, and design complexity of integrated circuits are rapidly increasing specifically in 3-D integration where multi-plane synchronization is required. The power and clock distribution networks consume a large portion of the limited on-chip metal resources. In order to reduce the metal overhead associated with the power, global clock, and local clock distribution networks, the concept of an integrated power and clock distribution network (IPCDN) was investigated and correct functionality of combinational and sequential elements verified. This study discusses potential power savings in IPCDNs achieved by reducing the central voltage at which the signal oscillates. Methods/Statistical analysis: In this paper, an IPCDN with differential power-clock signals centered at half the supply voltage is proposed to further reduce the power consumption. The elements of the proposed scheme including the LC differential power-clock driver, clamping circuit, clock buffer, and voltage doubler have been simulated using Tanner 0.25 um CMOS technology at a frequency of 50 MHz and a supply voltage of 2.5 V. Findings: Simulation results indicate that the proposed scheme achieves 75.32% and 76.47% power reduction in the LC differential powerclock driver and clock buffer, respectively. The effects of process, voltage supply, and temperature (PVT) variations on the proposed scheme were also investigated. Discussion: The IPCDN has a large capacitance and is heavily loaded, thus reducing the central voltage of the resonant sinusoidal signal flowing in this network enables significant reduction in power consumption. Novelty/Applications: The proposed scheme enables power reductions in the LC differential power clock driver and clock buffer. The effects of process, voltage supply, and temperature (PVT) variations on all circuit elements of the proposed scheme was investigated. Keywords: resonant clocking; power reduction; routing complexity; LC clock driver; clock buffer; clamping circuit; voltage doubler Density, performance, and design complexity of integrated circuits are rapidly increasing specifically in 3-D integration where multi-plane synchronization is required. The power and clock distribution networks consume a large portion of the limited on-chip metal resources. In order to reduce the metal overhead associated with the power, global clock, and local clock distribution networks, the concept of an integrated power and clock distribution network (IPCDN) was investigated and correct functionality of combinational and sequential elements verified. This study discusses potential power savings in IPCDNs achieved by reducing the central voltage at which the signal oscillates. Methods/Statistical analysis: In this paper, an IPCDN with differential power-clock signals centered at half the supply voltage is proposed to further reduce the power consumption. The elements of the proposed scheme including the LC differential power-clock driver, clamping circuit, clock buffer, and voltage doubler have been simulated using Tanner 0.25 um CMOS technology at a frequency of 50 MHz and a supply voltage of 2.5 V. Findings: Simulation results indicate that the proposed scheme achieves 75.32% and 76.47% power reduction in the LC differential powerclock driver and clock buffer, respectively. The effects of process, voltage supply, and temperature (PVT) variations on the proposed scheme were also investigated. Discussion: The IPCDN has a large capacitance and is heavily loaded, thus reducing the central voltage of the resonant sinusoidal signal flowing in this network enables significant reduction in power consumption. Novelty/Applications: The proposed scheme enables power reductions in the LC differential power clock driver and clock buffer. The effects of process, voltage supply, and temperature (PVT) variations on all circuit elements of the proposed scheme was investigated. Keywords: resonant clocking; power reduction; routing complexity; LC clock driver; clock buffer; clamping circuit; voltage doubler

On SFC Low Power Hardware Implementation in FPGAs

The paper presents an idea of automatic synthesis to an FPGA device of a program developed with use of the SFC including actions. The synthesis is oriented to achieve power reduction by creating multiple clock domains and controlling switching activity. A circuit is selectively clocked based on processing activity. Global clock distribution networks are used in order to assure proper operation of a system. Proposed methods automatically split a controller into clock domains and implements all necessary circuitry. The paper is concluded with benchmark experiments that proves energy consumption reduction for proposed methods in reference to standard approach using fully synchronous implementation methodology.

Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits

In the paradigm of stochastic computing, arithmetic functions are computed on randomized bit streams. The method naturally and effectively tolerates very high clock skew. Exploiting this advantage, this paper introduces polysynchronous clocking, a design strategy in which clock domains are split at a very fine level. Each domain is synchronized by an inexpensive local clock. Alternatively, the skew requirements for a global clock distribution network can be relaxed. This allows for a higher working frequency and so lower latency. The benefits of both approaches are quantified. Polysynchronous clocking results in significant latency, area, and energy savings for wide variety of applications.

A 780 mW 4 <formula formulatype="inline"><tex Notation="TeX">$\times$</tex></formula> 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS

This paper describes a reconfigurable 4 × 28 Gb/s transceiver supporting 100 GbE/40 GbE standards. In each lane, the transmitter incorporates a 3-tap FIR with independent output phase adjustment, and the receiver has a half-rate CDR with a dedicated eye-monitor channel. There is a global resonant clock distribution network implemented using programmable distributed on-chip inductors. Implemented in a 40 nm CMOS process, the TX output measures 1.87 pspp DJ and 202 fsrms RJ. The RX jitter tolerance is 0.46 UIpp at 80 MHz with an input sensitivity of 27 mVpp-diff. The transceiver achieves BER on a channel with 20 dB loss at Nyquist, dissipating only 780 mW from a 0.9 V supply for all four lanes at 28 Gb/s operation.

An 8–16 Gb/s, 0.65–1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning

Serial link transmitters which efficiently incorporate equalization, while also enabling fast power-state transitioning to leverage dynamic power scaling, are necessary to meet future systems' I/O requirements. This paper presents a scalable voltage-mode transmitter which offers low static power dissipation and adopts an impedance-modulated 2-tap equalizer with analog tap control, thereby obviating driver segmentation and reducing pre-driver complexity and dynamic power. Topologies that allow for rapid power-up/down, including a replica-biased voltage regulator to power the output stages of multiple transmit channels and per-channel quadrature clock generation with injection-locked oscillators (ILO), enable fast power-state transitioning. Energy efficiency is further improved with capacitively driven low-swing global clock distribution and supply scaling at lower data rates, while output eye quality is maintained at low voltages with automatic phase calibration of the local ILO-generated quarter-rate clocks. A prototype fabricated in a general purpose 65 nm CMOS process includes a 2 mm global clock distribution network and two transmitters that support an output swing range of 100-300 mV with up to 12 dB of equalization. The transmitters achieve 8-16 Gb/s operation at 0.65-1.05 pJ/b energy efficiency and sub-3 ns power-up/down times.

A 4.8-mW/Gb/s 9.6-Gb/s 5 <inline-formula> <tex-math notation="TeX">$+$</tex-math></inline-formula> 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS

A low-jitter and low-power source-synchronous serializer/deserializer transmitter (TX) with a data rate of 9.6 Gb/s is presented. The TX consists of five data channels plus one forwarded-clock channel and features a total jitter of 20.39 ps p-p at 10-12 bit error rate. Low jitter is achieved through the use of a phase-locked loop with bandwidth linearization that has a random RMS jitter of 0.66 ps. A global clock distribution network is proposed to minimize the power-supply-induced jitter and the power consumption. The TX transmits preemphasized data through a current-mode logic driver with a four-tap feedforward equalizer. The on-chip output impedance and the signal amplitude can be accurately calibrated by a successive approximation register logic separately. The total power consumption for the 5 +1-lane TX physical core fabricated in 65-nm bulk CMOS running at 9.6 Gb/s is 230 mW or 4.8 mW/Gb/s.

Integrated Power and Clock Distribution Network

In this brief, we investigate and propose solutions for integrating the clock and power distribution networks all the way to circuit level. The aim is to reduce metal requirements, routing complexity, and power. The concept of an integrated power and clock distribution network (IPCDN) is proposed in order to eliminate the need for the global and local clock distribution networks. In IPCDN, a differential power-clock signal (Pwr_Clk) with a suitable dc voltage level and sinusoidal voltage-swing feeds the VDD ports in combinational and sequential elements. A clock buffer is used for sequential elements in order to extract a full-swing clock from the differential Pwr_Clk+ and Pwr_Clk- signals. IPCDN does not require any change to be made to the conventional combinational and sequential circuit design. The proposed elements of IPCDN, including the LC differential Pwr_Clk driver and the clock buffer, have been simulated using Taiwan Semiconductor Manufacturing Company 65-nm CMOS technology with a Pwr_Clk signal, a 1-V dc component, and 400-mV sinusoidal swing at a frequency of 5 GHz. In addition, the behavior of a master-slave flip-flop with IPCDN was investigated at extreme corners. Simulation results demonstrate correct functionality of all elements of the IPCDN. Comparing IPCDN to a buffered square-wave clock distribution network illustrates that, with a heavily loaded network, IPCDN achieves around 20% reduction in power. This percentage increases when the network capacitance is dominating.

Effect of process variations in 3D global clock distribution networks

In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D clock distribution networks is considered in this article. A statistical clock skew model incorporating both the systematic and random components of process variations is employed to describe this effect. Two regular 3D clock tree topologies are investigated and compared in terms of clock skew variation. The statistical skew model used to describe clock skew variations is verified through Monte-Carlo simulations. The clock skew is shown to change in different ways with the number of planes forming the 3D IC and the clock network architecture. Simulations based on a 45-nm CMOS technology show that the maximum standard deviation of clock skew can vary from 15 ps to 77 ps. Results indicate that simply increasing the number of planes of a 3D IC does not necessarily lead to lower skew variation and higher operating frequencies. A multigroup 3D clock tree topology is proposed to effectively mitigate the variability of clock skew. Tradeoffs between the investigated 3D clock distribution networks and the number of planes comprising a 3D circuit are discussed and related design guidelines are offered. The skew variation in 3D clock trees is also compared with the skew variation of clock grids.

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process

A 12.3-mW 12.5-Gb/s complete transceiver based on the 65-nm standard digital CMOS process was developed. The chip includes a clock-and-data-recovery (CDR) device, a multiplexer/demultiplexer (MUX/DEMUX), and a global clock-distribution network. To reduce power consumption, a low-swing voltage-mode driver with pulse-current boosting and an LC resonant-clock distribution with distributed on-chip inductors are used in the transmitter, while a symbol-rate phase detector (SPD) using a three-stage sense amplifier and phase-rotating phase-locked loop (PLL) with variable delay are used in the receiver. The transceiver operates at a bit error rate (BER) of 10-12 or less through a 20-cm test board with total attenuation of -12.1 dB while consuming power of 0.98 mW/(Gb/s) per transceiver.

Latency/area analysis and optimization of asynchronous nanowire reconfigurable crossbar system

With continued scaling of complementary metal-oxide-silicon (CMOS) technology, numerous challenges have arisen making it difficult to progress with. These challenges include the increase of integrated circuit complexity, non-recoverable expenses, frequency and power density. Nanotechnologies are expected to take the forefront of continuing the technological revolution. In this work, a novel model-based latency/area analysis and optimization method for the newly proposed Asynchronous Nanowire Reconfigurable Crossbar Architecture (ANRCA) is presented and validated. ANRCA is based on a self-timed logic referred to as the Null Convention Logic (NCL). There is no global clocking and clock distribution network, all failure modes related to timing will be either eliminated or relaxed. The proposed architecture is anticipated to have higher manufacturability and robustness that are critical factors in nanoscale systems due to the nondeterministic nature of nanoassemblies and also suitable computing frameworks for asynchronous nanoscale communication networks. In order to facilitate efficient programming and flexible reconfiguration, a new hierarchical reconfigurable architecture for ANRCA is also proposed. Various configurable logic block structures have been considered and also their programming and reconfiguration issues are discussed. The proposed measurement and optimization method can be used to estimate area and latency measurements for different configurable logic blocks and also applied to find the optimal structure for the given arbitrary logic to map.

A low-power reduced swing global clocking methodology

In this brief, we investigate the potential of reduced swing clock networks for low-power applications. We designed and laid out a full swing conventional and a reduced swing H-tree clock distribution network in 0.13-/spl mu/m CMOS technology operating at 500 MHz. In the reduced swing clock network, the swing was reduced in the global clock distribution network and was restored to the full swing in the local clock distribution domains. The post-layout simulation results of this research shows that a power saving of 22% under nominal operating condition is feasible.

Guest editorial: special issue on on-chip inductance in high-speed integrated circuits

HE appropriate interconnect model has changed several times over the past two decades due to aggressive technology scaling. New, more accurate interconnect models were introduced when parasitic effects that were negligible in earlier technologies, could no longer be ignored. Currently, RC models are used to analyze high resistance nets while capacitive models are used for less resistive interconnects. However, on-chip inductance is becoming increasingly important since integrated circuits now operate at frequencies where the inductive impedance of thick wide wires is comparable to wire resistance and line lengths are long enough, relative to signal rise times, for transmission line behavior to become significant. Furthermore, this trend shows every indication of spreading beyond the relatively few lines it now affects. Operating frequencies that have increased dramatically over the past decade, are expected to maintain the same rate of increase over the next decade approaching 10 GHz by the year 2012. The use of thick upper level metals, large die sizes, and low resistance copper interconnect—already used in many commercial CMOS technologies, will likewise continue. Finally, because large die sizes enable more system integration, the use of long thick wide wires, once largely devoted to global clock distribution networks, will spread to critical data-buses and control lines. This special issue deals with the design and analysis of integrated circuits including parasitic on-chip inductance. It does not deal with intentionally designed structures like the spiral inductors used in RF circuits and LC tank oscillators. As evidence that the subject material is still under investigation, the papers in this special issue do not present a unified approach to modeling parasitic inductance. The most notable difference centers around the use of 2-D (or loop inductance) models versus more general 3-D inductance models, and at the center of this debate is the question of current loops formed by return currents. The 3-D model advocates take the position that the return current paths are fundamentally unknown and present sophisticated analysis methods to cope with the increased complexity of 3-D models. The 2-D advocates insist that the return currents are equal and opposite to the interconnect currents and can therefore, employ simpler models. While this debate is apparent in the second paper which favors 2-D models and the third, fourth, and sixth papers which favor 3-D models, several other papers also imply a preference by presenting analytical methods that are suitable to 2-D models only. The paper summary below highlights when notable, the authors stated or implied preference to 2-D or 3-D models. In the first paper, Ismail presents several analytical methods for including inductive effects in both timing and noise analysis. The analytical models he presents are only applicable to

Clocking design and analysis for a 600-MHz Alpha microprocessor

The clocking methodology for the 600 MHz Alpha microprocessor allows increased performance goals to be met through multi-level buffering. In addition power savings are realized through reduced metal usage and conditional clocks. Two distinct analysis methods are required to verify the clock design. One is used for large, globally distributed clocks and the other is applied to small, locally distributed clocks. The clock is generated from an 80-200 MHz reference clock multiplied by an on-chip phase-locked loop (PLL) to a nominal frequency of 600 MHz. The clock distribution network up to and including the global clock (GCLK) is included in the feedback loop of the PLL to control phase alignment. GCLK is the primary timing reference for the chip. The generation of GCLK begins at the PLL and is routed through a high-gain buffer network to a central point on the die. From there the clock is driven through buffered X, H and RC trees to distributed GCLK drivers located in a windowpane pattern across the chip. The final physical stage of the global clock distribution network is a grid of upper-level low-impedance metal that covers the entire die.