Gilbert Cell Research Articles

Design of Direct Digital Synthesizer of Gilbert Cell Using Chisel Generator with NCO

Numerous digital communication systems, such as digital radio and modems, digital converters, computer base stations, etc., depend on numerically controlled oscillators (NCOs). NCOs are so often utilized because of the wide range of beneficial characteristics that possess. Direct digital frequency synthesizers (DDFSs) are essential elements of modern radio electronics. These signals can be generated using either analogue circuitry or digital circuitry. These signals are generated by an NCO in a digital system, and they are then converted to analogue signals by a digital-to-analog converter (DAC). This paper presents a direct digital synthesizer (DDS) of Gilbert cell using a chisel generator with NCOs. The DDS has a sine-wave generator analogue Gilbert cell, a phase accumulator, wave-correction ROM (WCR), RAM, and DACs. Two ground-signal-ground (GSG) single-ended microwave probes and two DC probes are used to test the DDS on the wafer. The results of the test demonstrate that it can create sine waves with a frequency resolution of 23.44[Formula: see text]MHz and can operate consistently at 6[Formula: see text]GHz clock frequency.

Gilbert cell down-conversion mixer for THz wireless communication with passive baluns

Gilbert cell down-conversion mixer for THz wireless communication with passive baluns

An Inductor‐Less Zero‐IF Down‐Conversion Mixer With Low Flicker Noise and High Conversion Gain

ABSTRACTThis paper presents a novel active inductor (AI) to improve the performance of a down‐conversion active mixer in terms of conversion gain (CG) and flicker noise. The proposed AI exhibits negative resistance and partially flat inductance over a wide frequency band of 0.5–4.5 GHz. The effect of inserting the AI between the source of the switching quad of a Gilbert cell mixer is theoretically analyzed. The proposed inductor‐less mixer, designed to operate at a 2.4‐GHz RF input frequency and a 10‐MHz IF output frequency, employs current reuse and self‐forward body bias (SFBB) techniques. The proposed circuit is simulated in Cadence Spectre‐RF using RF‐TSMC 0.18‐μm CMOS technology. Post‐layout simulations demonstrate that the proposed AI significantly reduces flicker noise by over 23 dB at an IF output frequency of 1 kHz and improves the CG by over 16 dB at an RF frequency of 2.4 GHz. The proposed mixer achieves a CG of 37.6 dB and a flicker noise corner frequency of 6 kHz. Additionally, it exhibits a third‐order intermodulation intercept point (IIP3) of −5.2 dBm and a double‐sideband noise figure (DSB‐NF) of 6.1 dB at the IF output frequency of 10 MHz. Operating with a 1.5‐V supply, the proposed mixer consumes 10.6 mW of power.

Comparative Study and Design of High Performance Mixer

In recent time the use of RF mixer has been increased greatly. Gilbert cell is widely used as core of the mixer because it provides high conversion gain, good port-to-port isolation and low even-order distortion. It is found that the linearity of mixer is very good for Multi-Tanh technique by incorporating multiple differential trans-conductance stage but it reaches to very low conversion gain whereas, use of current bleeding technique increase linearity and conversion gain of the mixer by adding current source to increase the bias current at the expense of power consumption. Since, CMOS technology has become dominant because of its several advantages such as low cost, low static power dissipation and low area, the design of low noise amplifier using CMOS technology was top choice for design of Low Noise Amplifier. The single ended and differential LNA was designed to operate in a WCDMA reception range using a BSIM3V2 model (Level 49) CMOS UMC 0.18μm technology in Xcircuit Open source EDA tool. The key issues in the design, gain, noise and linearity were considered. The LNA’s was designed to provide high gain, matching to 50Ω RF system, good linearity.

Design of a 60-GHz Joint Radar–Communication Transceiver With a Highly Reused Architecture Utilizing Reconfigurable Dual-Mode Gilbert Cells

Design of a 60-GHz Joint Radar–Communication Transceiver With a Highly Reused Architecture Utilizing Reconfigurable Dual-Mode Gilbert Cells

Lung Mechanics Tracking With Forced Oscillation Technique (FOT) Based on CMOS Synchronous Demodulation Principle.

In this paper, an area-efficient CMOS integrated solution for lung impedance extraction is presented. The lock-in principle is leveraged for its high effective bandpass selectivity, to acquire information about the airways, through stimulation by FOT (Forced Oscillation Technique). The modulated pressure and flow signals are down-converted by a quadrature voltage commutating passive mixer-first receiver. In addition to its linearity, and unlike the Gilbert cell, it can be biased at zero dc current to alleviate flicker noise contributions. The proposed solution is designed and fabricated in 0.18µm TSMC technology. The chip occupies an active silicon area of 4.7 mm2 (including buffers and pads) and dissipates 429.63 µW. The proposed approach offers real time tracking of respiratory mechanics and is expected to be a promising solution for portable health monitoring and cost-effective biomedical devices.

220-240-GHz High-Gain Phase Shifter Chain and Power Amplifier for Scalable Large Phased-Arrays

This paper focuses on the design aspects of the key components for a scalable phased-array system over the 200 GHz frequency range. A high-gain phase shifter chain for 220 to 240 GHz frequency range and a high-gain power amplifier (PA) with a high output power are designed in a 0.13-μm SiGe BiCMOS technology. The phase shifter chain includes a low-noise amplifier (LNA), a vector modulator phase shifter (PS), and a gain-enhancing amplifier. The LNA is a five-stage cascode design. The vector modulator core is realized by two variable gain amplifiers based on the Gilbert cell architecture. A four-stage cascode design is used for the gain-enhancing amplifier. The phase shifter chain shows a measured gain of 18 dB at 230 GHz with a 360° phase tuning range and more than 10 dB of gain control. The chip achieves a minimum measured noise figure of 11.5 dB at 230 GHz and shows a wideband noise characteristic. The complete phase shifter chain chip consumes a dc power of 153 mW and occupies a 1.41 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area. A high-power PA that is critical for a large phased-array system is designed. This paper presents a unique 4-way power combining technique utilizing a differential quadrature coupler. The realized balanced PA occupies an area of 0.67 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and shows a measured peak gain of 21 dB at 244 GHz. The PA consumes 819 mW of dc power and delivers a maximum saturated output power ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P_sat</i> ) of 7.1 dBm at 244 GHz and more than 4.3 dBm of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P_sat</i> from 230 to 255 GHz.

A 28 GHz RF-DAC With Analog LO Leakage Cancellation

A 28-GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times 8$ </tex-math></inline-formula> bit quadrature RF-DAC is presented, which has an analog LO leakage cancellation circuit. It is based on a double-balanced Gilbert cell structure where current bleeding paths are introduced to prevent the cells from being completely turned off. LO leakages of the RF-DAC are canceled by controlling the current bleeding paths. It was fabricated in a 28-nm bulk CMOS process and achieved a −5.6-dBm CW output power with 12-mW power consumption from a 1.1 V supply and 3-Gb/s maximum data rate with 64-QAM signals. −45-dBc LO leakage was achieved using the proposed leakage cancellation technique.

A CMOS down-conversion mixer for microwave radar application

This paper introduces a CMOS down-conversion mixer for microwave radar application. The mixer is based on the classical Gilbert cell architecture, using PMOS current bleeding technology and cross-coupling as a transconductance stage to further elevate the conversion gain and decrease the noise factor, while introducing source negative feedback technology to enhance the linearity performance of the mixer. Using the SMIC 0.13 um CMOS process, the simulation results prove that the frequency conversion gain of the mixer is 12.31 dB, the noise factor is 21.16 dB, and the -1dB compression point of the output is -12.66 dBm when the input RF signal is 10 GHz and the output IF signal is 10 MHz. The third-order intermodulation cut-off point is -1.70 dBm, and the power dissipation is 3.16 mW under a 1.2 V power supply.

A 200–250-GHz Phase Shifter Utilizing a Compact and Wideband Differential Quadrature Coupler

This letter presents the design of a 200–250-GHz compact vector modulator (VM) phase shifter in a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. A compact, low-loss, and wideband differential quadrature coupler is used to generate differential I/Q signals. The design details of the millimeter-wave wideband differential coupler is presented and compared with other I/Q generators by the 3-D electromagnetic (EM)-simulated results. The VM core is realized by two variable gain amplifiers based on Gilbert cell architecture. The measured phase shifter shows a gain of −10.3 dB for the maximum gain setting at 230 GHz. The phase shifter shows a −17 dB of gain for full 360° phase tuning range and a 10 dB of gain control. The maximum rms gain error and the phase error are 1.25 dB and 10°, respectively, from 200 to 250 GHz. The chip consumes a dc power of 55 mW and occupies a core area of 0.09 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 193-nW Wake-Up Receiver Achieving −84.5-dBm Sensitivity for Green Wireless Communications

This paper presents a cost-effective, ultra-low-power and highly sensitive wake-up receiver (WuRX) to reduce overall power consumption of Wireless Sensor Networks (WSN). The proposed tuned radio frequency (TRF) receiver (RX) analogue front-end (AFE) incorporates a 400-MHz, low-power, low-noise amplifier (LNA) with a high voltage gain of 50 dB as well as a Gilbert Cell based envelop detector achieving a conversion gain of 224V^&#x2212;1 to enhance the overall sensitivity of the WuRX. Meanwhile, a duty-cycling technique is used to reduce the power consumption of the WuRX AFE. In addition, a 31-bit correlator is implemented in the WuRX digital back-end (DBE) to further improve the sensitivity of the WuRX by 4 dB. A proof-of-concept WuRX circuit prototype has been fabricated in a low-cost 180-nm CMOS technology. Measurement results show the complete WuRX attains a sensitivity of &#x2212;84.5 dBm at a wake-up error rate (<i>WER</i>) of 10^&#x2212;3 whilst only consuming 193nW at the minimum data rate of 64 bps with a carrier frequency of 402 MHz. With the sensitivity unchanged, the data rate of the WuRX can be scaled up from 64 bps to 8.2 kbps. The used 4-time oversampling technique makes the WuRX robust against asynchronization and clock deviation between the TX and RX. The proposed WuRX is a promising solution for energy-efficient rendezvous between wireless sensor nodes, particularly in application scenarios where both low power consumption and high sensitivity are indispensable.

A 24‐GHz active up/down bidirectional mixer in 130‐nm RF CMOS

An active bidirectional mixer based on modified Gilbert cell has been proposed to perform the up/down conversion at 24 GHz in a 130-nm RF CMOS. Employing the transconductance gm/load sharing stage, the mixer not only reduces the required power of local oscillator (LO) signal, but also increases the linearity and the conversion gain (CG). With a 2-dBm LO power, the mixer achieves measured CG of −1.7 dB, noise figure (NF) of 14.6 dB, and output 1-dB compression point (OP1dB) of −8.4 dBm at 24 GHz in the up-conversion mode. In the down-conversion mode, the mixer exhibits measured CG of 2.6 dB, NF of 15.9 dB, and input 1-dB compression point (IP1dB) of −0.1 dBm at 24 GHz. From 23 to 25 GHz, the measured LO-to-RF and LO-to-IF isolations (ISOs) are better than 55 dB and 48 dB, respectively. The chip area including all testing pads is 0.75 × 0.8 mm2, which consumes 10.5 mW from a supply of 1.5 V.

An Inverter Amplifier with Resistive Feedback Current Mirror Gilbert Mixer

ABSTRACT A low-voltage, low-power, high-conversion-gain, short-range up-conversion Gilbert mixer for the licence-free band (865–867 MHz) in India is presented. In this work, the Gilbert cell transconductance stage is replaced by an inverter amplifier with a resistive feedback current mirror. The current bleeding technique is also applied to attain high conversion gain (CG) and low noise figure (NF). The design is realised in 180 nm CMOS SCL process technology and powered by 0.9 V. The proposed design offers a CG of 26.62 dB and an NF of 6.48 dB@866.5 MHz at the expense of an OIP3 of −3.3 dBm with the total power consumption of 1.94 mW. Its layout occupies a core area of 52 µm × 53 µm.

A 5–50 GHz SiGe BiCMOS Linear Transimpedance Amplifier with 68 dBΩ Differential Gain towards Highly Integrated Quasi-Coherent Receivers

Quasi-coherent optical receivers have recently emerged targeting access networks, offering improved sensitivity and reach over direct-detection schemes at the expense of a higher receiver bandwidth. Higher levels of system integration together with sufficiently wideband front-end blocks, and in particular high-speed linear transimpedance amplifiers (TIAs), are currently demanded to reduce cost and scale up receiver data rates. In this article, we report on the design and testing of a linear TIA enabling high-speed quasi-coherent receivers. A shunt-feedback loaded common-base topology is adopted, with gain control provided by a subsequent Gilbert cell stage. The circuit was fabricated in a commercial 130 nm SiGe BiCMOS technology and has a bandpass characteristic with a 3 dB bandwidth in the range of 5–50 GHz. A differential transimpedance gain of 68 dBΩ was measured, with 896 mVpp of maximum differential output swing at the 1 dB compression point. System experiments in a quasi-coherent receiver demonstrate an optical receiver sensitivity of −30.5 dBm (BER = 1 × 10−3) at 10 Gbps, and −26 dBm (BER = 1 × 10−3) at 25 Gbps. The proposed TIA represents an enabling component towards highly integrated quasi-coherent receivers.

Design and Performance Analysis of Low Power and High Throughput of Analog Data Compression and Decompression using ANN in 32nm FinFET Technology

The development and fabrication of integrated circuits for the applicational areas of VLSI such as processing of the signal, medicine tomography, telecommunication turn out to be a novel technology for the upcoming innovations. The fabrication of IC’s is attributable to the methodology in the technology of VLSI and when compared to artificial Neural Network, the genetic performance of these productions is approximately the same and are typically employed for diagnosing the syndrome, compression as well as the decompression of signal used in the medical domain. Techniques such as HMM, DCT, as well as PCA are employed for compression and decompression of signals but these approaches still possess some disadvantages. Therefore, to overcome these issues, a chip-level design for Artificial Neural Network is proposed that makes use of FinFET 32 nm technology and includes sigmoid activation function (SAF), Gilbert cell number, as well as bias circuits to prolong the compressed magnitude relation and accuracy. As a result, with the help of the Cadence Virtuoso analog tool, the Artificial Neural Network has been designed using FinFET 32nm technology along with all the details of sub-units such as Layout vs Schematic (LVS), Design rule check (DRC), RC extraction as well as chip level (GDS-II). Feed Forward Artificial Neural Network (FWANN) is considered as one of the most basic types of ANN and it is implemented using the concept of Back Propagation (BP). The simulation results of the suggested 16-bit 6TRAM cell were found to have 8%, 21%, and 0.9% improvement in consuming power, delay, and compressed data losses respectively.

Design of analog nonlinear transformations based on a Gilbert multiplier for energy detection

This paper focuses on the design of two analog nonlinear transformations dedicated to analog signal processing such as energy detection: the square function and the Teager Energy Operator (TEO). Both requiring an analog multiplier, this paper firstly analyses the design equations of a MOS Gilbert cell in order to operate around the mid supply voltage. Considering this, an analog multiplier, having a differential input range of ±400 mV, has been designed using an AMS 0.35 μm technology and a voltage supply (VDD) of 3.3 V. It has a core area of 620 μm2 and offers power-gating capability, which enables a power consumption of 2.28 μW when a duty cycle of 0.25% is considered. Next, an analog square function and an analog TEO, have been implemented and manufactured using the designed Gilbert cell. The analog square function has a core area of 0.9 mm2 and measurement results show that it is able to compute the square value of its differential input voltage with a mean precision of 2.92% in 5 μs assuming a differential input voltage of ±400 mV with a common voltage of VDD/2. Moreover, it generates 700 mV spikes when 200 mV pulses are applied on its input. Finally, the designed analog TEO has been implemented using its discrete time equation instead of its continuous time equation since it does not require derivatives computing. It has a core area of 2.2 mm2, an active power consumption of 6.21 mW and a standby power consumption of 1.43 nW. Measurement results shows that it generates until 250 mV spikes when 200 mV pulses are applied on its input.

A Mixed-Signal Chip-Based Configurable Coherent Photoacoustic-Radar Sensing Platform for In Vivo Temperature Monitoring and Vital Signs Detection

For precise health status monitoring and accurate disease diagnostics in the current COVID-19 pandemic, it is essential to detect various kinds of target signals robustly under high noise and strong interferences. Moreover, the health monitoring system is preferred to be realized in a small form factor for convenient mass deployments. A CMOS-integrated coherent sensing platform is proposed to achieve the goal, which synergetically leverages quadrature coherent photoacoustic (PA) detection and coherent radar sensing for achieving universal healthcare. By utilizing configurable mixed-signal quadrature coherent PA detection, high sensitivity and enhanced specificity can be achieved. In-phase (I) and quadrature (Q) templates are specifically designed to accurately sense and precisely reconstruct the target PA signals in a coherent mode. By mixed-signal implementation leveraging an FPGA to generate template waveforms adaptively, accurate tracking and precise reconstruction on the target PA signal can be attained based on the early-late tracking principle. The multiplication between the received PA signal and the templates is implemented efficiently in analog-domain by the Gilbert cell on-chip. In vivo blood temperature monitoring was realized based on the integrated PA sensing platform fabricated in a 65-nm CMOS process. With an integrated radar sensor deployed in the indoor scenario, noncontact monitoring on respiration and heartbeat rates can be attained based on electromagnetic (EM) sensing. By complementary usage of PA-EM sensing mechanisms, comprehensive health status monitoring and precise remote disease diagnostics can be achieved for the currentglobal COVID-19 pandemic and the future pervasive healthcare in the Internet of Everything (IoE) era.

Design and Analysis of a Reconfigurable Gilbert Mixer for Software-Defined Radios.

A reconfigurable -boosted, image-rejected downconversion mixer is presented in this paper using the SiGe 8 HP technology. The proposed mixer operates within 0.9–13.5 GHz that is suitable for software-defined radio applications. The conversion mixer comprises of resistive biased radio frequency (RF) section, double balanced Gilbert cell mixer core sections divided as per I and Q stages for image-rejection purpose, inductively peaked -boosting section and tunable filter section, respectively. In comparison to previous works in the scientific literature, the design shows enhanced conversion gain (CG), noise figure (NF), and image-rejection ratio (IRR). For the entire band of operation, the mixer attains a good return loss of <−10 dB. Additionally, the design accomplishes an excellent CG of 22 dB, NF of 2.5 dB, and an image-rejection ratio of 30.2 dB at maximum frequency. Finally, a third-order intercept point (IP3) of −3.28 dBm and 1 dB compression point (CP1) of −13 dBm, respectively, shows moderate linearity performance.

A K-Band Variable-Gain Phase Shifter Based on Gilbert-Cell Vector Synthesizer With RC–RL Poly-Phase Filter

A K-band variable-gain phase shifter using a Gilbert-cell vector synthesizer with a current digital-to-analog converter (DAC) and an RC-RL poly-phase filter (PPF) is presented, which is fabricated with a 65-nm RF CMOS process. It controls both gain and phase with low phase and gain variations as well as a low insertion loss. The Gilbert cell synthesizes a vector by summing in-phase (I) and quadrature (Q) phase signals of which the amplitudes are decided by the tail currents of the summing cells, respectively. The tail currents are given by current DACs, which are particularly designed to make the synthesizer have a constant output impedance in all phase and gain states. Because the gain and phase control resolutions depend on those of the current DACs, the size and insertion loss of the variable-gain phase shifter are not dependent on the control resolutions. The total root-mean-square (rms) phase and gain errors are measured to be 0.488° and 0.098 dB for 4096 states of the 7-bit 360° phase and 5-bit 17.8-dB gain controls, respectively, which are calibrated with extra 2-phase and 1-gain control bits. It shows -3.5 dB maximum gain including ON-chip balun losses with 6.6-mW dc power consumption.

Design and optimization of a CMOS IC novel RF tracking sensor

SummaryThis research reports the development of an RF sensor integrated circuit (IC) chip capable of tracking the directionality of RF remote emissions. The IC design uses an angle‐of‐arrival algorithm, and it is designed for the 180 nm CMOS technology and applicable to other technologies, also. The sensor chip requires two pairs of antennas aligned and placed at distance s for detection of azimuthal and polar angles of the RF incident wave. The circuit consists of custom designed low‐noise amplifiers (LNAs) at the front end, with a novel design of double‐balanced Gilbert cell mixers (GCMs). This amplifies and mixes the signals from the antennas and converts the phase difference Δφ into an equivalent output voltage map suitable for an 18‐bit analog to digital converter. Systematic optimization techniques were developed to maximize the third‐order intercept point and suppress flicker noise for the LNAs and GCMs, resulting in improved sensing accuracy. The overall system‐level evaluation results showed state‐of‐art angle‐of‐arrival sensing capability with an upper limit error of 3.447°.