GHz Voltage Research Articles

GHz voltage amplification in stack of piezoelectric ScAlN and non-piezoelectric SiO2 layers

Abstract GHz voltage amplification was found in a stacked structure of piezoelectric layers, such as ScAlN, and non-piezoelectric layers, such as SiO2. This allows for large-area fabrication using commercial equipment. This approach contributes to wireless sensor activation. The electromechanical coupling coefficients k t 2 of input and output layers were 17.6% and 13.7%, respectively. An experimental open-circuit voltage gain of 4.5 (+13 dB) at 0.8 GHz was observed, with a maximum transmission loss (S21) of -5 dB. The experimental result shows good agreement with the theoretical prediction simulated by electromechanical transmission line model.

Silicon-Organic Hybrid Electro-Optic Modulator and Microwave Photonics Signal Processing Applications.

Electro-optic modulator (EOM) is one of the key devices of high-speed optical fiber communication systems and ultra-wideband microwave photonic systems. Silicon-organic hybrid (SOH) integration platform combines the advantages of silicon photonics and organic materials, providing a high electro-optic effect and compact structure for photonic integrated devices. In this paper, we present an SOH-integrated EOM with comprehensive investigation of EOM structure design, silicon waveguide fabrication with Slot structure, on-chip poling of organic electro-optic material, and characterization of EO modulation response. The SOH-integrated EOM is measured with 3 dB bandwidth of over 50 GHz and half-wave voltage length product of 0.26 V·cm. Furthermore, we demonstrate a microwave photonics phase shifter by using the fabricated SOH-integrated dual parallel Mach-Zehnder modulator. The phase shift range of 410° is completed from 8 GHz to 26 GHz with a power consumption of less than 38 mW.

Design and Optimization of 4-Bit Array Multiplier with Adiabatic Logic Using 65 nm CMOS Technologies

ABSTRACT This paper proposes a 4-bit array multiplier useful in the design of basically mixer circuit, which is highly involved in signal and image processing using an efficient low-power VLSI technique. The presented architecture is completely implemented adiabatic techniques in the Near Threshold Region, which optimize the product of propagation delay and power dissipation. Multiplier is the most frequently used element in many digital electronics applications. Depending on the applications, various types of multipliers emerge. With this technique, the total power dissipation, i.e. dynamic power dissipation as well as static power dissipation is less as compared to the conventional CMOS technique. The Near Threshold Adiabatic Logic (NTAL) technique is used with a single timevarying power supply which reduces the clock tree management and enhances the energy-saving capability. Simulation of the proposed design is done by Cadence virtuoso schematic editor with specter simulator on TSMC 65 nm technology node to verify the optimized result. Also comparing our result to conventional CMOS techniques with all the same design parameters, the result shows that power dissipation improvement of approximately 66.6%, 14.4%, and 64.6% with respect to varying frequency, supply voltage, and load capacitance with other parameters keep constant such as if the frequency is varying than capacitance load value is C load = 10 pF and V DD(max) = 1.2 V, similarly if the supply voltage is varying than capacitance load value is C load = 10 pF and frequency F = 4 GHz and if load capacitance is varying than frequency F = 4 GHz and supply voltage V DD(max) = 1.2 V.

An end-fire low profile patch antenna to work on WiMAX frequencies used for harvesting power supply

In this paper, an end-fire microstrip patch antenna (MPA) is proposed of 3 GHz as a center frequency, designed, simulated, and measured to work on WiMAX frequencies within standard of 802.16e (WiMAX). A high gain ranged between (12.117-13.324) dB, high front to back ratio (F/B) of (35.770) at the center frequency, a wide band of 1.701 GHz, low profile, and semi-ideal voltage standing wave ratio (VSWR) of 1.053 is achieved. The simulation is done using computer simulation technology (CST-MW). The proposed design is based on two Fire-retardant substrates (FR-4) of relative permittivity (ε) 4.3+j0.025 and 1.53 mm thickness for each one, which is considered a high loss material. The measurement results show good agreement with the simulated results. In addition, the design can be used for harvesting power supply from mobile towers. Finally, the proposed design is compared with two other designs in terms of power conversion efficiency and overall size.

A 25 Gbps single‐end input limiting amplifier with loss of signal for low power integrated optical receivers

AbstractA 25 Gbps limiting amplifier (LA) with loss of signal (LOS) detection is presented in this paper. The proposed LA is composed of an input buffer, three‐stage cascaded amplifier, an output buffer, a DC offset cancellation (DCOC) and a LOS circuit. The LA adopts single‐end input and differential output structure to reduce the complexity of optical receiver front‐end and therefore decrease power consumption drastically. DCOC circuit consists of a low‐pass filter and an operation amplifier to extract the DC point of transimpedance amplifier output signal. Replica peak detector is employed in LOS to overcome the fluctuations of process, voltage, temperature (PVT). Fabricated in 0.13 μm SiGe BiCMOS technology, the LA acquires gain of 43.5, –3 dB bandwidth of 20.6 GHz and differential output voltage swing of 350 mV. With the 20 mV PRBS31 input data, the peak‐to‐peak jitter of output signal is 13.9 ps. When the input swing is larger than 40 mV, the peak‐to‐peak jitter is decreased to 7.5 ps. The whole LA with LOS chip only consumes 25.2 mW with a 1.8 V supply voltage.

Highly stable signal generation in microwave interferometer using PLLs

Abstract The microwave interferometer is a device that works in the millimeter-wave frequency range, and it is used to measure the plasma density. The instability in the frequency source at the transmitter section of the interferometer affects the accuracy of the phase measurement in the receiver section. The phase-locked loop (PLL) circuit is a substantial unit in the generation of highly stable frequency. This paper proposes a highly stable frequency source generator for the D-band Microwave interferometer. The design, development, and analysis of the PLL system with the frequency signal of 6.9 GHz and 7.0 is presented in this paper. Two alternate approaches using the dielectric resonator oscillator (DRO) and Frequency synthesizer are presented to design the PLL circuit. The stability is achieved using a 7 GHz DRO in the transmitter section, which is phase-locked with a 6.9 GHz voltage controlled oscillator (VCO) at the receiver section in the proposed first design and a frequency synthesizer is used instead of DRO in the proposed second design. The developed circuit is analysed in terms of parameters like phase noise performance, output power level, development cost, design complexity, and operating frequency range. The PLL in the receiver section is configured using FPGA to analyze the circuit performance at various frequency offset. DRO generates the power of 17.62 dB m at a frequency of 7.0 GHz. The DRO and synthesizer circuit provides excellent phase noise performance of -120 dBc/Hz and -93 dBc/Hz, respectively, at the transmitter section and -94.12 dBc/Hz at the receiver section. Indigenous methods have been made for the development of PLLs. It will be used to develop a D-band microwave interferometer to measure the electron density of fusion plasma at the Institute for plasma research (IPR)-Government of India.

A miniaturized high gain dipole array antenna for 2.4/5 GHz wireless local area network applications

AbstractA miniaturized high gain dipole array antenna for 2.4/5 GHz wireless local area network (WLAN) applications (2.4‐2.5/5.15‐5.85 GHz) is proposed in this paper. The proposed antenna is composed of a 1 × 3 dipole array, a U‐shaped branch, and a double‐layer feedline. Dual‐band operation is realized by using a double‐branch dipole. The peak gain of the proposed dipole array antenna is improved due to the in‐phase current distributions on dipole elements. A U‐shaped branch is added to further enhance the peak gain in the lower band. For miniaturization, the half‐cutting method is applied. One prototype of the proposed miniaturized antenna with a size of 168 × 10.5 × 0.6 mm3 is manufactured and measured. As a result, the proposed antenna provides the operating bands of 2.30 to 2.59 GHz and 5.10 to 6.73 GHz (voltage standing wave ratio ≤ 2), fully covering 2.4/5 GHz WLAN band. Over the lower/higher band, the peak gain and efficiency are higher than 4.2/5 dBi and 58%/49%, respectively. Furthermore, good omnidirectional radiation characteristic in the horizontal plane is achieved.

Analysis and Design of Integrated Blocks for a 6.25 GHz Spacefibre PLL.

The design of a Phase-Locked Loop (PLL) to generate the clock reference for the new Spacefibre standard is presented in this paper. Spacefibre has been recently released by the European Space Agency (ESA) and supports up to 6.25 Gbps for on-board satellite communications. Taking as a starting point a rad-hard 6.25 GHz Voltage Controlled Oscillator in 65 nm technology, this work presents the design of the key blocks for an integrated PLL: a Triple Modular Redundancy Phase/Frequency Detector, a Charge Pump, and a passive Loop Filter. The modeling activities carried out in an Advanced Design System have proven that the proposed PLL can be completely integrated on-chip, with a Loop Filter area consumption of only 6000 µm2 (considering the 65 nm technology). The design of active circuits has been carried out at the transistor level in a Cadence Virtuoso environment, implementing both system and layout rad-hard techniques, and different solutions are discussed in this paper. As a result, a compact (0.09 mm2), low power (10.24 mW), dead zone free and rad-hard PLL is obtained with a Phase Noise below −80 dBc/Hz @ 1 MHz. A preliminary block view and floor plan of the test chip is also proposed.

Analysis of Omega-Gate Nanowire SOI MOSFET Under Analog Point of View

This paper presents an evaluation of omega-gate nanowire n- and p-type SOI MOSFETs performance focusing on the main analog figures of merit. The different channel widths (WNW) and channel lengths (L) were also evaluated. These devices presented values of subthreshold slope near the theoretical limit at room temperature (60 mV/dec) and in the worst case a DIBL value smaller than 70 mV/V showing its immunity to short channel effects (SCEs) in the range studied. The narrowest device showed great electrostatic coupling, improving transconductance (gm), presenting an unit gain frequency over 200 GHz and intrinsic voltage gain over 80 dB. These values suggests that this device is capable of achieving good performance on new applications such as 5G communications and Internet-of-Things (IoT).

A Novel THz Forward and Backward Wave Two-Mode Band-Edge Oscillator

In this article, a novel two-mode operation concept for the THz oscillator with the folded waveguide is proposed. To demonstrate this concept, a two mode 4π band-edge oscillator has been simulated and fabricated. The simulation predicted that the designed oscillator was capable of delivering maximal output power of over 2 W at 301.7–303 GHz for both forward and backward operation mode. On the other hand, the testing data showed that the first prototype of the two-mode oscillator was able to produce output power over 1 W at about 305.6 GHz (voltage 23.04 kV) and 1.51 W at 308.8 GHz (voltage 24.33 kV), for forward and backward operation mode, respectively, with a 5–7 GHz frequency shift compared to the simulation. The findings demonstrate the correctness of the proposed two-mode concept for developing novel two-mode band-edge oscillators. There exist some inconsistencies between the testing and simulation, which will be discussed in the article. It is believed that the proposed two-mode concept is useful for the exploration of other novel two-mode band-edge oscillators, such as compact, high-power THz radiation sources for potential applications.

A heterogeneously integrated silicon photonic/lithium niobate travelling wave electro-optic modulator.

Silicon photonics is a platform that enables densely integrated photonic components and systems and integration with electronic circuits. Depletion mode modulators designed on this platform suffer from a fundamental frequency response limit due to the mobility of carriers in silicon. Lithium niobate-based modulators have demonstrated high performance, but the material is difficult to process and cannot be easily integrated with other photonic components and electronics. In this manuscript, we simultaneously take advantage of the benefits of silicon photonics and the Pockels effect in lithium niobate by heterogeneously integrating silicon photonic-integrated circuits with thin-film lithium niobate samples. We demonstrate the most CMOS-compatible thin-film lithium niobate modulator to date, which has electro-optic 3 dB bandwidths of 30.6 GHz and half-wave voltages of 6.7 V×cm. These modulators are fabricated entirely in CMOS facilities, with the exception of the bonding of a thin-film lithium niobate sample post fabrication, and require no etching of lithium niobate.

Design of Common-gate with Common-source Active Balun for WiMAX Receiver Front-end

This paper presents a design and simulation study of a common-gate with common-source active balun circuit implemented in a standard 90-nm complementary metal-oxide semiconductor (CMOS) process. The active balun design is intended for worldwide interoperability for microwave access (WiMAX) application, with operating frequency of 5.8 GHz and supply voltage of 1 V. Measurements are taken for parameters namely gain difference, phase difference, and noise figure. The common-source active balun design achieved a minimal gain difference of 0.04 dB, phase difference of 180 ± 1.5 degrees, and noise figure of 8.76 dB, which are comparable to past active balun designs and researches. The design eventually achieved a low power consumption of 4.45 mW.

Design of Common-Source/Drain Active Balun Using 90nm CMOS Technology

This research paper presents a design and study of a common-source/drain active balun circuit implemented in a standard 90-nm complementary metal-oxide semiconductor (CMOS) technology. The active balun design is intended for worldwide interoperability for microwave access (WiMAX) application, with operating frequency of 5.8GHz and supply voltage of 1V. Measurements are taken for parameters namely gain difference, phase difference, and noise figure. The common-source active balun design achieved a minimal gain difference of 0.016dB, phase difference of 180° ± 7.1°, and noise figure of 7.42-9.85dB, which are comparable to past active balun designs and researches. The design eventually achieved a low power consumption of 2.56mW.

Variation aware intuitive clock gating to mitigate on-chip power supply noise

ABSTRACTWith the advent of semiconductor process technology, both the dynamic and static power consumption have become major concerns for the circuit designers. Though clock gating (CG) is a potentially accomplished technique to minimise the dynamic power, it generally fails to cut down the static power dissipation. To address the same, we have unveiled a new CG scheme incorporating leakage control transistor, which simultaneously curbs the static and dynamic power along with the alleviation of power supply noise (PSN) in silicon chips by smartly controlling the current ramp (di/dt) and average current i(t): the main contributors to PSN. The proposed CG does not only save average, dynamic and static power by 84.34%, 90.33% and 66.73%, respectively, but also reduces PSN by 84.44% with respect to its non-gated counterpart when simulated using Cadence Virtuoso® for 90 nm Generic Process Design Kit at a switching frequency of 5 GHz and power supply voltage of 1.1 V.

Phase noise analysis of voltage controlled oscillator used in cesium atomic clock

Coherent population trapping (CPT) cesium frequency standard plays a significant role in precision guidance of missile and global positioning system (GPS). Low noise 4.596 GHz voltage controlled oscillator (VCO) is an indispensable part of microwave signal source in cesium frequency standard. Low-phase noise is also the most important and difficult performance indicator of VCO. Starting from phase noise analysis method proposed by Leeson, the formulas about the relationship between phase noise of output signal of oscillator feedback model and phase fluctuation spectrum of amplifier, phase noise of oscillator are derived in this paper. Finally, the asymptote model of microwave oscillator is proposed based on the formula derivation. The experiment shows that when the reverse bias voltage of variode is 1.8 V, the designed oscillation frequency of VCO is 4.596 GHz, the power is −1 dBm and the DC power consumption is 19.6 mW. The tendency of phase noise simulation curve and actual test curve conform to asymptote model. The phase noise in 1 and 10 kHz is, respectively, −60.86 and −86.58 dBc/Hz. The significance of the paper lies in determining the main factors influencing oscillator phase noise and providing guiding direction for the design of low-phase noise VCO.

Performance study of a 248 GHz voltage controlled hetero-integrated source in InP-on-BiCMOS technology

This paper presents the performance study of a 248 GHz voltage-controlled hetero-integrated signal source using indium phosphide (InP)-on-bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The source consists of a voltage controlled oscillator (VCO) in 0.25 µm BiCMOS technology and a frequency multiplier in 0.8 µm transferred-substrate InP-heterojunction bipolar transistor technology, which is integrated on top of the BiCMOS monolithic microwave integrated circuit in a wafer-level based benzocyclobutene bonding process. The vertical transitions from BiCMOS to InP in this process exhibit broadband properties with insertion losses below 0.5 dB up to 325 GHz. The VCO operates at 82.7 GHz with an output power of 6 dBm and the combined circuit delivers −9 dBm at 248 GHz with 1.22% tuning range. The phase noise of the combined circuit is −85 dBc/Hz at 1 MHz offset. The measured output return loss of the hetero-integrated source is >10 dB within a broad frequency range. This result shows the potential of the hetero integrated process for THz frequencies.

Physical design optimization of MOSFETs for millimeter wave and sub-millimeter wave circuits

Deep-scaled CMOS technologies have provided ultra-high speed devices and enabled the possibility to achieve integrated millimeter wave and sub-millimeter wave systemon-a-chip (SoC). However, the drawbacks and constraints of deep-scaled technologies require not only creative circuit design ideas but also accurate active device models and optimum physical design. The paper presents a systematic design approach to optimize active device physical design and build the corresponding model, which is exemplified through two layout examples. With the optimum active device physical design and new circuit design ideas, we have successfully demonstrated several key circuits in mm-wave/sub-mm-wave frequency ranges: a 450 GHz voltage controlled oscillator, a 200 GHz frequency divider, and a 200 GHz amplifier all in 65 nm bulk CMOS technologies. The availability of these key building blocks would benefit the realization of mm-wave/sub-mm-wave SoCs in the future.

A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects

This paper explores the general framework and prospects for on-chip and off-chip wireless interconnects implemented for high-performance computing (HPC) systems in the context of micro power wireless design. HPC interconnects demand very high (≥ 10 Gb/s) transmission rates using ultraefficient (~ 1 pJ/bit) transceivers over extremely short (≤ 100 cm) ranges. In an attempt to design such wireless interconnects, first a model for the wireless communication channel properties is developed. The use of CMOS-based energyefficient on-off keying (OOK) transceiver architectures operating in the 60-90 GHz bands is considered as a practical solution. In order to address strict performance requirements of wireless HPC interconnects, and taking advantage of the recent developments in device scaling, compact low-power and innovative circuits based on novel double-gate MOSFETs (DG-MOSFETs) are proposed in the implementation of the architecture. The performance of a compact low-noise amplifier (LNA) design using common source (CS) inductive degeneration with 32 nm DGMOSFETs is investigated by quantitative analysis and simulation. The proposed inductor-less two-stage cascode cascade LNA is optimized for 90 GHz operation and has the advantage of gain switching over its CMOS counterpart without the use of additional switching transistors, which makes it remarkably power efficient and faster. As further examples of efficient and compact DG-MOSFET circuits for OOK transceiver design, a three-stage CS 5 dB tunable power amplifier operating up to 90 GHz, and a novel 90 GHz voltage controlled oscillator are also presented. This is followed by the proposal of an array of four monopole antennas studied using full-wave EM solver.

Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer

<?Pub Dtl=""?> To provide wide frequency tuning range (FTR) with compact implementation area, a new inductive tuning method is introduced in this paper for CMOS 60 GHz voltage controlled oscillator (VCO). The inductive tuning is based on a switching inductor-loaded transformer by configuring different current return-paths in the secondary coil of the transformer. Different from previous inductive tuning methods, the proposed VCO topology can achieve wide FTR for multiple sub-bands at 60 GHz within compact area by only one transformer. Two 60 GHz VCOs are demonstrated in 65 nm CMOS with design targets for the maximum FTR and the balanced phase noise in each sub-band, respectively. As measured by experiments, the first VCO (asymmetric) achieves a wide FTR of 25.8% from 51.9 to 67.3 GHz with phase noise variation of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\pm$</tex></formula> 8.2 dB ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex></formula> 90.2 to <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex></formula> 106.7 dBc/Hz at 10 MHz offset) in all sub-bands; and the second VCO (symmetric) realizes a low phase noise variation of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\pm$</tex> </formula> 2.5 dB ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex> </formula> 105.9 to <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex> </formula> 110.8 dBc/Hz at 10 MHz offset) in all sub-bands with a FTR of 14.2% from 57.0 GHz to 65.5 GHz.

A 120 GHz Voltage Controlled Oscillator Integrated with 1/128 Frequency Divider Chain in 65 nm CMOS Technology

A 120 GHz voltage controlled oscillator (VCO) with a divider chain including an injection locked frequency divider (ILFD) and six static frequency dividers is demonstrated using 65-nm CMOS technology. The VCO is designed based on the LC cross-coupled push-push structure and operates around 120 GHz. The 60 GHz ILFD at the first stage of the frequency divider chain is based on a similar topology as the core of the VCO to ensure the frequency alignment between the two circuit blocks. The static divider chain is composed of D-flip flops, providing a 64 division ratio. The entire circuit consumes a DC power of 68.5 mW with the chip size of 1385 × 835 μm².