A 25 Gbps single‐end input limiting amplifier with loss of signal for low power integrated optical receivers

Abstract

AbstractA 25 Gbps limiting amplifier (LA) with loss of signal (LOS) detection is presented in this paper. The proposed LA is composed of an input buffer, three‐stage cascaded amplifier, an output buffer, a DC offset cancellation (DCOC) and a LOS circuit. The LA adopts single‐end input and differential output structure to reduce the complexity of optical receiver front‐end and therefore decrease power consumption drastically. DCOC circuit consists of a low‐pass filter and an operation amplifier to extract the DC point of transimpedance amplifier output signal. Replica peak detector is employed in LOS to overcome the fluctuations of process, voltage, temperature (PVT). Fabricated in 0.13 μm SiGe BiCMOS technology, the LA acquires gain of 43.5, –3 dB bandwidth of 20.6 GHz and differential output voltage swing of 350 mV. With the 20 mV PRBS31 input data, the peak‐to‐peak jitter of output signal is 13.9 ps. When the input swing is larger than 40 mV, the peak‐to‐peak jitter is decreased to 7.5 ps. The whole LA with LOS chip only consumes 25.2 mW with a 1.8 V supply voltage.