Generic Layout Research Articles

Modeling an Edge Computing Arithmetic Framework for IoT Environments.

IoT environments are forecasted to grow exponentially in the coming years thanks to the recent advances in both edge computing and artificial intelligence. In this paper, a model of remote computing scheme is presented, where three layers of computing nodes are put in place in order to optimize the computing and forwarding tasks. In this sense, a generic layout has been designed so as to easily achieve communications among the diverse layers by means of simple arithmetic operations, which may result in saving resources in all nodes involved. Traffic forwarding is undertaken by means of forwarding tables within network devices, which need to be searched upon in order to find the proper destination, and that process may be resource-consuming as the number of entries in such tables grow. However, the arithmetic framework proposed may speed up the traffic forwarding decisions as relaying on integer divisions and modular arithmetic, which may result more straightforward. Furthermore, two diverse approaches have been proposed to formally describe such a design by means of coding with Spin/Promela, or otherwise, by using an algebraic approach with Algebra of Communicating Processes (ACP), resulting in a explosion state for the former and a specified and verified model in the latter.

Modeling and validation of dynamic performances of timing belt driving systems

A modeling method for a generic layout of timing belt driving system (TBDS) is presented, and the formulas for modeling a meshed teeth belt, an automatic tensioner, and rotational pulleys are established. A numerical method consisting of an iterative algorithm for calculating the dynamic responses of system is proposed. One engine TBDS with a crankshaft, a camshaft and a tensioner is taken as a studying example. The method and the procedure for obtaining the dynamic responses are described and studied. The dynamic performance of the TBDS, such as oscillation angles of pulleys and tensioner arm, and the transmission error between pulleys, are calculated and compared with the measurement, which validates the presented method. The influence of tensioner performance (stiffness and damping), meshed teeth model and different belt pre-tensions on the dynamic responses of a TBDS system are investigated. The tensioner behavior and belt tension are also analyzed based on the calculated dynamic responses. The developed method presented in this paper can be used for predicting the dynamic responses, optimizing the parameters of an engine TBDS, and reducing the design period and the cost for prototype validation.

WARNING SYSTEM FOR NAVIGATION AND MOORED SHIPS IN PORTS

This paper describes the SWAMS ALERT system; a forecast and warning system based on the assessment of risks associated with navigation and moored ships in port areas. This system is based on HIDRALERTA, a previously developed system for overtopping and flooding in coastal and port areas. The basic idea is to use 72-hour sea waves’ forecasts and simulate their effect on ships, either in port approach maneuvers or when they are moored inside.This modular system consists of four modules: I – Sea waves characteristics; II - Navigation and mooring in port areas; III - Risk assessment and IV - Warning System. The system is implemented on a fully interactive user-friendly web platform.The system prototype was tested in the Azorean island of Terceira. A generic container ship and a specific berth in the container terminal of the Praia da Vitória port were chosen, as well as a generic mooring layout with six mooring cables and two fenders. This test case illustrates some of the system’s capabilities, namely its ability to forecast, not only wave characteristics on the specific site of the moored vessel, but also forces on mooring lines and fenders and the risk of pre-set thresholds being surpassed.

Abstract 1569: Optimizing transducer array configuration for treatment of pancreatic cancer using Tumor Treating Fields (TTFields)

Abstract Introduction TTFields is an antimitotic cancer treatment that utilizes low intensity (1-3 V/cm) alternating electric fields in the intermediate frequency (100-300 kHz) that are delivered in two orthogonal directions using 2 pairs of transducer arrays. TTFields are currently approved for Glioblastoma Multiforme (GBM). A phase II clinical trial (EF-20) showed that TTFields in combination with gemcitabine was safe in patients with locally advanced pancreatic cancer. Preclinical studies show that the effect of TTFields is intensity-dependent with a therapeutic threshold of 1 V/cm. Simulation-based studies show that the field distribution changes with array placement. Treatment planning with arrays positioned on the scalp to maximize field intensity to the tumor is standard of practice when treating GBM. Studies to examine array layout on the abdomen to maximize the field distribution in this region have not been done. In the EF-20 study, a generic layout was used. We used computer simulations to test how altering the transducer array layout on the mid-body alters the field distribution within the abdomen and pancreas. Methods To simulate delivery of TTFields to the abdomen, we used a realistic computerized model of a human male (DUKE 3.0 from ZMT-Zurich). Eight different layouts utilizing combinations of arrays with either 13 or 20 disks placed at different locations on the abdomen were simulated. In order to generate TTFields, an alternating voltage difference with a peak to peak magnitude of 100V and a frequency of 150 KHz was imposed on the outer surfaces of the disks of each pair of arrays. The simulations were performed using ZMT's Sim4Life V3.0 electro-quasi-static solver. For each pair of transducer arrays, the mean field intensity in the abdomen and chest, and in the pancreas and liver, was calculated. Results All eight layouts delivered fields with mean intensities of about 2 V/cm to the abdomen. The average field intensity delivered to the pancreas and the liver exceeded the therapeutic threshold of 1 V/cm for all layouts. The highest intensities were delivered to the pancreas by layouts in which a 20-disk array was placed at the middle of the back, and either a 20 disk array placed at the middle of the abdomen or a 13 disk array placed on the front-left side of the abdomen over the pancreas. Generally, field intensities in the pancreas are lower than in the rest of the abdomen because of the high electric conductivity of this organ. Conclusion This work shows that TTFields can be delivered to the pancreas with intensities well above the therapeutic threshold of 1 V/cm, and that altering the location of the arrays on the abdomen can influence the field intensity and distribution within the body. This work forms the basis for developing optimal strategies for delivering TTFields to the pancreas. Citation Format: Ariel Naveh, Ze'ev Bomzon, Noa Urman, Ofir Yesharim, Eilon D. Kirson, Uri Weinberg. Optimizing transducer array configuration for treatment of pancreatic cancer using Tumor Treating Fields (TTFields) [abstract]. In: Proceedings of the American Association for Cancer Research Annual Meeting 2017; 2017 Apr 1-5; Washington, DC. Philadelphia (PA): AACR; Cancer Res 2017;77(13 Suppl):Abstract nr 1569. doi:10.1158/1538-7445.AM2017-1569

An algorithm for automated layout of process description maps drawn in SBGN.

Motivation: Evolving technology has increased the focus on genomics. The combination of today’s advanced techniques with decades of molecular biology research has yielded huge amounts of pathway data. A standard, named the Systems Biology Graphical Notation (SBGN), was recently introduced to allow scientists to represent biological pathways in an unambiguous, easy-to-understand and efficient manner. Although there are a number of automated layout algorithms for various types of biological networks, currently none specialize on process description (PD) maps as defined by SBGN.Results: We propose a new automated layout algorithm for PD maps drawn in SBGN. Our algorithm is based on a force-directed automated layout algorithm called Compound Spring Embedder (CoSE). On top of the existing force scheme, additional heuristics employing new types of forces and movement rules are defined to address SBGN-specific rules. Our algorithm is the only automatic layout algorithm that properly addresses all SBGN rules for drawing PD maps, including placement of substrates and products of process nodes on opposite sides, compact tiling of members of molecular complexes and extensively making use of nested structures (compound nodes) to properly draw cellular locations and molecular complex structures. As demonstrated experimentally, the algorithm results in significant improvements over use of a generic layout algorithm such as CoSE in addressing SBGN rules on top of commonly accepted graph drawing criteria.Availability and implementation: An implementation of our algorithm in Java is available within ChiLay library (https://github.com/iVis-at-Bilkent/chilay).Contact: ugur@cs.bilkent.edu.tr or dogrusoz@cbio.mskcc.orgSupplementary information: Supplementary data are available at Bioinformatics online.

Novel Buffered Magnetic Logic Gate Grid

After many decades of steep progress in semiconductor industry the performance gain due to CMOS scaling will stop in the foreseeable future. This stems from the sharp risein factory costs and the growing severeness of physical limits. Power dissipation caused by leakage especially in mobile devices becomes a critical burden nowadays. A simple way to reduce power dissipation and the total power consumption is to shut downidle circuit parts. However, when these circuits are activated their previous state mustbe recovered. In order to avoid energy and time consuming recovery cycles non-volatile elements must be added to realize the desired instant ON capability. Here, spintronics is very appealing due to its non-volatility, fast switching, and high endurance.Even though some feasible solutions are already available and competitive with respect to energy consumption and speed, e.g. magnetic tunnel junction (MTJ) MRAM [1] and non-volatile CMOS MTJ hybrid circuits [2], they are still not able to challenge pure CMOS with regard to integration density. The reason is that the spintronic elements (commonly MTJs) are introduced as mere memory, while the actual computation is carried out by CMOS transistors. Therefore, additional transistors are required to read and write the MTJs, which rather leads to a decrease in integration density and power increase. Therefore, we propose a magnetic non-volatile flip flop [3] anda magnetic non-volatile shift register [4], which perform the actual computation also in the magnetic domain, thus, reducing complexity and allowing extremely small foot prints.In this work we present an extension of our idea for sequential logic towards a novel non-volatile magnetic logic gate grid facilitating non-volatile magnetic flip flops as bufferas well as shared memory. The magnetic logic gate grid comprises spin transfer torque (STT) majority gates and thenon-volatile flip flops and are positioned at two different levels. The STT majority gates are structurally and operationally compatible with the non-volatile flip flops [5].The majority gates are arranged in an array and linked to their respective neighbors by the non-volatile magnetic flip flops (see Fig. 1). This arrangement holds the benefits of a very dense layout, a highly regular structure, allows parallel execution of operations on the logic gates, and minimizes theenergy and time spend for information transport. It also supports the shift away from the Von Neumann architecture and its currently performance limiting continuous information flow between physically separated memory and computation units. Even more, the generic layout of the structure not only eases manufacturing, but also enables, together with the majority gates, highly reconfigureable logic and flexible allocation of employed resources like the number of used gates and buffers depending on the requirements of the task at hand. In order to illustrate the idea, consider a practical example like a full adder implemented in such a structure. A 1-bit full adder has three inputs A,B,Cin and two outputs Sum and Cout. The carry bit Cout is defined as Majority(A,B,Cin) and the Sum as A XOR B XOR Cin. In a first step Majority(A,B,Cin) is calculated and copied into a first flip flop FF1. Then Majority(A,B,NOT(Cin)) is calculated and copied into a second flip flop FF2. Finally Majority(NOT(FF1)),FF2,Cin) is calculated by using the results from the previous steps stored in FF1 and FF2 to calculate the Sum, which again is stored in a third flip flop FF3.One has to note that for a functional complete system negation must be available. This is realized by inverting the polarity of the applied pulse. Thus, Cout and Sum are calculated via a well defined set of subsequent majority and copy operations in the magnetic domain only. Since Cout and Sum are stored in the flip flops FF1 and FF3 and these are also accessible by neighboring gates their informationcan be used for futher processing elsewhere. This research is supported by the European Research Council through the Grant #247056 MOSILSPIN.

Autonomous Laser Guided Vehicle for Book Deposition in a Library

This paper proposes a technology to automate the book deposition process in a generic Library layout. It includes usage of autonomous vehicle in the library that is guided by an assembly of lasers. To prove the practicability of this proposal a physical prototype of an autonomous robot has been developed. The robot acts as an external storage unit for books and is capable of delivering them from the initial pre-defined point to the desired final destination.

A Semantic Scene Description Language for Procedural Layout Solving Problems

Procedural content generation is becoming more and more relevant to solve the problem of content creation for the ever growing virtual worlds of games, simulations and other applications. However, these procedures are often unintuitive or use vague parameters, making it somewhat difficult for a designer to express his or her creative intent. Even worse, most of these techniques lack an accessible and easy to use interface.We have developed a generic layout solving approach to automatically create sensible content for virtual worlds. In that context, this paper proposes a high-level scene description language that allows designers to specify particular types of scenes. This description language allows designers to easily specify which objects need to be present in a scene, their attributes, and possible interrelationships. Application of the language, based on the rich vocabulary taken from a semantic library, is illustrated with several examples, showing its flexibility, intuitiveness and ease of use.

Study of an optimization approach for a disposal tunnel layout, taking into account the geological environment with spatially heterogeneous characteristics

The geological environment has spatially heterogeneous characteristics with varied host rock types, fractures and so on. In this case the generic disposal tunnel layout, which has been designed by JNC, is not the most suitable for HLW disposal in Japan. The existence of spatially heterogeneous characteristics means that in the repository region there exist sub-regions that are more favourable from the perspective of long-term safety and ones that are less favourable. In order that the spatially heterogeneous environment itself may be utilized most effectively as a natural barrier system, an alternative design of disposal tunnel layout is required. Focusing on the geological environment with spatially heterogeneous characteristics, the authors have developed an alternative design of disposal tunnel layout. The alternative design adopts an optimization approach using a variable disposal tunnel layout. The optimization approach minimizes the number of locations where major water-conducting fractures are intersected, and maximizes the number of emplacement locations for waste packages. This paper will outline the variable disposal tunnel layout and its applicability.

Programming with C++ concepts

This paper explores the definition, applications, and limitations of concepts and concept maps in C++, with a focus on library composition. We also compare and contrast concepts to adaptation mechanisms in other languages. Efficient, non-intrusive adaptation mechanisms are essential when adapting data structures to a library’s API. Development with reusable components is a widely practiced method of building software. Components vary in form, ranging from source code to non-modifiable binary libraries. The Concepts language features, slated to appear in the next version of C++, have been designed with such compositions in mind, promising an improved ability to create generic, non-intrusive, efficient, and identity-preserving adapters. We report on two cases of data structure adaptation between different libraries, and illustrate best practices and idioms. First, we adapt GUI widgets from several libraries, with differing APIs, for use with a generic layout engine. We further develop this example to describe the run-time concept idiom, extending the applicability of concepts to domains where run-time polymorphism is required. Second, we compose an image processing library and a graph algorithm library, by making use of a transparent adaptation layer, enabling the efficient application of graph algorithms to the image processing domain. We use the adaptation layer to realize a few key algorithms, and report little or no performance degradation.

The influence of training length on generalization of visual feature assemblies in honeybees

Generalization is a fundamental cognitive ability that allows treating similar stimuli as equivalents, and thus responding to them in the same manner. Here, we show that after training free-flying bees with a single, constant pair of patterns made of four quadrants, each displaying different oriented gratings, bees extract the orientation information corresponding to each quadrant and integrate it in a generic layout that preserved the spatial relationship between oriented edges. Our results show that the amount of experience with the training patterns is critical to determine or not generalization to novel stimuli sharing the layout of the rewarded stimulus. Increasing experience results in higher generalization levels reflected in significant responding to novel stimuli. With ongoing training, redundant information seems to be eliminated and reduced to the minimum that is necessary and sufficient to solve the task. Controlling precisely the level of experience of individuals is therefore crucial in experiments on visual recognition

A Simulation free Reduction Scheme and Nonlinear Modelling of an Electrostatic Beam

In this paper, a new approach to the model order reduction of a type of singular nonlinear systems is presented. This approach does not need simulation or linearization of the original system and therefore, it is suitable for large systems. By separating the linear and nonlinear parts of the original nonlinear model, the idea is considering the nonlinearities of the resulting system as additional inputs and applying a Krylov subspace method. We apply the method for reduced order modelling of an electrostatic actuated beam model which is a typical structure whose generic layout corresponds to an RF switch as well as an RF electromechanical filter.

Time-of-flight spin echo

IN15 has been built in the framework of a collaboration between the ILL, HMI Berlin and FZ-Jiilich as an answer to the ever increasing need of higher resolution and higher intensity. NSE, unlike conventional quasielastic instruments (TOF or backscanering), measures S(q,t), the intermediate scattering hncrion. As described in ref. [1] this is achieved by using the Larmor precession as a clock attached to each neutron, thus decoupling monochromatization from energy resolurion. The generic layout of an NSE insrrument consists of a moderately (10–15% FWHM) monochromatic and polarized beam, a π flipper which flips the spins perpendicular to the magnetic field and starts the Larmor precession. In a first precession region (e.g. asolenoid) the spins accumulate a high number of turns (−l04). A π flipper close to the sample reverses the precession direction, followed by a second precession regon in which the spins wind back. Finally a second π flipper stops the precession and the scatrered beam goes through an analyzer (e.g. supermirrors) before reaching the detector. If the magnetic field integral of the two precession regions is the same, the initial polarization is recovered. A small energy exchange during the scattering process inthe sample will make the neutron precess more (energy loss) or less (energy gain) in the second half of the spectrometer. Integrating over all energy exchanges the recovered beam polarization isdiminished and becomes a measure of the quasielastic broadening. This way of measuring introducesan automatic Fourier transform of S(q,w) leading directly to S(q,t). The time constant is a function of the field inregral namely:

Customization of system software for large-scale embedded applications

Operating systems are one of the most frequently reused software components: almost every application is sitting on top of an OS which establishes the required runtime platform. It is claimed that bridging the gap between a high level application design and the OS is a costly process, especially in distributed systems. A conceptual framework is presented which aims at supporting the automatic generation of distributed runtime platforms from high-level application designs. It is based on the generic layout of operating system services, their extended description including nonfunctional properties, as well as analysis and development tools which filter out OS requirements from the application design.

QUADTREE LAYOUTS AND I/O BANDWIDTH

Quadtree data structure, popular in 2-D applications, has not been studied in the context of VLSI embedding. This paper proposes two generic layout strategies for quadtree layout. Layout attributes are derived with primary focus on area-I/O trade-off. We demonstrate a simple layout mixing strategy to obtain improved boundary I/O characteristics. This is followed by development of a recursive layout mixing strategy which yields an order of improvement.

Systematic capacitance matching errors and corrective layout procedures

Precise capacitor ratios are employed in a variety of analog and mixed signal integrated circuits. The use of identical unit capacitors to form larger capacitances can easily produce 1% accuracy, but, in many cases, 0.1% accuracy can provide important performance advantages. Unfortunately, the ultimate matching precision of the ratio is limited by a number of systematic and random error sources. We have analyzed the source and significance of the systematic error sources on actual integrated circuit layouts and isolated five key contributors. Based on this analysis, we have developed a list of generic layout rules and a layout scheme that predict matching accuracies better than 0.1% for the individual systematic error sources using capacitor sizes in the range of 20-40 /spl mu/m.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Housing site layout system

An approach to c.a.a.d. systems design directed at housing site layout is presented. This refers to user interests, the distinction between real and generic layout proposals, and the generation of three-dimensional information. The systems strategy is outlined in terms of input options, description of design elements, and storage of layout geometry. The resulting system is described by reference to its operating procedure and its design functions.