True Random Number Generator Research Articles

Randomness quantification for quantum random number generation based on detection of amplified spontaneous emission noise

The amplified spontaneous emission (ASE) noise has been extensively studied and employed to build quantum random number generators (QRNGs). While the previous relative works mainly focus on the realization and verification of the QRNG system, the comprehensive physical model and randomness quantification for the general detection of the ASE noise are still incomplete, which is essential for the quantitative security analysis. In this paper, a systematical physical model for the detection and acquisition of the ASE noise with added electronic noise is developed and verified, based on which the numerical simulations are performed under various setups and the simulation results all significantly fit well with the corresponding experimental data. Then, a randomness quantification method and the corresponding experimentally verifiable approach are proposed and validated, which quantifies the randomness purely resulted from the quantum process and improves the security analysis for the QRNG based on the detection of the ASE noise. The physical model and the randomness quantification method proposed in this paper are of significant feasibility and applicable for the QRNG system with randomness originating from the detection of the photon number with arbitrary distributions.

Spurious OLS Estimators of Detrending Method by Adding a Linear Trend in Difference-Stationary Processes—A Mathematical Proof and Its Verification by Simulation

Adding a linear trend in regressions is a frequent detrending method in economic literatures. The traditional literatures pointed out that if the variable considered is a difference-stationary process, then it will artificially create pseudo-periodicity in the residuals. In this paper, we further show that the real problem might be more serious. As the Ordinary Least Squares (OLS) estimators themselves are of such a detrending method is spurious. The first part provides a mathematical proof with Chebyshev’s inequality and Sims–Stock–Watson’s algorithm to show that the OLS estimator of trend converges toward zero in probability, and the other OLS estimator diverges when the sample size tends to infinity. The second part designs Monte Carlo simulations with a sample size of 1,000,000 as an approximation of infinity. The seed values used are the true random numbers generated by a hardware random number generator in order to avoid the pseudo-randomness of random numbers given by software. This paper repeats the experiment 100 times, and gets consistent results with mathematical proof. The last part provides a brief discussion of detrending strategies.

An 8.4 Gbps real-time quantum random number generator based on quantum phase fluctuation

Based on the fundamental uncertainty of quantum mechanics, quantum random number generators can generate truly random number which is critically important for many applications, such as information security. However, while the generation rate of offline quantum random number generators could be up to tens of Gbps or more, that of real-time quantum random number generators is only 3.2 Gbps due to the relatively low post-processing speed, and the application of real-time quantum random number generators is limited. We propose an efficient and robust high-speed real-time quantum random number generation scheme based on quantum phase fluctuation of a distributed feedback laser, with improved post-processing techniques. Firstly, the quantum signal-to-noise ratio is increased by analyzing and quantifying quantum noise. Secondly, a time-interleaved analog-to-digital converter scheme is designed to achieve a real-time sampling rate of 8 GSa/s. Finally, the random bits are extracted using the minimum entropy estimation and Toeplitz-hashing randomness extraction. Experimental results show that the proposed scheme could achieves a real-time generation rate up to 8.4 Gbps, with an estimated offline generation rate of 82.32 Gbps.

Silicon single-electron random number generator based on random telegraph signals at room temperature

The need for hardware random number generators (HRNGs) that can be integrated in a silicon (Si) complementary-metal–oxide–semiconductor (CMOS) platform has become increasingly important in the era of the Internet-of-Things (IoT). Si MOSFETs exhibiting random telegraph signals (RTSs) have been considered as such a candidate for HRNG, though its application has been hindered by RTS’s variability and uncontrollable, unpredictable characteristics. In this paper, we report the generation and randomness evaluation of random numbers from RTSs in a Si single electron pump (SEP) device at room temperature. SEP devices are known to consistently produce RTSs due to a quantum dot electrically defined by multi-layer polycrystalline Si gates. Using RTSs observed in our devices, random numbers were extracted by a classifier supported by supervised learning, where part of data was used to train the classifier before it is applied to the rest to generate random numbers. The random numbers generated from RTSs were used as inputs for the Monte Carlo method to calculate the values of π, and the distribution was compared against the result obtained from the Mersenne Twister, a representative pseudo-random number generator (PRNG), under the same condition. π was estimated more than 80 000 times, and the distribution of the estimated values has a central value of 3.14 with a variance of 0.273, which is only twice as large as the result from PRNG. Our result paves a way to fully electronic CMOS compatible HRNGs that can be integrated in a modern system-on-a-chip in IoT devices.

Practical decoy-state quantum random number generator with weak coherent sources

Considering imperfect experimental conditions, here we give a practical proposal on the decoy-state quantum random number generator with weak coherent sources. In the proposal, three different intensities of light sources are used to estimate the contribution of single-photon pulses. System randomness is characterized and simulated through the minimum entropy. Numerical simulation results show that our new scheme can extract out randomness close to the asymptotic case where the fraction of single-photon pulses are exactly known. Furthermore, a proof-of-principle experimental demonstration is presented, showing excellent agreement between experiment and theory.

A fully CMOS true random number generator based on hidden attractor hyperchaotic system

Low-power devices used in Internet-of-things networks have been short of security due to the high power consumption of random number generators. This paper presents a low-power hyperchaos-based true random number generator, which is highly recommended for secure communications. The proposed system, which is based on a four-dimensional chaotic system with hidden attractors and oscillators, exhibits rich dynamics. Numerical analysis is provided to verify the dynamic characteristics of the proposed system. A fully customized circuit is deployed using 130 nm CMOS technology to enable integration into low-power devices. Four output signals are used to seed a SHIFT-XOR-based chaotic data post-processing to generate random bit output. The chip prototype was simulated and tested at 100 MHz sampling frequency. The hyperchaotic circuit consumes a maximum of 980 upmu W in generating chaotic signals while dissipates a static current of 623 upmu A. Moreover, the proposed system provides ready-to-use binary random bit sequences which have passed the well-known statistical randomness test suite NIST SP800-22. The proposed novel system design and its circuit implementation provide a best energy efficiency of 4.37 pJ/b at a maximum sampling frequency of 100 MHz.

Quantum random number generation based on spontaneous Raman scattering in standard single-mode fiber.

We investigate quantum random number generation based on backward spontaneous Raman scattering in standard single-mode fiber, where the randomness of photon wavelength superposition and arrival time is simultaneously utilized. The experiment uses four avalanche photodiodes working in gated Geiger mode to detect backward Raman scattering photons from four different wavelength channels and a time-to-digital converter placed behind the detectors to record their arrival time. Both information of the wavelength and arrival time interval of photons from different channels are applied to generate random bits. Due to the independence of these two entropy sources, the random number resource of the present system is fully utilized. Five-bit raw data can be obtained for every effective click, which contains 2.87-bit min-entropy. To obtain the optimal generation rate of random bits, appropriate pump power and fiber length are adopted. The post-processing method by the SHA-256 hashing algorithm is used to remove the bias of the raw data, after which the final random bit sequences pass the NIST statistical test.

Improved Performance of SRAM-Based True Random Number Generator by Leveraging Irradiation Exposure.

Encryption is an important step for secure data transmission, and a true random number generator (TRNG) is a key building block in many encryption algorithms. Static random-access memory (SRAM) chips can be easily available sources of true random numbers, benefiting from noisy SRAM cells whose start-up values flip between different power-on cycles. Embarking from this phenomenon, a novel performance (i.e., randomness and throughput) improvement method of SRAM-based TRNG is proposed, and its implementation can be divided into two phases: irradiation exposure and hardware postprocessing. As the randomness of original SRAM power-on values is fairly low, ionization irradiation is utilized to enhance its randomness, and the min-entropy can increase from about 0.03 to above 0.7 in the total ionizing irradiation (TID) experiments. Additionally, while the data remanence effect hampers obtaining random bitstreams with high speed, the ionization irradiation can also weaken this impact and improve the throughput of TRNG. In the hardware postprocessing stage, Secure Hash Algorithm 256 (SHA-256) is implemented on a Field Programmable Gate Array (FPGA) with clock frequency of 200 MHz. It can generate National Institute of Standards and Technology (NIST) SP 800-22 compatible true random bitstreams with throughput of 178 Mbps utilizing SRAM chip with 1 Mbit memory capacity. Furthermore, according to different application scenarios, the throughput can be widely scalable by adjusting clock frequency and SRAM memory capacity, which makes the novel TRNG design applicable for various Internet of Things (IOT) devices.

Set-Based Obfuscation for Strong PUFs Against Machine Learning Attacks

Strong physical unclonable function (PUF) is a promising solution for device authentication in resource-constrained applications but vulnerable to machine learning (ML) attacks. In order to resist attack, many defenses have been proposed in recent years. However, these defenses incur high hardware overhead, degenerate reliability and are inefficient against advanced ML attacks such as approximation attacks. To address these issues, we propose a Random Set-based Obfuscation (RSO) for Strong PUFs to resist ML attacks. The basic idea is that several stable responses are derived from the PUF itself and pre-stored as the set for obfuscation in the testing phase, and then a true random number generator is used to select any two keys to obfuscate challenges and responses with XOR operations. When the number of challenge-response pairs (CRPs) collected by the attacker exceeds the given threshold, the set will be updated immediately. In this way, ML attacks can be prevented with extremely low hardware overhead. Experimental results show that for a 64 × 64 Arbiter PUF, when the size of set is 32 and even if 1 million CRPs are collected by attackers, the prediction accuracies of the several ML attacks we use are about 50% which is equivalent to the random guessing.

Random-telegraph-noise-enabled true random number generator for hardware security

The future security of Internet of Things is a key concern in the cyber-security field. One of the key issues is the ability to generate random numbers with strict power and area constrains. “True Random Number Generators” have been presented as a potential solution to this problem but improvements in output bit rate, power consumption, and design complexity must be made. In this work we present a novel and experimentally verified “True Random Number Generator” that uses exclusively conventional CMOS technology as well as offering key improvements over previous designs in complexity, output bitrate, and power consumption. It uses the inherent randomness of telegraph noise in the channel current of a single CMOS transistor as an entropy source. For the first time multi-level and abnormal telegraph noise can be utilised, which greatly reduces device selectivity and offers much greater bitrates. The design is verified using a breadboard and FPGA proof of concept circuit and passes all 15 of the NIST randomness tests without any need for post-processing of the generated bitstream. The design also shows resilience against machine learning attacks performed by the LSTM neural network.

Deep Learning-Based Security Verification for a Random Number Generator Using White Chaos.

In this paper, a deep learning (DL)-based predictive analysis is proposed to analyze the security of a non-deterministic random number generator (NRNG) using white chaos. In particular, the temporal pattern attention (TPA)-based DL model is employed to learn and analyze the data from both stages of the NRNG: the output data of a chaotic external-cavity semiconductor laser (ECL) and the final output data of the NRNG. For the ECL stage, the results show that the model successfully detects inherent correlations caused by the time-delay signature. After optical heterodyning of two chaotic ECLs and minimal post-processing are introduced, the model detects no patterns among corresponding data. It demonstrates that the NRNG has the strong resistance against the predictive model. Prior to these works, the powerful predictive capability of the model is investigated and demonstrated by applying it to a random number generator (RNG) using linear congruential algorithm. Our research shows that the DL-based predictive model is expected to provide an efficient supplement for evaluating the security and quality of RNGs.

Ring oscillator as confusion – diffusion agent: a complete TRNG drove image security

The utility of true random number generators (TRNGs) is not only restricted to session key generation, nonce generation, OTP generation etc. in cryptography. In the proposed work, two ring oscillator (RO) based TRNG structures adopting identical and non-identical ring of inverters have alone been employed for confusion (scrambling) and diffusion (intensity variation) processes for encrypting the greyscale and RGB images. Cyclone IVE EP4CE115F29C7 FPGA was utilised to generate a couple of random synthetic images using the two RO architectures which took a maximum of 520 combinational units and 543 logic registers. The suggested scheme of image encryption was tested on 100 test greyscale images of size 256 × 256. This non-chaos influenced image ciphering has resulted in an approximate average entropy of 7.99 and near-zero correlation figures for the greyscale & RGB cipher images. The attack resistance capability was checked by performing various occlusion and noise attacks on encrypted images.

Low‐cost TRNG IPs

This study presents a low-cost multi-throughput true random number generator (TRNG) intellectual property (IP) based on a variable-length multi-mode ring oscillator. The proposed TRNG implements a multi-throughput feature by bypassing inverter cells in the ring oscillator for reducing the loop delay. This multi-throughput feature offers the advantage of high-performance or low-power operation when needed. These options make the proposed TRNG suitable for end-to-end encryption in highly restricted devices such as Internet of Things sensor nodes. Measurement results show that the proposed TRNG passes national institute of standards and technology (NIST) tests for different throughput operations. The TRNG is embedded in a reduced instruction set computer V (RISC-V)-based system-on-chip (SoC) for periodical-driven applications, and it achieves an energy efficiency of 92 pJ at 3.7 Mbps, occupying 58 μ m × 150 μ m in a 180 nm technology. This study also presents a system technique to implement the entropy enhanced TRNGs, using multiple entropy sources. An extraction system provides high-quality random numbers with a sampling method that takes one entropy output to sample the other entropy sources. The system requires few resources, using low-cost TRNG IPs as entropy sources.

Practical source-independent quantum random number generation with detector efficiency mismatch

Quantum random number generators (QRNGs) are widely used in information processing tasks. The quality of the random numbers obtained from QRNGs relies on the accurate characterization of the physical implementations. In practice, realistic devices are difficult to characterize, resulting in incorrect entropy estimations of the output random numbers. Recently, a novel quantum random number generation (QRNG) scheme, referred to as source-independent QRNG (SIQRNG), has attracted a lot of interest. The scheme can provide certified randomness by using untrusted and uncharacterized sources, under the assumption that the measurement devices are trusted. However, realistic devices inevitably feature imperfections. Here, we show that the output randomness of SIQRNG is compromised in the presence of detection imperfection , by constructing an attack based on a time-domain detection efficiency mismatch between two practical detectors. More importantly, we provide an unconditional security proof of SIQRNG that takes detection efficiency mismatch into account. In addition, we provide a parameter optimization method to effectively improve the final random number generation rate. Our work demonstrates that SIQRNG is highly practical and that randomness can be extracted even in the presence of a detection efficiency mismatch.

Hardware Random Number Generator Using Josephson Oscillation and SFQ Logic Circuits

A hardware random number generator using Josephson oscillation and a few single flux quantum (SFQ) logic gates is presented. The logic circuit of the random number generator consists of one toggle flip flop and one and gate. A prototype random number generator is designed by logic cells based on a 2.5-kA/cm2 Nb/AlOx/Nb integration process. The fundamental operation at a few hundred megahertz of the random number sampling frequency is confirmed by numerical simulation when a DC/SFQ converter is used for generating trigger signals. An additional delay line using an overdamped Josephson transmission line is used for increasing the timing jitter to get random numbers. The delay line makes it possible for the random number generator to operate over 1 GHz. To confirm the fundamental operation of the circuit, a primitive SFQ random number generator is fabricated using the AIST standard process with 2.5-kA/cm2 Nb/AlOx/Nb junctions and the standard logic cell library. A random number generation based on a low-speed functional test is successfully confirmed.

0.4 mW, 0.27 pJ/bit true random number generator using jitter, metastability and current starved topology

This study introduces the design of true random number generator (TRNG) using jitter, metastability and current starved topology. The proposed design consisted of a current starved inverter-based ring oscillator (RO) with a high-frequency divider block (designed by T-FF followed by D-FF to address setup and hold time issues), jitter extraction and metastable block followed by two sampling blocks. The design avails fewer amenities to yield the reduction in hardware and enhances the degree of randomness. The post-layout simulation of the proposed work was performed using a 180 nm CMOS technology environment in the Cadence Virtuoso tool. The speed and power dissipation achieved are 1.5 Gbps and 0.4 mW, respectively, with an efficiency of 0.27 pJ/bit. The effect of temperature and variation in supply voltages (by 10% around its nominal value) is also investigated on the generated random numbers through parametric analysis. For validation of randomness, the generated random signals are first sampled and then converted in binary format using MATLAB and finally verified by Kolmogorov–Smirnov and Chi-square test for the uniformity and independency. The validity of the proposed work is done by NIST 800.22 statistical test suite. The proposed TRNG design achieved a very high-pass efficiency.

An optical chip for self-testing quantum random number generation

We present an implementation of a semi-device-independent protocol of the generation of quantum random numbers in a fully integrated silicon chip. The system is based on a prepare-and-measure scheme, where we integrate a partially trusted source of photons and an untrusted single photon detector. The source is a silicon photomultiplier, which emits photons during the avalanche impact ionization process, while the detector is a single photon avalanche diode. The proposed protocol requires only a few and reasonable assumptions on the generated states. It is sufficient to measure the statistics of generation and detection in order to evaluate the min-entropy of the output sequence, conditioned on all possible classical side information. We demonstrate that this protocol, previously realized with a bulky laboratory setup, is totally applicable to a compact and fully integrated chip with an estimated throughput of 6 kHz of the certified quantum random bit rate.

Holographically controlled random numbers from entangled twisted photons

We present a quantum random number generator (QRNG) based on the random outcomes inherent in projective measurements on a superposition of quantum states of light. Firstly, we use multiplexed holograms encoded on a spatial light modulator to spatially map down-converted photons onto a superposition of optical paths. This gives us full digital control of the mapping process which we can tailor to achieve any desired probability distribution. More importantly, we use this method to account for any bias present within our transmission and detection system, forgoing the need for time-consuming and inefficient unbiasing algorithms. Our QRNG achieved a min-entropy of $\text{H}_{\text{min}}=0.9991\pm0.0003$ bits per photon and passed the NIST statistical test suite. Furthermore, we extend our approach to realise a QRNG based on photons entangled in their orbital angular momentum (OAM) degree of freedom. This combination of digital holograms and projective measurements on arbitrary OAM combinations allowed us to generate random numbers with arbitrary distributions, in effect tailoring the system's entropy while maintaining the inherent quantum irreproducibility. Such techniques allow access to the higher-dimensional OAM Hilbert space, opening up an avenue for generating multiple random bits per photon.

The euploid blastocysts obtained after luteal phase stimulation show the same clinical, obstetric and perinatal outcomes as follicular phase stimulation-derived ones: a multicenter study.

The euploid blastocysts obtained after luteal phase stimulation show the same clinical, obstetric and perinatal outcomes as follicular phase stimulation-derived ones: a multicenter study.

True Random Number Generation Using Latency Variations of FRAM

True random number generation (TRNG) plays an important role in security applications and protocols. In this article, we propose an effective technique to generate a robust true random number using emerging, energy-efficient, nonvolatile, consumer-off-the-shelf (COTS) ferroelectric random access memory (FRAM) chips. In the proposed method, we extract inherent randomness from internal ferroelectric capacitors by exploiting latency variation across cells within FRAM. Hardware results and subsequent National Institute of Standards and Technology (NIST) statistical test suite (STS) testing indicate that the proposed latency-based TRNG is robust over a wide range of operating conditions at speeds of 6.23 Mb/s using COTS, silicon FRAM chips from Cypress Semiconductor Corporation.