General Purpose Multipliers Research Articles

ISA Extensions for Finite Field Arithmetic

We present and evaluate a custom extension to the RISC-V instruction set for finite field arithmetic. The result serves as a very compact approach to software-hardware co-design of PQC implementations in the context of small embedded processors such as smartcards. The extension provides instructions that implement finite field operations with subsequent reduction of the result. As small finite fields are used in various PQC schemes, such instructions can provide a considerable speedup for an otherwise software-based implementation. Furthermore, we create a prototype implementation of the presented instructions for the extendable VexRiscv core, integrate the result into a chip design, and evaluate the design on two different FPGA platforms. The effectiveness of the extension is evaluated by using the instructions to optimize the Kyber and NewHope key-encapsulation schemes. To that end, we also present an optimized software implementation for the standard RISC-V instruction set for the polynomial arithmetic underlying those schemes, which serves as basis for comparison. Both variants are tuned on an assembler level to optimally use the processor pipelines of contemporary RISC-V CPUs. The result shows a speedup for the polynomial arithmetic of up to 85% over the basic software implementation. Using the custom instructions drastically reduces the code and data size of the implementation without introducing runtime-performance penalties at a small cost in circuit size. When used in the selected schemes, the custom instructions can be used to replace a full general purpose multiplier to achieve very compact implementations.

Multiplierless Implementation of Digital Colored Noise Generator

Colored noise can be generated by filtering of the white noise. It is a simple task. However, it becomes challenging if high operating speed of the generator is required. The realization of digital filter generally requires one multiplication per coefficient. Therefore, a high operating speed is achieved only with the cost of several general-purpose multipliers. In this paper, a multiplierless realization of the colored noise generator is proposed. It is based on the filtering of 1-bit random signal by a finite impulse response filter. The design of the generator is described and its implementation is considered. Furthermore, an application is described in which the proposed generator is used in mitigation of undesired effects caused by nonlinearities in an analog to digital converter.

The Impact of Alternative Encoding Techniques on Field Programmable Gate Array Implementation of Sigma-Delta Modulated Ternary Finite Impulse Response Filters

This paper presents the design and synthesis of a single-bit ternary finite impulse response filter with balanced ternary coefficients (ie. -1, 0, +1) implemented in VHDL on small commercial field programmable gate arrays (FPGAs). A comparison is made between implementations based on 2s complement, redundant binary signed digit (RBSD) and canonical signed digit (CSD) encoding techniques. Through simulation, the area and performance of an example filter are analysed using pipelined and non-pipelined modes for all three techniques. The simulation results show that, unlike in the equivalent multi-bit filters, CSD offers no advantages in single-bit sigma-delta modulated (∑ΔM) systems. Similarly, RBSD occupies twice the area and exhibits much poorer performance compared to a conventional 2s complement representation due to the small symbol size in single-bit systems. These results demonstrate that simple, short word length ∑ΔM filters will be useful in greatly reducing the number of general-purpose digital multipliers in general purpose digital signal processor applications using FPGA and especially ASIC.

New Iterative Framework for Frequency Response Mismatch Correction in Time-Interleaved ADCs: Design and Performance Analysis

This paper proposes a new iterative framework for the correction of frequency response mismatch in time-interleaved analog-to-digital converters. Based on a general time-varying linear system model for the mismatch, we treat the reconstruction problem as a linear inverse problem and establish a flexible iterative framework for practical implementation. It encumbrances a number of efficient iterative correction algorithms and simplifies their design, implementation, and performance analysis. In particular, an efficient Gauss-Seidel iteration is studied in detail to illustrate how the correction problem can be solved iteratively and how the proposed structure can be efficiently implemented using Farrow-based variable digital filters with few general-purpose multipliers. We also study important issues, such as the sufficient convergence condition and reconstructed signal spectrum, derive new lower bound of signal-to-distortion-and-noise ratio in order to ensure stable operation, and predict the performance of the proposed structure. Furthermore, we propose an extended iterative structure, which is able to cope with systems involving more than one type of mismatches. Finally, the theoretical results and the effectiveness of the proposed approach are validated by means of computer simulations.

A Versatile Iterative Framework for the Reconstruction of Bandlimited Signals from Their Nonuniform Samples

In this paper, we study a versatile iterative framework for the reconstruction of uniform samples from nonuniform samples of bandlimited signals. Assuming the input signal is slightly oversampled, we first show that its uniform and nonuniform samples in the frequency band of interest can be expressed as a system of linear equations using fractional delay digital filters. Then we develop an iterative framework, which enables the development and convergence analysis of efficient iterative reconstruction algorithms. In particular, we study the Richardson iteration in detail to illustrate how the reconstruction problem can be solved iteratively, and show that the iterative method can be efficiently implemented using Farrow-based variable digital filters with few general-purpose multipliers. Under the proposed framework, we also present a completed and systematic convergence analysis to determine the convergence conditions. Simulation results show that the iterative method converges more rapidly and closer to the true solution (i.e. the uniform samples) than conventional iterative methods using truncation of sinc series.

ADVANCED SYNTHESIS OF DSP ALGORITHMS IN MODERN PROGRAMMABLE ARCHITECTURES

In this paper, using FIR filters as an example, the discussion on efficiency of different implementation methodologies used in DSP application targeted modern FPGA architectures is presented. Nowadays programmable technology provides possibility to implement digital system with use of specialized embedded DSP blocks. On the first place, however, this technology gives the designer the possibility to increase efficiency of designed system by exploitation of parallelisms of implemented algorithms. Moreover, it is possible to apply special techniques, such as distributed arithmetic (DA). Since in this approach general purpose multipliers are replaced by combinational LUT blocks, it allows constructing digital filters of very high performance. Additionally, application of the functional decomposition based method to LUT blocks optimisation and mapping has been investigated. The paper presents results of comparison of different design approaches.

B06: Advanced synthesis of digital filters based on distributed arithmetic concept for FPGAs

This paper presents the application of distributed arithmetic in implementation of digital filter in FPGA structures. Since in this approach general purpose multipliers are replaced by combinational LUT blocks, it is possible to construct digital filters of very high performance. In this paper an application of the functional decomposition based method to LUT blocks optimisation and mapping has been investigated. This method is recognised as the best synthesis method targeted FPGA architectures, thus it allows significant improvements in digital filters implementation. The paper presents many examples confirming that decomposition allows reduction of logic cell utilisation of filter implementation based on distributed arithmetic concept with no performance degradation and even increasing it.

Highly efficient, limited range multipliers for LUT-based FPGA architectures

A novel design technique for deriving highly efficient multipliers that operate on a limited range of multiplier values is presented. Using the technique, Xilinx Virtex field programmable gate array (FPGA) implementations for a discrete cosine transform and poly-phase filter were derived with area reductions of 31%-70% and speed increases of 5%-35% when compared to designs using general-purpose multipliers. The technique gives superior results over other fixed coefficient methods and is applicable to a range of FPGA technologies.

Low-power constant-coefficient multiplier generator

Constant-coefficient multipliers are used in many DSP cores. A new low-power constant multiplier, with detailed design procedure, is presented. A generator written in C++ is used to generate technology-independent VHDL code of the constant multiplier for different input specifications (signed/unsigned, word length, etc.). Synthesis results indicate the new design features less power and area consumption while offering similar speed performance when compared with other general-purpose multipliers.

Hearing aid digital filter

A digital hearing aid uses a digital filter using coefficient multipliers and with digital signal processing algorithms, which can be implemented with a minimum amount of dedicated circuitry, which may be contained in an integrated circuit. Power consumption in the digital hearing aid is kept to a minimum by the use of a single, general purpose multiplier by eliminating a multiplexed multiplier, and by eliminating a plurality of general purpose multipliers. Preferably, filter coefficients which are limited to powers of 2 are used in the digital filter, whereby coefficient multipliers function as shifters. Shifting-hardware is simpler and more economical compared to a multiplier. Multiplication by powers of 2 is implemented by circuit connections in the hearing aid circuitry, without requiring any power expenditure from the battery. The digital filter may be a non-recursive finite impulse response (FIR) digital filter, or, an infinite impulse response (IIR) digital filter.

The Hall-Effect Analog Multiplier

The application of the Hall effect to a general-purpose four-quadrant multiplier is discussed. Circuit diagrams for the transistor amplifiers are given. An evaluation of the experimental results is given for a breadboard model of the multiplier. Static accuracies on the order of 1 per cent to 3 per cent are obtained for the Hall channel and the magnetic channel, respectively. Bandwidths of 25 kc and 1.3 kc are achieved for the Hall channel and the magnetic channel, respectively.