Low-power constant-coefficient multiplier generator

Abstract

Constant-coefficient multipliers are used in many DSP cores. A new low-power constant multiplier, with detailed design procedure, is presented. A generator written in C++ is used to generate technology-independent VHDL code of the constant multiplier for different input specifications (signed/unsigned, word length, etc.). Synthesis results indicate the new design features less power and area consumption while offering similar speed performance when compared with other general-purpose multipliers.