General-purpose CPU Research Articles

Embedded GPU 3D Panoramic Viewing System Based on Virtual Camera Roaming 3D Environment

The traditional 2D panoramic view has the problem of small imaging range, low utilization of original image and serious stretching of the foreground. This paper designs a 3D panoramic viewing system. The real-time performance of the panoramic system requires a large number of parallel image transformations. The general-purpose processor CPU is incapable. This paper designs an embedded GPU solution. The core computing module is based on NXP's i.MX6Q application processor and builds an embedded Linux system. Using V4L2 to capture images to reduce memory and CPU usage, and use OpenGL ES shaders to process image transformations in parallel at high speed. Because it is in a 3D environment, it is impossible to cover all images through a still viewpoint like a 2D look-around. In order to roam the 3D scene, this paper proposes to design a virtual camera system. Using the virtual camera to roam the 3D environment, realize the virtual viewpoint in the 3D scene, traverse each scene in the grid, eliminate the dead angle of the field of view, and finally realize the 3D panoramic view, and verified on the embedded hardware platform, which can clearly roam every image on the surface. And recorded the video of 3-D looping. Experiments show that the 3D panoramic viewing system proposed in this paper has excellent performance and good effects. It has a good real-time performance on the image display, and the response speed is increased by 5%. The main operation is undertaken by the GPU and only takes a small number of CPU resources. The proposed virtual camera system can better realize the 3D panoramic view.

A Single-Phase Step-Up Seven-Level Inverter With a Simple Implementation Method for Level-Shifted Modulation Schemes

This paper proposed a single-phase seven-level inverter topology with a simple implementation method for level-shifted modulation schemes, which includes two novelty work. One aspect of the work is the proposed inverter topology that integrates a three-time step-up ratio and capacitor voltage self-balance capability. Compared to the existing single-phase seven-level inverters, the proposed inverter reduces the number of power switches and the voltage stresses across them. The other aspect of the work is a new way to implement level-shifted modulation schemes (level-shifted carrier modulation scheme and level-shifted sine modulation scheme) by three basic steps: (1) obtaining modulation logic based on Karnaugh Map technique; (2) determining a level-shifted modulation scheme; and (3) software implementation using the general-purpose input output(GPIO) terminals and CPU timer interruption function of a DSP chip. Therefore, complex trigonometric calculations of the traditional implementation methods for carrier modulation schemes are replaced by simple logic operations of the proposed implementation method, and thus extra logic chips used in the traditional implementation methods are not necessary for the proposed implementation method. Both simulation and experimental results are presented to verify the proposed inverter topology and the proposed implementation method for level-shifted modulation schemes.

Experimental analysis of surface detection methods for two-medium imaging with a linear ultrasonic array

In ultrasonic nondestructive testing, when using an ultrasonic linear array transducer for imaging objects with nonplanar surfaces, a coupling medium must be used. To compensate for the refraction at the coupler-object interface, its shape must be known. Two methods for surface detection of convex objects in immersion are proposed, using the same linear array transducer for surface detection and for SAFT imaging. One is based on imaging technique and the other is based on the time-of-flight of the echoes on the captured ultrasonic signals. The accuracy and performance of the two methods are compared experimentally with an existing fast method called pitch-catch. The proposed methods produced smaller errors in part of the tested configurations, with a slower performance compared with the pitch-catch method. After the surface detection, in the SAFT image formation phase, the delays are calculated through a simple and fast proposed technique to determine the fastest paths, following the Fermat’s principle. Images are formed for nine distinct array element groups, and then combined using the effective aperture technique. The results show that the developed methods allow interactive two-medium image formation on a general-purpose CPU.

Real-Time Refocusing Using an FPGA-Based Standard Plenoptic Camera

Plenoptic cameras are receiving increasing attention in scientific and commercial applications because they capture the entire structure of light in a scene, enabling optical transforms (such as focusing) to be applied computationally after the fact, rather than once and for all at the time a picture is taken. In many settings, real-time interactive performance is also desired, which in turn requires significant computational power due to the large amount of data required to represent a plenoptic image. Although GPUs have been shown to provide acceptable performance for real-time plenoptic rendering, their cost and power requirements make them prohibitive for embedded uses (such as in-camera). On the other hand, the computation to accomplish plenoptic rendering is well-structured, suggesting the use of specialized hardware. Accordingly, this paper presents an array of switch-driven Finite Impulse Response (FIR) filters, implemented with FPGA to accomplish high-throughput spatial-domain rendering. The proposed architecture provides a power-efficient rendering hardware design suitable for full-video applications as required in broadcasting or cinematography. A benchmark assessment of the proposed hardware implementation shows that real-time performance can readily be achieved, with a one order of magnitude performance improvement over a GPU implementation and three orders of magnitude performance improvement over a general-purpose CPU implementation.

Nonlinear predictive control on a heterogeneous computing platform

We propose an implementation of an interior-point-based nonlinear predictive controller on a heterogeneous processor. The workload can be split between a general-purpose CPU and a field-programmable gate array to trade off the contradicting design objectives of control performance and computational resource usage. A new way of exploiting the structure of the KKT matrix yields significant memory savings. We report an 18x memory saving, compared to existing approaches, and a 6x speedup over a software implementation with an ARM Cortex-A9 processor. We also introduce a new release of Protoip, which abstracts low-level details of heterogeneous programming and allows processor-in-the-loop verification.

Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network.

The deep convolutional neural network (DCNN) is a class of machine learning algorithms based on feed-forward artificial neural network and is widely used for image processing applications. Implementation of DCNN in real-world problems needs high computational power and high memory bandwidth, in a power-constrained environment. A general purpose CPU cannot exploit different parallelisms offered by these algorithms and hence is slow and energy inefficient for practical use. We propose a field-programmable gate array (FPGA)-based runtime programmable coprocessor to accelerate feed-forward computation of DCNNs. The coprocessor can be programmed for a new network architecture at runtime without resynthesizing the FPGA hardware. Hence, it acts as a plug-and-use peripheral for the host computer. Caching is implemented for input features and filter weights using on-chip memory to reduce the external memory bandwidth requirement. Data are prefetched at several stages to avoid stalling of computational units and different optimization techniques are used to efficiently reuse the fetched data. Dataflow is dynamically adjusted in runtime for each DCNN layer to achieve consistent computational throughput across a wide range of input feature sizes and filter sizes. The coprocessor is prototyped using Xilinx Virtex-7 XC7VX485T FPGA-based VC707 board and operates at 150 MHz. Experimental results show that our implementation is energy efficient than highly optimized CPU implementation and achieves consistent computational throughput of more than 140 G operations/s for a wide range of input feature sizes and filter sizes. Off-chip memory transactions decrease by due to the use of the on-chip cache.

An Approach to Domain Generic IC with Acceleration of Multi-island GA

ASIC while smaller in size, is expensive to develop and tends to lack the flexibility needed to adapt to diverse application scenarios. In our paper, we proposed the concept of “domain general utility.” We designed a DGIC chip which innovative structure to be equivalent to an application layer language, named as LL7, divided into two parts: the control engine LL7.PI, and the user-defined “domain instruction set,” said as LL7.PS. The control engine LL7.PI is suitable for all application fields. Some IP cores can be encapsulated into the form of components, serving as general instruction set LL7.PS. They can both be deployed to the architecture based on the WoB proposed in this paper, bringing the “domain general utility” DGIC into being. The test results showed its advantages consisted in that the DGIC allows the IC to keep the customizable syntax of an ASIC, while retaining flexible, reconfigurable semantic processes, much like a general-purpose CPU. To demonstrate the power of our solution, we tested a multi-island GA based on Xilinx FPGA V5. The test results showed that its acceleration ratio was 3.43 × 104, which was notably better than the results provided by the combined GPU + CPU approach.

CPU-FPGA Coscheduling for Big Data Applications

FPGA accelerators integrated with general-purpose CPUs have brought opportunities to improve energy efficiency of data center workloads. This article addresses the problem of coordination between FPGAs and multicore CPUs for big data applications.

A programmable ternary CPU using hybrid CMOS/memristor circuits

The carry propagation of arithmetic operations is one of the major shortcomings of common binary number encodings as the two’s complement. Signed-digit arithmetic allows the addition of two numbers without carry propagation and in asymptotically constant time in dependence of the word length, while at the same time requiring a digit representation with more than two states. With the advent of memristors, it has become possible to store multiple states within a single memory cell. This paper proposes an implementation of a general purpose CPU using signed-digit arithmetic by exploiting memristors in order to implement multi-value registers. The proposed model of the CPU is evaluated by the execution of various image processing algorithms. It is shown that a break-even point exists at which signed-digit algorithms outperform conventional binary arithmetic operations. Furthermore, simulation results prove that the memristor device lends itself to store signed-digit data efficiently.

Nonlinear predictive control on a heterogeneous computing platform

Nonlinear Model Predictive Control (NMPC) is an advanced control technique that often relies on computationally demanding optimization and integration algorithms. This paper proposes and investigates a heterogeneous hardware implementation of an NMPC controller based on an interior point algorithm. The proposed implementation provides flexibility of splitting the workload between a general-purpose CPU with a fixed architecture and a field-programmable gate array (FPGA) to trade off contradicting design objectives, namely performance and computational resource usage. A new way of exploiting the structure of the Karush-Kuhn-Tucker (KKT) matrix yields significant memory savings, which is crucial for reconfigurable hardware. For the considered case study, a 10x memory savings compared to existing approaches and a 10x speedup over a software implementation are reported. The proposed implementation can be tested from Matlab using a new release of the Protoip software tool, which is another contribution of the paper. Protoip abstracts many low-level details of heterogeneous hardware programming and allows quick prototyping and processor-in-the-loop verification of heterogeneous hardware implementations.

A Comparative Study of Programming Environments Exploiting Heterogeneous Systems

This paper compares programming environments that exploit heterogeneous systems to process a large amount of data efficiently. Our motivation is to investigate the feasibility of the adaptive, transparent migration of intensive computation for a large amount of data across heterogeneous programming languages and processors for high performance and programmability. We compare a variety of programming environments composed of programming languages, such as Java and C, memory space models, such as distinct and shared memory, and parallel processors, such as general-purpose CPUs and graphics processing units (GPUs) to examine their performance-programmability tradeoffs. In addition, we introduce a software-based shared virtual memory that creates a view of the host memory inside GPU kernels to enable seamless computation offloading from the host to the device. This paper reveals a programmability-performance hierarchy in which programs increase their performance at the cost of decreasing programmability. The experimental results suggest the desirability of a well-balanced system.

The Design of a Portable Control Module Based on TMS320C6748 and FPGA

This paper proposes a portable control module based on TMS320C6748 and FPGA. We take advantage of the rich interface resources of TMS320C6748, including LCD/DDR2/Ethernet/ EMIF/uPP etc. And we also use FPGA plus the PCI bridge chip, UART transceiver and CAN transceiver to realize the system control module. This control module includes interactive module, memory module and communication module. The control module has the characteristics of low power consumption, high reliability and low cost. It can replace the general-purpose CPU board in the field of portable test and meet the resources and performance requirements. So it has great application value.

VirtualSoC

Architectural heterogeneity has proven to be an effective design paradigm to cope with an ever-increasing demand for computational power within tight energy budgets, in virtually every computing domain. Programmable manycore accelerators are currently widely used not only in high-performance computing systems, but also in embedded devices, in which they operate as coprocessors under the control of a general-purpose CPU (the host processor). Clearly, such powerful hardware architectures are paired with sophisticated and complex software ecosystems, composed of operating systems, programming models plus associated runtime engines, and increasingly complex user applications with related libraries. System modeling has always played a key role in early architectural exploration or software development when the real hardware is not available. The necessity of efficiently coping with the huge HW/SW design space provided by the described heterogeneous Systems on Chip (SoCs) calls for advanced full-system simulation methodologies and tools, capable of assessing various metrics for the functional and nonfunctional properties of the target system. In this article, we describe VirtualSoC, a simulation tool targeting the full-system simulation of massively parallel heterogeneous SoCs. We also describe how VirtualSoC has been successfully adopted in several research projects.

Energy efficient parallel neuromorphic architectures with approximate arithmetic on FPGA

In this paper, we present the parallel neuromorphic processor architectures for spiking neural networks on FPGA. The proposed architectures address several critical issues pertaining to efficient parallelization of the update of membrane potentials, on-chip storage of synaptic weights and integration of approximate arithmetic units. The trade-offs between throughput, hardware cost and power overheads for different configurations are thoroughly investigated. Notably, for the application of handwritten digit recognition, a promising training speedup of 13.5x and a recognition speedup of 25.8x are achieved by a parallel implementation whose degree of parallelism is 32. In spite of the 120MHz operating frequency, the 32-way parallel hardware design demonstrates a 59.4x training speedup over the single-thread software program running on a 2.2GHz general purpose CPU. Equally importantly, by leveraging the built-in resilience of the neuromorphic architecture we demonstrate the energy benefit resulted from the use of approximate arithmetic computation. Up to 20% improvement in energy consumption is achieved by integrating approximate multipliers into the system while maintaining almost the same level of recognition rate achieved using standard multipliers. To the best of our knowledge, it is the first time that the approximate computing and parallel processing are applied to FPGA based spiking neural networks. The influence of the parallel processing on the benefits of approximate computing is also discussed in detail.

A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing

In the near future, the ability to solve combinatorial optimization problems will be a key technique to enable the IoT era. A new computing architecture called Ising computing and implemented using CMOS circuits is proposed. This computing maps the problems to an Ising model, a model to express the behavior of magnetic spins, and solves combinatorial optimization problems efficiently exploiting its intrinsic convergence properties. In the computing, “CMOS annealing” is used to find a better solution for the problems. A 20k-spin prototype Ising chip is fabricated in 65 nm process. The Ising chip achieves 100 MHz operation and its capability of solving combinatorial optimization problems using an Ising model is confirmed. The power efficiency of the chip can be estimated to be 1800 times higher than that of a general purpose CPU when running an approximation algorithm.

A neural network accelerator for mobile application processors

Today’s mobile consumer electronics devices, such as smartphones and tablets, are required to execute a wide variety of applications efficiently. To this end modern application processors integrate both general-purpose CPU cores and specialized accelerators. Energy efficiency is the primary design goal for those processors, which has recently rekindled interest in neural network accelerators. Neural network accelerators trade the accuracy of computation for performance and energy efficiency and are suitable for errortolerant media applications such as video and audio processing. However, most existing accelerators only exploit inter-neuron parallelism and leave processing elements underutilized when the number of neurons in a layer is small. Thus, this paper proposes a novel neural network accelerator that can efficiently exploit both inter- and intra-neuron parallelism. For five applications the proposed accelerator achieves average speedups of 126% and 23% over a generalpurpose CPU and a state-of-the-art accelerator exploiting inter-neuron parallelism only, respectively. Besides, the proposed accelerator saves energy consumption by 22% over the state-of-the-art accelerator.

Modular Real-Time Face Detection System

In this paper, a novel system architecture of face detection in possession of modular characteristic is proposed, and the corresponding face detection method is described, to match with the proposed architecture. First of all, the proposed architecture of face detection consists of two modules, namely, the coprocessor module of face detection based on FPGA and target system module, which hopes to implement finial face detection, based on general purpose CPU, and USB bus is used as the communication bridge between the two modules. Secondly, taking the characteristics of FPGA and general purpose CPU into consideration, face detection algorithm can be divided into two layers. The first layer of face detection algorithm based on skin color and eyes’ graylevel variation is implemented in the FPGA, and then the corresponding detection results and image are transmitted to the second module by USB bus so as to further detect face using the algorithm combining principle component analysis with support vector machine, which is referred to as the second layer of algorithm. Because the second layer of the algorithms are operations of float-point and loop, it implemented in the general purpose CPU. This architecture enables face detection to be implemented not only in high performance computing platform in possession of USB bus interface, but also in small terminal products and low-end embedded systems, where the performance of processor and the resource of hardware are limited. Actual testing results show that the proposed system architecture can implement real-time face detection for the images with 640 $$\times $$ 480 resolution, and the detection accuracy is about 89 %.

FPGA-Based Hardware Accelerator for Feature Extraction in Automatic Speech Recognition

We describe in this paper a hardware-based improvement scheme of a real-time automatic speech recognition (ASR) system with respect to speed by designing a parallel feature extraction algorithm on a Field-Programmable Gate Array (FPGA). A computationally intensive block in the algorithm is identified implemented in hardware logic on the FPGA. One such block is mel-frequency cepstrum coefficient (MFCC) algorithm used for feature extraction process. We demonstrate that the FPGA platform may perform efficient feature extraction computation in the speech recognition system as compared to the generalpurpose CPU including the ARM processor. The Xilinx Zynq-7000 System on Chip (SoC) platform is used for the MFCC implementation. From this implementation described in this paper, we confirmed that the FPGA platform is approximately 500× faster than a sequential CPU implementation and 60× faster than a sequential ARM implementation. We thus verified that a parallelized and optimized MFCC architecture on the FPGA platform may significantly improve the execution time of an ASR system, compared to the CPU and ARM platforms.

A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification

This paper presents a parallel digital VLSI architecture for combined support vector machine (SVM) training and classification. For the first time, cascade SVM, a powerful training algorithm, is leveraged to significantly improve the scalability of hardware-based SVM training and develop an efficient parallel VLSI architecture. The presented architecture achieves excellent scalability by spreading the training workload of a given data set over multiple SVM processing units with minimal communication overhead. Hardware-friendly implementation of the cascade algorithm is employed to achieve low hardware overhead and allow for training over data sets of variable size. In the proposed parallel cascade architecture, a multilayer system bus and multiple distributed memories are used to fully exploit parallelism. In addition, the proposed architecture is rather flexible and can be tailored to realize hybrid use of hardware parallel processing and temporal reuse of processing resources, leading to good tradeoffs between throughput, silicon overhead and power dissipation. Several parallel cascade SVM processors have been designed with a commercial 90-nm CMOS technology, which provide up to a $561\times $ training time speedup and a significant estimated $21\,859\times $ energy reduction compared with the software SVM algorithm running on a 45-nm commercial general-purpose CPU.

GPU Acceleration for Simulating Massively Parallel Many-Core Platforms

Emerging massively parallel architectures such as a general-purpose processor plus many-core programmable accelerators are creating an increasing demand for novel methods to perform their architectural simulation. Most state-of-the-art simulation technologies are exceedingly slow and the need to model full system many-core architectures adds further to the complexity issues. This paper presents a fast, scalable and parallel simulator, which uses a novel methodology to accelerate the simulation of a many-core coprocessor using GPU platforms. The main idea is to use. The target architecture of the associated . Simulation of many target nodes is mapped to the many hardware-threads available on highly parallel GPU platforms. This paper presents a novel methodology to accelerate the simulation of many-core coprocessors using GPU platforms. We demonstrate the challenges, feasibility and benefits of our idea to use heterogeneous system (CPU and GPU) to simulate future architecture of many-core heterogeneous platforms. The target architecture selected to evaluate our methodology consists of an ARM general purpose CPU coupled withmany-core coprocessor with thousands of simple in-order cores connected in a tile network. This work presents optimization techniques used to parallelize the simulation specifically for acceleration on GPUs. We partition the full system simulation between CPU and GPU, where the target general purpose CPU is simulated on the host CPU, whereas the many-core coprocessor is simulated on the NVIDIA Tesla 2070 GPU platform. Our experiments show performance of up to 50 MIPS when simulating the entire heterogeneous chip, and high scalability with increasing cores on coprocessor.