Ge Pre-amorphization Implantation Research Articles

Impact of Ge pre-amorphization implantation on Co/Co-Ti/n+-Si contacts in advanced Co interconnects

Co has been proposed as one of the most promising candidates to replace W or Cu in interconnects, where Co–Ti could be used as a single barrier/liner to prevent Co out-diffusion into dielectric and Si substrate as well as to enhance the adhesion property. In this paper, the material and electrical properties of Co/Co-Ti/n+-Si contacts with different compositions and thicknesses of Co–Ti, with and without Ge pre-amorphization implantation (Ge PAI) were investigated elaborately. Sheet resistance, phase formation, interfacial morphology and element distribution were comprehensively characterized in terms of four-point probe, X-ray diffraction and high-resolution transmission electron microscopy in combination with corresponding energy dispersive X-ray spectroscopy respectively. Meanwhile, the specific contact resistivity (ρc) was extracted using refined transmission line model structures, and it is found that Ge PAI is indeed beneficial in reducing ρc values in Co/Co-Ti/n+-Si contacts. With the assistance of Ge PAI, the lowest ρc value of 8.56 × 10−9 Ω cm2 is accomplished for Co/Co0.65Ti0.35/n+-Si contacts, which is a ∼47.8% reduction in contrast to that without Ge PAI.

Impacts of Ge Preamorphization Implantation and Si Capping on the Specific Contact Resistivity of Ni(Pt)SiGe/p+-SiGe Contacts

This article explores the impacts of both Ge preamorphization implantation (PAI) and Si capping on the specific contact resistivity ( $\rho _{c}$ ) of Ni(Pt)SiGe/p+-SiGe contacts elaborately. Both Ge PAI and Si capping are found to be beneficial in reducing the $\rho _{c}$ of Ni(Pt)SiGe/p+-SiGe contacts remarkably, with $\rho _{c}$ values reduced from the original ${20.03} \times {10}^{-{8}} \Omega $ -cm2 to ${9.92} \times {10}^{-{8}}\,\,\Omega $ -cm2 with Ge PAI and ${1.44} \times {10}^{-{8}} \Omega $ -cm2 with Si capping, respectively. Improved interfacial uniformity and morphology are thought to be primarily responsible for such significant reductions in $\rho _{c}$ since neither Ge PAI nor Si capping induces an obvious difference in B concentrations at the interface of Ni(Pt)SiGe/p+-SiGe. Moreover, by combining Ge PAI or Si capping with extra B implantation before germanosilicidation to intentionally introduce B dopant segregation (DS) at the interface of Ni(Pt)SiGe/p+-SiGe contacts, further reduction of $\rho _{c}$ values is accomplished as anticipated.

Exploration of the impact of interface states density on the specific contact resistivity in TiSix/n+-Si Ohmic contacts through high-low frequency method

In our previous work, a reduction of specific contact resistivity (ρc) in TiSix/n+-Si Ohmic contacts by ∼21% has been achieved with proper Ge Pre-amorphization Implantation (PAI). In this work, the mechanism behind such an improvement using Ge PAI is explored experimentally. Versatile characterizations including current–voltage (I–V), capacitance–voltage (C–V) measurements and cross-sectional transmission electron microscopy (XTEM) are performed and analyzed. High-low frequency method is used to extract the responsive interface states density (Dit) of TiSix/n-Si Schottky diodes with and without Ge PAI. It is demonstrated that in TiSix/n+-Si Ohmic contacts, the ρc reduction by ∼21% with Ge PAI should be ascribed to the reduction of Dit at TiSix/n-Si interface. From the distribution of Dit, it can be inferred that a part of shallow level defects can be annihilated after annealing for TiSix/n-Si with Ge PAI, but deep level traps still exist. A further discussion about the relationship between Dit and ρc is tentatively provided.

Improved Ti germanosilicidation by Ge pre-amorphization implantation (PAI) for advanced contact technologies

In this work, a fundamental material's study of the formation of ultrathin TiSixGey film on highly B-doped SiGe substrates with different Ge pre-amorphization implantation (PAI) conditions is presented, for its future application in Ti/p+-SiGe Ohmic contacts. The sheet resistance (Rsh), phase identity, morphology, as well as the elemental distribution for resulting TiN/Ti/TiSixGey stacking films were characterized using four-point probe measurements, X-ray diffraction (XRD), cross-sectional scanning transmission electron microscopy (STEM) in conjunction with electron energy loss spectroscopy (EELS), and Secondary Ion Mass Spectrometry (SIMS). It is found that Ti germanosilicidation process is significantly promoted by Ge PAI in employed temperature span of 400–600 °C. Across as-formed ultrathin TiSixGey films, the composition is not constant but graded from Ti-rich at Ti/TiN side to Si-rich at SiGe substrate side. The inhomogeneous interfacial layer consisting of crystallites with obvious lattice texture at TiSixGey/p+-SiGe interface is much thicker for the sample with Ge PAI than for the reference without Ge PAI. The percentage contents of Si and Ge in as-formed TiSixGey film with Ge PAI are much higher and lower than those without Ge PAI respectively. With Ge PAI, out-diffusion of B atoms towards TiSixGey films is more aggravated compared to the reference without Ge PAI.

Impact of Ge Preamorphization Implantation on Both the Formation of Ultrathin TiSi<italic>x</italic> and the Specific Contact Resistivity in TiSi<italic>x</italic>/n-Si Contacts

In this paper, the impact of different Ge preamorphization implantation (PAI) conditions on the formation of ultrathin TiSi x as well as on the specific contact resistivity ( $\rho _{c}$ ) in TiSi x /n-Si contacts was investigated systematically. Extensive material characterizations, such as cross-sectional transmission electron microscopy, X-ray diffraction, and angle-resolved X-ray photoelectron spectroscopy, as well as electrical characterizations such $\rho _{c}$ values, Schottky barrier height (SBH), and leakage current of p-n junctions, were performed. It is found that Ge PAI indeed promotes Ti silicidation at 550 °C and the resultant ${t}_{\text {TiSix}}$ values are strongly dependent on the thickness of amorphous Si ( ${t}_{\boldsymbol {\alpha -{\mathrm{ Si}}}}$ ) created by Ge PAI. The stoichiometry of TiSi x films is rather graded than constant from the TiN/Ti side to Si side. Proper Ge PAI is beneficial in reducing the $\rho _{c}$ values in TiSi x /n-Si contacts, and this reduction in $\rho _{c}$ cannot attribute to the reduction of SBH. Though proper Ge PAI leads to reduced $\rho _{c}$ values, the leakage current of p-n diodes is increased as a penalty which needs to be compromised in practical applications.

Impact of Ge pre-amorphization implantation on forming ultrathin TiGex on both n- and p-Ge substrate

In this work, the effects of Ge pre-amorphization implantation (PAI) on forming ultrathin TiGex films at 350–600 °C are explored. It is found that the Ge PAI indeed enhances the formation of TiGex at relatively low temperature, as confirmed by the lower sheet resistance and thicker TiGex films compared to the case without Ge PAI. The energy dispersive X-ray spectroscopy (EDX) reveals that the composition of as-formed TiGex across its thickness is rather graded than constant. Characterizations using advanced autocorrelation function (ACF) in transmission electron microscopy (TEM) demonstrate that numerous Ti6Ge5 and Ti5Ge3 nanocrystals are embedded in as-formed amorphous TiGex film.

Improved leakage current and device uniformity for sub-20 nm N-FinFETs by cryogenic Ge pre-amorphization implant in contact

Prior to contact silicide formation, cryogenic Ge pre-amorphization implantation (PAI) was adopted in sub-20nm FinFETs to investigate how device characteristics can be affected. As compared to room-temperature PAI, cryogenic PAI does not enhance drive current from the viewpoint of mean value, however, it significantly improves variation in device parameters such as sub-Vt swing (SS), drain induced barrier lowering (DIBL) and total series resistance (RTotal) for N-FinFETs by 22%–34% which is due to a reduced number of end of range (EOR) defects caused by Ge PAI. However, the benefit is not observed for P-FinFETs since its source/drain is composed of SiGe which is intrinsically less prone to form EOR defects. In addition, cryogenic PAI also contributes to leakage current reduction for N-FinFETs including gate induced drain leakage (GIDL) by 67%, sub-Vt leakage by 50% and junction leakage by 67% which is primarily due to a lower number of EOR defects that make fewer native point defects. The mechanism for pronounced GIDL reduction for I/O devices than core devices is also proposed. Besides the improved device uniformity as well as leakage current, the process can be fully integrated into incumbent VLSI technology and holds great potential for sub-10nm node.

Improved Current Drivability for Sub-20-nm N-FinFETs by Ge Pre-Amorphization in Contact With Reverse Retrograde Profile

Prior to contact silicide formation, multiple Ge pre-amorphization implantation (PAI) with reverse retrograde Ge profile was investigated for sub-20-nm FinFETs. Compared with conventional single PAI, N-FinFETs from the new PAI scheme exhibit enhanced drive current by 12%, which can be attributed to decreased total series resistance ( ${\mathrm {R}}_{\mathrm {{{Total}}}}$ ) by 15% and enhanced peak electron mobility by 8%. The former arises from reduced Schottky barrier height and better crystallinity of C49/C54 TiSi2, while the latter is resulted from higher tensile strain in the channel induced by TiSi2 with more Ge incorporation. Furthermore, ring oscillator for the new PAI scheme shows better circuit performance as compared with conventional scheme in terms of 6% increase in output frequency. The newly developed PAI process is fully compatible with the incumbent ULSI technology and can be extended to sub-10-nm FinFETs.

On the Manifestation of Ge Pre-Amorphization Implantation (PAI) in Forming Ultrathin TiSix for Ti Direct Contact on Si in Sub-16/14 nm Complementary Metal-Oxide-Semiconductor (CMOS) Technology Nodes

From the 22 nm 3D FinFET technology node, the Ti silicide-last contact scheme based on ultrathin TiSix (0 < x< 2) has replaced the Ni(Pt)Si employed widely in previous planar CMOS nodes, due to its inherent advantages. Most work on Ti direct contacting with Si focuses on improving the specific contact resistivity (ρc) by all means. The detailed investigation on the formation of ultrathin TiSix at relatively low temperature (≤600°C), is, however, rarely reported. In this work, a fundamental material’ study of the formation of ultrathin TiSix on highly P-doped Si substrates with different Ge pre-amorphization implantation (PAI) conditions is described, for the future application in Ti direct contact scheme on n-Si. The sheet resistance (Rsh), phase identity, morphology, as well as the elemental distribution for the resulting TiN/Ti/TiSix stacking films were characterized using four-point probe measurements, X-ray diffraction (XRD), Secondary Ion Mass Spectrometry (SIMS), cross-sectional transmission electron microscopy (XTEM) in conjunction with energy-dispersive X-ray spectroscopy (EDX), and Nano-Beam-Diffraction (NBD). It is found that Ge PAI can significantly promote the Ti silicidation at relatively low temperature, which is also consistent with previous publications. The optimal temperature for Ti silicidation is ∼550°C, at which amorphous Si (α-Si) caused by Ge PAI is crystallized by Solid Phase Epitaxial Regrowth (SPER), while the silicidation process is also adequate. Across as-formed TiSix films, the composition is not constant and altered from Ti-rich at the metal side to Si-rich at the Si substrate side. Furthermore, the as-formed ultrathin TiSix film is proposed to be not completely amorphous, instead it is a mixture of amorphous TiSix embedded with numerous fine grains at the early growth stage.

Study of Hetero-Tunneling Gfet with an Ultra-Shallow Pocket Junction

Because the subthreshold swing (SS) of a MOSFET is larger than 60mV/dec at room temperature, its threshold voltage cannot be very small. This limits the scaling of power supply voltage (VDD) and the reduction of power density. Tunnel field effect transistor (TFET) can overcome this fundamental limitation, which mechanism is based in the band-to-band tunneling (BTBT). However, the drive current in TFETs is significantly lower than in MOSFETs owing to tunneling resistance which arises due to carrier tunneling. Achieving large drive current at low VDDhas been a great challenge. Green transistor (gFET) is a novel structure TFET with a heavily doped pocket in the gate-source overlap region. The pocket junction can provide large and uniform field over a substantial area, which can offer larger drive current and steeper subthreshold swing as compared to conventional tunneling transistors. And, when the pocket junction depth becomes shallower, the drive current will be improved significantly. But study reveal that gFET is only suitable for orepation at 0.5V. To further reduce Vdd, even smaller bandgap material may be employed.In this study, a hetero-tunneling gFET with an ultra-shallow pocket junction has been developed, as shown in Fig.1. The gFET was fabricated in a 8inch (100) silicon (Si) substrate, as shown in Fig.2. After LOCOS formation, silicon-germanium (Si1-xGex) and Si cap layer were grown on Si substrate using selective epitaxy. After source implantation, an ultra-shallower pocket is formed by using of the Ge preamorphization implantation (PAI), ultra low energy implantation and spike annealing. Si1-xGex and Si have different lattice constant. Biaxially strained will be formed in the Si1-xGex/Si heterostructures. The biaxial strain will shift the conduction and valance band energy levels of semiconductors and obtain ultra low effective tunneling bandgaps, which is helpful to get smaller tunneling length and barrier height. The same current can be obtained at lower gate voltage and drain voltage. The hetero-tunneling gFET integrated with the ultra-shallow pocket junction exhibits good electrical characteristics, such as smaller subthreshold swing, higher Ion/Ioff ratio and so on.

Study of Si Green Transistor with an Ultra-Shallow Pocket Junction

Achieving large on-state current at low power supply voltage is one great challenge for tunneling transistors (TFETs). In this paper, an N-type Green transistor (gFET) with an ultra-shallow pocket junction has been fabricated. The main feature of the device is that the pocket junction was formed by germanium (Ge) preamorphization implantation (PAI) plus arsenic (As) ultra-low energy implantation combined with spike annealing. The Ge PAI can form a Si1-xGex/Si heterojunction in the N+ pocket region. Combined with a heavily doped N+ pocket, it can realize an abrupt tunnel junction between N+ pocket and P+ source, which is helpful to increase the tunneling probability and get higher on-state current. The fabricated gFET exhibits good electrical characteristics. The device’s on-state current is up to 215µA/µm (@VDS=VGS=2V).

Reliability study of methods to suppress boron transient enhanced diffusion in high-k/metal gate Si/SiGe channel pMOSFETs

The effects of extension profile engineering to suppress boron transient enhanced diffusion (TED) are investigated in Si/SiGe channel metal–oxide–semiconductor field-effect transistor (MOSFET). In performance, Ge pre-amorphization implantation (PAI) samples exhibit low drain-induced barrier lowering (DIBL) and a good Ion/Ioff ratio due to suppressed boron diffusion. In reliability, negative bias temperature instability (NBTI) degradation is reduced in Si/SiGe channel pMOSFETs, but hot carrier injection (HCI) degradation is worsened, especially in Ge PAI samples. The results suggest that HCI is an important factor in limiting device life time in Si/SiGe channel pMOSFETs.

Formation of Ultra Shallow p+/n Junction in Silicon Using a Combination of Low-Temperature Solid Phase Epitaxy and Non-Melt Double-Pulsed Green Laser Annealing

MOSFETs scaling-down is an effective way to attain high-performance CMOS operating with lower power and leakage current. However, short channel effects have become a serious problem due to the shortening of channel length. One of the promising methods to suppress this problem is by forming a shallow, highly doped and activated source/drain extension region. Fabricating ultra shallow p+/n junction is difficult due to the channeling of boron ions and anomalous boron diffusion during fabrication processes. A combination of Ge pre-amorphization implantation, low-energy boron implantation and two-step annealing, involving low-temperature solid phase epitaxy preannealing followed by non-melt laser annealing was used for forming ultra shallow p+/n junction in silicon. The physical relationship among the regrowth of implanted layer, boron activation and diffusion, and leakage current is investigated. We have succeeded in forming ultra shallow p+/n junction with junction depth of 8 nm and sheet resistance of 920 Ω/□.

Comparison of Boron Diffusion in Silicon during the Formation of Shallow p+/n Junction with KrF and Green Laser Annealing

A combination of Ge pre-amorphization implantation (Ge-PAI), low-energy B implantation and non-melt laser annealing is a promising method to form highly-activated, abrupt and ultra-shallow junctions (USJ). In this work, shallow p+/n junction was formed by annealing the implanted sample with two different laser sources, i.e. by using excimer laser, KrF (λ= 248nm, pulse duration : 37ns) and green laser (λ= 527nm, pulse duration : 110ns) in order to compare the diffusion of boron during the formation of shallow p+/n junction. Experimental results show that remarkable boron diffusion occurred during annealing of the samples subjected to KrF laser annealing with a very short annealing time. Meanwhile, boron diffusion is controlled in the samples subjected to green laser annealing. We considered that the penetration depth and the pulse duration are the important factor that may caused the difference in boron diffusion during annealing process.

Boron Diffusion Behavior During the Formation of Shallow p+/n Junction Using the Combination of Ge Pre-amorphization Implantation, Pre-Annealing RTA and Post-Annealing Non-Melt Excimer Laser(NLA) Processes

In this paper, we studied the behavior of boron diffusion during the formation of shallow p+/n junction. The combination of Ge-PAI with low-energy boron implantation, pre-annealing RTA and post annealing NLA processes lead to the ultra-fast-diffusion of boron which increase the junction depth of the annealed samples.

Boron Diffusion Behavior during the Formation of Shallow p+/n Junction using the combination of Ge Pre-amorphization Implantation, Pre-Annealing RTA and Post-Annealing Non Melt Excimer Laser(NLA) Processes

not Available.

Laser activation of Ultra Shallow Junctions (USJ) doped by Plasma Immersion Ion Implantation (PIII)

Today, the main challenges for the realization of the source/drain extensions concern the ultra-low energy implantation and the activation of the maximum amount of dopants with a minimized diffusion. Among the different annealing processes, one solution is the laser thermal annealing. Many studies [F. Torregrosa, C. Laviron, F. Milesi, M. Hernandez, H. Faik, J. Venturini, Proc. 14th International Conference on Ion Implant Technology, 2004; M. Hernandez, J. Venturini, D. Zahorski, J. Boulmer, D. Débarre, G. Kerrien, T. Sarnet, C. Laviron, M.N Semeria, D. Camel, J.L Santailler, Appl. Surf. Sci. 208–209 (2003) 345–351] have shown that the association of Plasma Immersion Ion Implantation (PIII) and Laser Thermal Process (LTP) allows to obtain junctions of a few nanometers with a high electrical activation. All the wafers studied have been implanted by PULSION ® (PIII implanter developed by Ion Beam Services) with an acceleration voltage of 1 kV and a dose of 6 × 10 15 at./cm 2. In this paper, we compare the annealing process achieved with three excimer lasers: ArF, KrF and XeCl with a wavelength of respectively 193, 248 and 308 nm. We analyse the results in terms of boron activation and junction depth. To complete this study, we have observed the effect of pre-amorphization implantation (PAI) before PIII process on boron implantation and boron activation. We show that Ge PAI implanted by classical beam line allows a decrease of the junction depth from 20 down to 12 nm in the as-implanted condition. Transmission Electron Microscopy (TEM) analyses were performed in order to study the structure of pre-amorphized silicon and to estimate the thickness of the amorphous layer. In order to determine the sheet resistance ( R s ) and the junction depth ( X j ), we have used the four-point probe technique (4PP) and secondary ion mass spectrometry (SIMS) analysis. To complete the electrical characterizations some samples have been analyzed by non-contact optical measurements. All the results are presented as a function of the laser fluence and the laser wavelength.

Finite-element study of strain field in strained-Si MOSFET

The strain field in the channel of a p-type metal-oxide-semiconductor field effect transistor fabricated by integrating Ge pre-amorphization implantation for source/drain regions is evaluated using a finite-element method combining with large angle convergent-beam electron diffraction (LACBED). The finite-element calculation shows that there is a very large compressive strain in the top layer of the channel region caused by a low dose of Ge ion implantation in the source and drain extension regions. Moreover, a transition region is formed in the bottom of the channel region and the top of the Si substrate. These calculation results are in good agreement with the LACBED experiments.

Study of strained-silicon channel metal–oxide–semiconductor field effect transistors by large angle convergent-beam electron diffraction

Strained-silicon p-type metal–oxide–semiconductor field effect transistors (pMOSFETs) have been investigated by large angle convergent-beam electron diffraction (LACBED). Longitudinal compressive strain is induced into the channel region of a p-type strained-silicon channel metal–oxide–semiconductor field effect transistor by a low-cost Ge pre-amorphization implantation for source/drain extension flow. Anomalously large longitudinal compressive strain, up to 2.5×10 −2, in the nanometer scale channel region of pMOSFETs has been measured using LACBED. We propose a novel scaling effect for the giant strain enhancement. Our experimental results and model analysis together reveal that the channel strain is inversely proportional to the shrinking channel length.

Low-Cost and Highly Manufacturable Strained-Si Channel Technique for Strong Hole Mobility Enhancement on 35-nm Gate Length pMOSFETs

Local strained-silicon channel pMOSFETs with minimum gate length down to 22 nm have been fabricated by integrating Ge preamorphization implantation (PAI) for source/drain (S/D) extension, which induces a uniaxial compressive stress in the channel to attain an enhanced pMOSFET performance without additional masks. A 43 % improvement of hole effective mobility has been obtained for 35-nm gate length pMOSFETs with an optimized Ge PAI condition for S/D extension at 1.1-MV cm vertical effective field, and the hole mobility improvement is nearly maintained at higher vertical field. The corresponding enhancement of a saturated drive current is 25 % at 1.3-MV ldr cm vertical field. The scaling strengthens the enhancement of the hole mobility remarkably. No negative effect on electron effective mobility is observed. An analysis by using a zero-order Laue zone diffraction on large angle convergent beam electron diffraction patterns in a transmission electron microscopy confirms that the significant residual compressive strain up to -3.0 % in the channel region is induced for 60-nm gate length strained channel pMOSFETs with the same optimized Ge PAI condition as that of 35-nm gate length pMOSFETs. The depth profiles of the residual compressive strain and shear strain in the channel region are given, respectively. The possible mechanisms are discussed.