Low-Cost and Highly Manufacturable Strained-Si Channel Technique for Strong Hole Mobility Enhancement on 35-nm Gate Length pMOSFETs

Abstract

Local strained-silicon channel pMOSFETs with minimum gate length down to 22 nm have been fabricated by integrating Ge preamorphization implantation (PAI) for source/drain (S/D) extension, which induces a uniaxial compressive stress in the channel to attain an enhanced pMOSFET performance without additional masks. A 43 % improvement of hole effective mobility has been obtained for 35-nm gate length pMOSFETs with an optimized Ge PAI condition for S/D extension at 1.1-MV cm vertical effective field, and the hole mobility improvement is nearly maintained at higher vertical field. The corresponding enhancement of a saturated drive current is 25 % at 1.3-MV ldr cm vertical field. The scaling strengthens the enhancement of the hole mobility remarkably. No negative effect on electron effective mobility is observed. An analysis by using a zero-order Laue zone diffraction on large angle convergent beam electron diffraction patterns in a transmission electron microscopy confirms that the significant residual compressive strain up to -3.0 % in the channel region is induced for 60-nm gate length strained channel pMOSFETs with the same optimized Ge PAI condition as that of 35-nm gate length pMOSFETs. The depth profiles of the residual compressive strain and shear strain in the channel region are given, respectively. The possible mechanisms are discussed.