Ge Metal Oxide Semiconductor Research Articles

Electrical properties of Ge metal–oxide–semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti**Project supported by the National Natural Science Foundation of China (No. 61274112), the Natural Science Foundation of Hubei Province (No. 2011CDB165), and the Scientific Research Program of Huanggang Normal University (No. 2012028803).

LaON, LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La2O3 using the sputtering method to fabricate Ge MOS capacitors, and the electrical properties of the devices are carefully examined. LaON/Ge capacitors exhibit the best interface quality, gate leakage property and device reliability, but a smaller k value (14.9). LaTiO/Ge capacitors exhibit a higher k value (22.7), but a deteriorated interface quality, gate leakage property and device reliability. LaTiON/Ge capacitors exhibit the highest k value (24.6), and a relatively better interface quality (3.1 × 1011 eV−1 cm−2), gate leakage property (3.6 × 10−3 A/cm2 at Vg = 1 V + Vfb) and device reliability. Therefore, LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials.

Improved interfacial and electrical properties of Ge MOS devices with ZrON/GeON dual passivation layer**Project supported by the National Natural Science Foundation of China (Nos. 6127411261176100, 61404055).

The interfacial and electrical characteristics of Ge metal–oxide–semiconductor (MOS) devices with a dual passivation layer of ZrON/GeON formed by NH3- or N2-plasma treatment are investigated. The experimental results show that the NH3-plasma treated sample exhibits significantly improved interfacial and electrical properties as compared to the samples with N2-plasma treatment and no treatment: a lower interface-state density at the midgap (1.64 × 1011 cm−2 · eV−1) and gate leakage current (9.32 × 10−5 A/cm2 at Vfb + 1 V), a small capacitance equivalent thickness (1.11 nm) and a high k value (32). X-ray photoelectron spectroscopy is used to analyze the involved mechanisms. It is indicated that more GeON and less GeOx (x < 2) are formed on the Ge surface during NH3-plasma treatment than the N2-plasma treatment, resulting in a high-quality high-k/Ge interface, because H atoms and NH radicals in NH3-plasma can enhance volatilization of the unstable low-k GeOx, creating high-quality GeON passivation layer. Moreover, more nitrogen incorporation in ZrON/GeON induced by NH3-plasma treatment can build a stronger N barrier and thus more effectively inhibit in-diffusion of O and Ti from high-k gate dielectric and out-diffusion of Ge.

Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors

We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/SiO2/SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe nano-patterned pillar over a Si3N4 buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5−90 nm), the SiO2 thickness (3−4 nm), and as well the SiGe-shell thickness (2−15 nm) has been demonstrated, enabling a practically-achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO2/Ge-dot and SiO2/SiGe interfaces were assessed using transmission electron microscopy, energy dispersive x-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO2/SiGe and Al/SiO2/Ge-dot/SiO2/SiGe MOS capacitors exhibit low interface trap densities of as low as 3-5x10^11 cm^-2·eV^-1 and fixed charge densities of 1-5x10^11 cm^-2, suggesting good-quality SiO2/SiGe-shell and SiO2/Ge-dot interfaces. In addition, the advantage of having single-crystalline Si1-xGex shell (x > 0.5) in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge) MOS nanoelectronic and nanophotonic applications.

Electrical properties of LaTiO high-k gate dielectric Ge MOS Capacitor and Ti content optimization

Ti is intentionally added into La2O3 to prepare LaTiO gate dielectric Ge metal-oxide-semiconductor (MOS) capacitor with both high k value and good interface quality. In order to examine the effects of Ti content on the electrical properties of the device, LaTiO films with different Ti/La2O3 ratios (10.6%, 18.4%, 25.7% and 31.5%) are deposited by reactively co-sputtering Ti and La2O3 targets. Capacitance-voltage curves, gate-leakage current properties and high-field stress characteristics of the devices are measured and analyzed. It is found that some electrical properties, such as interface-sate density, gate-leakage current, device reliability and k value, strongly depend on Ti content incorporated into La2O3. Ti incorporation can significantly increase the k value: the higher the Ti content, the larger the k value is. The relevant mechanism lies in the fact that higher Ti content leads to an increase of Ti-based oxide in the LaTi-based oxide, because Ti-based oxide has larger k value than La-based oxide. On the contrary, interface quality, gate-leakage current and device reliability deteriorate as Ti content increases because Ti-induced defects at and near the interface increase with Ti content increasing. Of the Ti/La2O3 ratios in the examined range, the largest Ti/La2O3 ratio is 31.5%, which results in the highest k value of 29.4, the largest gate-leakage current of 9.710-2 Acm-2 at Vg=1 V, the highest interface-sate density of 4.51012 eV-1cm-2 and the worst device reliability, while the La2O3 film without Ti incorporation exhibits the lowest k value of 11.7, the smallest gate-leakage current of 2.510-3 Acm-2 at Vg=1 V, the lowest interface-sate density of 3.31011 eV-1cm-2 and the best device reliability. As far as the trade-off among the electrical properties is concerned, 18.4% is the most suitable Ti/La2O3 ratio, which leads to a higher k value of 22.7, lower interface-sate density of 5.51011 eV-1cm-2, an acceptable gate-leakage current of 7.110-3 Acm-2 at Vg=1 V, and a better device reliability. In view of the fact mentioned above, excellent electrical properties could be obtained by setting Ti content to be an optimal value. Therefore, the optimization of Ti content is critical for LaTi-based oxide Ge MOS device preparation.

Heteroepitaxial Ge MOS Devices on Si Using Composite AlAs/GaAs Buffer

Structural and electrical characteristics of epitaxial germanium (Ge) heterogeneously integrated on silicon (Si) via a composite, large bandgap AlAs/GaAs buffer are investigated. Electrical characteristics of N-type metal-oxide-semiconductor (MOS) capacitors, fabricated from the aforementioned material stack are then presented. Simulated and experimental X-ray rocking curves show distinct Ge, AlAs, and GaAs epilayer peaks. Moreover, secondary ion mass spectrometry, energy dispersive X-ray spectroscopy (EDS) profile, and EDS line profile suggest limited interdiffusion of the underlying buffer into the Ge layer, which is further indicative of the successful growth of device-quality epitaxial Ge layer. The Ge MOS capacitor devices demonstrated low frequency dispersion of 1.80% per decade, low frequency-dependent flat-band voltage, $V_{FB}$ , shift of 153 mV, efficient Fermi level movement, and limited C-V stretch out. Low interface state density $(D_{it} )$ from $8.55 \times 10^{11} $ to $1.09 \times 10^{12}~ {\rm cm}^{-2} ~{\rm eV}^{-1} $ is indicative of a high-quality oxide/Ge heterointerface, an effective electrical passivation of the Ge surface, and a Ge epitaxy with minimal defects. These superior electrical and material characteristics suggest the feasibility of utilizing large bandgap III-V buffers in the heterointegration of high-mobility channel materials on Si for future high-speed complementary metal-oxide semiconductor logic applications.

Quantitative evaluation of slow traps near Ge MOS interfaces by using time response of MOS capacitance

Time-dependent changes in current and threshold voltage due to slow traps near Ge metal–oxide–semiconductor (MOS) interfaces is one of the most serious problems in Ge metal–oxide–semiconductor field-effect transistors (MOSFETs). In this study, we propose a new evaluation method of slow traps near MOS interfaces utilizing the time response of capacitance in MOS capacitors at a constant gate voltage, allowing us to evaluate the density and time constant of slow traps. We apply this method to Au/Al2O3/GeOx/Ge MOS capacitors and evaluate the density and average time constant of slow traps. The slow trap density of n-Ge MOS capacitors is found to be much larger than that of p-Ge MOS capacitors, indicating that a higher density of slow traps exists near the conduction band edge. We also examine the effects of post deposition annealing in a variety of ambient gases, including several hydrogen-based species, on the properties of slow traps.

Research progress of high mobility germanium based metal oxide semiconductor devices

Germanium based metal oxide semiconductor (MOS) device has been a research hotspot and considered as a potential candidate for future complementary MOS (CMOS) technology due to its high and symmetric carrier mobility. However, the poor quality of gate dielectric/channel interface significantly restricts the performances of germanium based MOS devices. Besides, the solid-solubility and activation concentration of dopants in Ge are both quite low, and the dopants diffuse fast in Ge, which makes it difficult to achieve ultra-shallow junction with high dopant concentration, especially for Ge NMOS devices.To solve these problems, different techniques are proposed and overviewed. The proposed nitrogen-plasma-passivation method can effectively suppress the regrowth of germanium sub-oxide and reduce the interface state density. Thus the performance of the fabricated Ge NMOS device is significantly improved. To enhance the n-type dopant activation in Ge, the multiple implantation technique and the multiple annealing technique are proposed. High electrical activation over 1 1020 cm-3 is achieved, and the corresponding contact resistivity is reduced to 3.8 10-7 cm2. Besides, the implantation after germanide (IAG) technique is first proposed to modulate the Schottky barrier height (SBH). The record-low electron SBH of 0.10 eV is obtained by IAG technique, and the optimized process window is given. In addition, the poor thermal stability of NiGe restricts the further improvement in performance of Ge MOS device. P and Sb co-implantation technique and novel ammonium fluoride pretreatment method are proposed to improve the thermal stability of NiGe. The electrical characteristic of NiGe/Ge diode is also improved simultaneously. The results provide the guidelines for further enhancing the performances of germanium-based MOS devices.

Improved Interfacial and Electrical Properties of Ge-Based Metal-Oxide-Semiconductor Capacitor With LaTaON Passivation Layer

The interfacial and electrical properties of Ge-based metal–oxide–semiconductor (MOS) capacitor with high- \(k\) gate dielectric of HfTiO and passivation interlayer of LaTaON are investigated. Experimental results show the Ge MOS with HfTiO/LaTaON gate-stacked dielectric exhibits low interface-state density ( \(7.8\times 10^{11}\) cm \(^{-2}\) eV \(^{\mathrm {-1}}\) ), small gate-leakage current ( \(7.88\times 10^{\mathrm {-4}}\) A cm \(^{\mathrm {-2}}\) at \(V_{\rm g} - V_{\rm fb}= 1\) V), small capacitance equivalent thickness (1.1 nm), and large equivalent dielectric constant (27.7). X-ray photoelectron spectroscopy and transmission electron microscopy reveal that the improvements should be due to the fact that La/Ta-based oxide/oxynitride has excellent interface properties with Ge, and the LaTaON interlayer can effectively block the in-diffusion of oxygen and the out-diffusion of germanium, thus suppressing the growth of low- \(k\) GeOx and intermixing between Ge and Hf.

Improving the Electrical Properties of Lanthanum Silicate Films on Ge Metal Oxide Semiconductor Capacitors by Adopting Interfacial Barrier and Capping Layers

The electrical properties of La-silicate films grown by atomic layer deposition (ALD) on Ge substrates with different film configurations, such as various Si concentrations, Al2O3 interfacial passivation layers, and SiO2 capping layers, were examined. La-silicate thin films were deposited using alternating injections of the La[N{Si(CH3)3}2]3 precursor with O3 as the La and O precursors, respectively, at a substrate temperature of 310 °C. The Si concentration in the La-silicate films was further controlled by adding ALD cycles of SiO2. For comparison, La2O3 films were also grown using [La((i)PrCp)3] and O3 as the La precursor and oxygen source, respectively, at the identical substrate temperature. The capacitance-voltage (C-V) hysteresis decreased with an increasing Si concentration in the La-silicate films, although the films showed a slight increase in the capacitance equivalent oxide thickness. The adoption of Al2O3 at the interface as a passivation layer resulted in lower C-V hysteresis and a low leakage current density. The C-V hysteresis voltages of the La-silicate films with Al2O3 passivation and SiO2 capping layers was significantly decreased to ∼0.1 V, whereas the single layer La-silicate film showed a hysteresis voltage as large as ∼1.0 V.

Ge metal oxide semiconductor field effect transistors with optimized Si cap and HfSiO2 high-k metal gate stacks

High mobility metal-oxide-semiconductor-field-effect-transistors (MOSFETs) are demonstrated on high quality epitaxial Si0.75Ge0.25 films selectively grown on Si (100) substrates. With a Si cap processed on Si0.75Ge0.25 channels, HfSiO2 high-k gate dielectrics exhibited low C–V hysteresis (<10 mV), interface trap density (7.5 × 1010), and gate leakage current (∼10−2A/cm2 at an EOT of 13.4 Å), which are comparable to gate stack on Si channels. The mobility enhancement afforded intrinsically by the Si0.75Ge0.25 channel (60%) is further increased by a Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. The Si cap process also mitigates the low potential barrier issues of Si0.75Ge0.25 channels, which are major causes of the high off-state current of small band gap energy Si0.75Ge0.25 pMOSFETs, by improving gate control over the channel.

Crystalline ZrTiO$_{\bf 4}$-Gated Ge Metal–Oxide–Semiconductor Devices With Amorphous Yb$_{\bf 2}$O$_{\bf 3}$ as a Passivation Layer

An amorphous Yb2O3 passivation layer integrated with a crystalline ZrTiO4 film was explored as the advanced gate stack for Ge MOS devices. The ZrTiO4/Yb2O3 gate stack demonstrates Dit of 2.4 × 1011 cm-2· eV-1 and EOT down to 0.76 nm which are, respectively, due to the formation of an interfacial YbGeOx layer that well passivates the dangling bonds at Ge surface and the adoption of a crystalline ZrTiO4 film with a κ value of 45.6. The gate stack also shows low leakage current, tight distribution of device parameters, and desirable reliability performance, paving an alternative avenue to develop high-performance Ge MOS devices.

Theoretical comparison of Si, Ge, and GaAs ultrathin p-type double-gate metal oxide semiconductor transistors

Based on a self-consistent multi-band quantum transport code including hole-phonon scattering, we compare current characteristics of Si, Ge, and GaAs p-type double-gate transistors. Electronic properties are analyzed as a function of (i) transport orientation, (ii) channel material, and (iii) gate length. We first show that ⟨100⟩-oriented devices offer better characteristics than their ⟨110⟩-counterparts independently of the material choice. Our results also point out that the weaker impact of scattering in Ge produces better electrical performances in long devices, while the moderate tunneling effect makes Si more advantageous in ultimately scaled transistors. Moreover, GaAs-based devices are less advantageous for shorter lengths and do not offer a high enough ON current for longer gate lengths. According to our simulations, the performance switching between Si and Ge occurs for a gate length of 12 nm. The conclusions of the study invite then to consider ⟨100⟩-oriented double-gate devices with Si for gate length shorter than 12 nm and Ge otherwise.

High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using $\hbox{HfO}_{2}/\hbox{Al}_{2}\hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}$ Gate Stacks Fabricated by Plasma Postoxidation

An ultrathin equivalent oxide thickness (EOT) HfO2/Al2O3/Ge gate stack has been fabricated by combining the plasma postoxidation method with a 0.2-nm-thick Al2O3 layer between HfO2 and Ge for suppressing HfO2-GeOx intermixing, resulting in a low-interface-state-density (Dit) GeOx/Ge metal-oxide-semiconductor (MOS) interface. The EOT of these gate stacks has been scaled down to 0.7-0.8 nm with maintaining the Dit in 1011 cm-2·eV-1 level. The p- and n-channel MOS field-effect transistors (MOSFETs) (p- and n-MOSFETs) using this gate stack have been fabricated on (100) Ge substrates and exhibit high hole and electron mobilities. It is found that the Ge p- and n-MOSFETs exhibit peak hole mobilities of 596 and 546 cm2/V·s and peak electron mobilities of 754 and 689 cm2/V·s at EOTs of 0.82 and 0.76 nm, respectively, which are the record-high reports so far for Ge MOSFETs in subnanometer EOT range because of the sufficiently passivated Ge MOS interfaces in present HfO2/Al2O3/GeOx/Ge gate stacks.

Mechanism of dopant-vacancy association in α-quartz GeO2

Improving the electron mobility of devices such as Ge metal oxide semiconductor field effect transistors requires good Ge/dielectric interfaces. GeO2 thus is reconsidered as a passivation layer for Ge. However, O-vacancies need to be controlled as they have a deleterious impact on the properties. We employ electronic structure calculations to investigate the introduction of trivalent ions (Al, Y, and La) in α-quartz GeO2. The binding energies of the dopant-vacancy pairs reveal that dopants can be used to control the O-vacancies and reduce the induced dangling bonds. It is proposed that the introduction of Al will limit the concentration of O-vacancies at low Fermi energy.

Wet thermal annealing effect on TaN/HfO2/Ge metal—oxide—semiconductor capacitors with and without a GeO2 passivation layer

Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal—oxide—semiconductor (MOS) structures with and without a GeO2 passivation layer are investigated. The physical and the electrical properties are characterized by X-ray photoemission spectroscopy, high-resolution transmission electron microscopy, capacitance—voltage (C—V) and current—voltage characteristics. It is demonstrated that wet thermal annealing at relatively higher temperature such as 550 °C can lead to Ge incorporation in HfO2 and the partial crystallization of HfO2, which should be responsible for the serious degradation of the electrical characteristics of the TaN/HfO2/Ge MOS capacitors. However, wet thermal annealing at 400 °C can decrease the GeOx interlayer thickness at the HfO2/Ge interface, resulting in a significant reduction of the interface states and a smaller effective oxide thickness, along with the introduction of a positive charge in the dielectrics due to the hydrolyzable property of GeOx in the wet ambient. The pre-growth of a thin GeO2 passivation layer can effectively suppress the interface states and improve the C—V characteristics for the as-prepared HfO2 gated Ge MOS capacitors, but it also dissembles the benefits of wet thermal annealing to a certain extent.

Variation of Surface Roughness on Ge Substrate by Cleaning in Deionized Water and its Influence on Electrical Properties in Ge Metal–Oxide–Semiconductor Field-Effect Transistors

The control of Ge surface roughness using deionized water (DIW) was systematically investigated. It was found that a very flat surface was obtained by pure-DIW dipping at room temperature, while quite a rough surface was observed at high temperature. The surface reaction model of Ge with H2O is proposed to explain the correlation of surface roughness (SR) formation with the etching process of Ge in DIW. In addition, the effects of SR on electrical properties in Ge/GeO2 stack such as capacitance–voltage (C–V) curves, interface state density, and electron mobility are presented.

Variation of Surface Roughness on Ge Substrate by Cleaning in Deionized Water and its Influence on Electrical Properties in Ge Metal–Oxide–Semiconductor Field-Effect Transistors

Variation of Surface Roughness on Ge Substrate by Cleaning in Deionized Water and its Influence on Electrical Properties in Ge Metal–Oxide–Semiconductor Field-Effect Transistors

Improved AC conductance and Gray-Brown methods to characterize fast and slow traps in Ge metal–oxide–semiconductor capacitors

We use an improved AC conductance method and a modified Gray-Brown method to study fast interface traps and slow border traps in Ge-based MOS capacitors. The combined methods provide the corrected Fermi energy level (E) versus gate voltage (Vg) relationship, even in samples with high densities of traps that cause significant C-V distortion, the energy distribution of interface traps, their capture cross sections (σ), as well as slow border traps. A wide range of σ’s in p-type Ge is found, indicating that there is more than one type of interface trap near the Ge valence band edge. In contrast, a constant σ near the Ge conduction band edge is observed in n-type Ge. XPS results indicate that Ge suboxides near the interface are accountable for the detected slow border traps.

Improvement of Thermal Stability of Ni-Germanide with Ni/Co/Ni/TiN Structure for High Performance Ge Metal–Oxide–Semiconductor Field Effect Transistors

In this paper, the thermal stability of Ni-germanide is improved by utilizing Ni/Co/Ni/TiN structure for Ge metal–oxide–semiconductor field effect transistors (MOSFETs) technology. It was shown that the Ni/Co/Ni/TiN structure improved the thermal stability of Ni-germanide mainly due to the suppression of Ni diffusion, and/or the retardation of agglomeration. The incorporated Co atoms distributed, mainly in the top region of the Ni-germanide and it is believed that this Co-rich Ni-germanide layer in the upper region of Ni-germanide enhanced the thermal stability. Therefore, the proposed Ni/Co/Ni/TiN structure is promising for the formation of a highly thermally immune Ni-germanide for nanoscale Ge MOSFETs technology.

Improvement of Thermal Stability of Ni-Germanide with Ni/Co/Ni/TiN Structure for High Performance Ge Metal–Oxide–Semiconductor Field Effect Transistors

Improvement of Thermal Stability of Ni-Germanide with Ni/Co/Ni/TiN Structure for High Performance Ge Metal–Oxide–Semiconductor Field Effect Transistors