Abstract
We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/SiO2/SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe nano-patterned pillar over a Si3N4 buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5−90 nm), the SiO2 thickness (3−4 nm), and as well the SiGe-shell thickness (2−15 nm) has been demonstrated, enabling a practically-achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO2/Ge-dot and SiO2/SiGe interfaces were assessed using transmission electron microscopy, energy dispersive x-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO2/SiGe and Al/SiO2/Ge-dot/SiO2/SiGe MOS capacitors exhibit low interface trap densities of as low as 3-5x10^11 cm^-2·eV^-1 and fixed charge densities of 1-5x10^11 cm^-2, suggesting good-quality SiO2/SiGe-shell and SiO2/Ge-dot interfaces. In addition, the advantage of having single-crystalline Si1-xGex shell (x > 0.5) in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge) MOS nanoelectronic and nanophotonic applications.
Highlights
Heterostructures of SiO2/Si have been the microstructural heart of metal-oxide-semiconductor (MOS) devices that have dominated integrated circuit (IC) technology since its inception nearly 60 years ago
Our previous results (Chien et al, 2011; Kuo et al, 2012; Wang et al, 2013; Chen et al, 2014; Lai et al, 2015) have shown that thermal oxidation performed on poly-Si0.85Ge0.15 nano-pillar structures preferentially converts the Si from the poly-Si0.85Ge0.15 to SiO2, leading to the formation of a single Ge dot within each oxidized nano-pillar through an unusual Ostwald Ripening process consolidating the segregated Ge nanocrystallites (Chien et al, 2011)
Excess thermal oxidation of 15–65 min enables the as-formed Ge dot to penetrate the underlying, buffer Si3N4 layer, and form a 2–15-nm-thick Si1−xGex-shell layer (x > 0.5) with a “cup”-shape morphology near the top surface of the Si substrate when the Ge dot comes in close proximity to the Si substrate
Summary
Heterostructures of SiO2/Si have been the microstructural heart of metal-oxide-semiconductor (MOS) devices that have dominated integrated circuit (IC) technology since its inception nearly 60 years ago. During the thermal oxidation process for fabricating the conventional Ge MOSFET gate structure, the interfaces, either between Ge and Si or between Ge and the gate dielectric layers, are susceptible to defect formation (Brunco et al, 2008a; Kamata, 2008). This is because of the large lattice mismatch of 4.2% that exists between Ge and Si as well as the fact that GeOx is both water-soluble and thermally unstable, all of which are key detriments to good device performance. All processing temperatures are constrained to be below 500°C in order to prevent GeO desorption that severely deteriorates the Ge/ dielectric interface and the thermal stability of the Ge MOSFETs (Lee et al, 2011; Nishimura et al, 2011; Takenaka et al, 2013)
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