Ge Condensation Process Research Articles

Ge Condensation Technologies for Advanced MOSFETs on SGOI and GOI Substrates

Recent developments in the Ge condensation technique for the fabrication of the SiGe on insulator (SGOI) structures, which are the basic templates for the strained channel MOSFET's, and the further extensions to the SGOI formation on (110) substrates and the Ge on insulator (GOI) formation are reviewed in this paper. The detail analyses of the phenomenon during the initial stage in the Ge condensation process, in which the fragments of the misfit dislocations, that are formed at the SiGe / SOI interface, rise up resulting the generation of the threading dislocations are quite important, and the controlling of the understood phenomenon by the modification of the condensation recipe brings the successful fabrication of the high quality SGOI substrates with low dislocation density.

Highly strain-relaxed ultrathin SiGe-on-insulator structure by Ge condensation process combined with H+ irradiation and postannealing

Strain-relaxation process of SiGe-on-insulator (SGOI) structures in the oxidation induced Ge condensation method has been investigated as a function of the SiGe thickness. Complete relaxation was obtained for thick SGOI layers (>100nm). However, the relaxation rates abruptly decreased with decreasing SiGe thickness below 50nm, i.e., the relaxation rate of 30% at 30nm SiGe thickness. In order to improve this phenomenon, a method combined with H+ irradiation with a medium dose (5×1015cm−2) and postannealing (1200°C) has been developed. This successfully achieved the high relaxation rate (70%) in the ultrathin SGOI (30nm).

Visualisation of Ge Condensation in SOI

AbstractWe use a novel technique CABOOM – Characterisation of Alloy concentration via Beveling, Oxidation and Optical Microscopy – to visualize the change of the Ge concentration sandwiched between two SiO2 layers during the Ge condensation process. CABOOM is very sensitive to variations in the gradient of the Ge concentration in the SiGe layer and thus gives a fast and simple way to interpret the condensation process. We present a systematic study of Ge condensation in a 120nm thick Si0.92Ge0.08 layer on a 60 nm Si body SOI (silicon-on-insulator) as a function of oxidation temperature and time, using CABOOM, SIMS and XRD. CABOOM shows the non-linear variation of the Ge diffusion as a function of process time.

Fabrication and Electrical Characterization of Strained Si-on-insulator/Strained SiGe-on-insulator Dual Channel CMOS structures with High-Mobility Channels

Mobility enhancement technologies by incorporating strain in MOSFETs have been recognized as key technologies for scaled CMOS devices. The most promising channel materials for n- and p-channel MOSFETs are tensily-strained Si and compressively-strained Ge (SiGe), respectively, from the viewpoint of their high mobility values. In this paper, dual channel CMOS structures with strained Si-on-insulator (strained-SOI)-nMOSFETs and strained SiGe-on-insulator (strained-SGOI)-pMOSFETs are demonstrated as well as their high channel mobility and current drive enhancements. Strained Si channels on a relaxed SGOI substrate and Ge-rich strained SGOI channels are located on the nMOS and pMOS regions of the same wafer, respectively. The dual channel structure was fabricated by a CMOS process combined with the Ge condensation process, in which the epitaxially grown SiGe layer on the SOI substrate was locally oxidized at high temperatures. As a result, significant electron- and hole-mobility enhancements for the strained SOI and SGOI channels were observed as well as the drain current enhancements. Based on the measured mobility for the nMOS and pMOS channels in the CMOS devices, CMOS performance enhancement of 30% was estimated.

Thickness-dependent stress-relaxation in thin SGOI structures and its improvement

The oxidation-induced Ge condensation process of SiGe/Si on insulator structures has been investigated. The relaxation rate obtained in the SiGe layers on insulator (SGOI) abruptly decreased with decreasing SGOI thickness below 50 nm. In order to enhance the relaxation rate in the ultra-thin SGOI, the new technique combined with H + irradiation with a medium dose (5 × 10 15 cm − 2 ) and post-annealing (1200 °C) has been developed. It was demonstrated that the highly relaxed (70%) ultra-thin SGOI with a low defect density (8 × 10 6 cm − 2 ) has been realized by this technique.

Lattice relaxation and dislocation generation/annihilation in SiGe-on-insulator layers during Ge condensation process

Dislocation behaviors in SiGe-on-insulator (SGOI) layers during the Ge condensation process are systematically studied by employing transmission electron microscopy, X-ray diffraction, Raman spectroscopy and secondary ion mass spectroscopy, in order to obtain insights into sufficient relaxation of SGOI layers with good crystal quality. It is found that misfit dislocations (MDs) are generated in the ramping up process in Ge condensation, whereas they disappear and threading dislocations (TDs) are generated after the oxidation process. This TD generation is attributable to the fact that the MDs were fragmented into dislocation half-loops and then rose to the SiGe surface. Thus, suppression of the rising motion is a key to fabricating high-quality SGOI substrates by the Ge-condensation technique.

Improvement of Oxidation-Induced Ge Condensation Method by H+ Implantation and Two-Step Annealing for Highly Stress-Relaxed SiGe-on-Insulator

The effects of the H+ implantation (8.1 keV and 0–5×1016 cm-2) and two-step annealing (1st: 500°C for 30 min, 2nd: 850°C for 60 min) on the stress relaxation of c-Si1-xGex buffer layers on insulator (SGOI) formed by the oxidation-induced Ge condensation process have been investigated. The stress relaxation of SGOI during oxidation (1100°C) was significantly improved by high-dose (>1015 cm-2) H+ implantation. However, the oxidation was also enhanced by the implantation. The enhanced oxidation was completely suppressed by the two-step annealing before oxidation. The enhanced stress relaxation was attributed to the enhanced gliding of the c-Si1-xGex layers on SiO2. This newly developed combination method of H+ implantation, the two-step annealing, and the oxidation-induced Ge condensation will be a powerful tool in the fabrication of highly relaxed SGOI for growth of strained Si layers.

H + implantation-enhanced stress relaxation in c-Si 1−xGe x on SiO 2 during oxidation-induced Ge condensation process

Enhancement effects of H + implantation on stress relaxation of c-Si 1− x Ge x layers on SiO 2 during oxidation-induced Ge condensation process have been investigated. Stress relaxation of c-Si 1− x Ge x layers during oxidation (1100 °C) was significantly improved by high-dose (>10 15 cm −2) H + implantation. However, oxidation was also enhanced by implantation. Enhanced oxidation was completely suppressed by the two-step annealing (1st: 500 °C for 30 min, 2nd: 850 °C for 60 min) before oxidation. The enhanced stress relaxation was tentatively assigned to enhanced gliding of c-Si 1− x Ge x layers on SiO 2. This newly developed combination method of H + implantation, two-step annealing, and oxidation-induced Ge condensation will be a powerful tool to fabricate highly relaxed c-Si 1− x Ge x buffer layers for growing strained Si layers.