Gaussian Random Number Generator Research Articles

WALLAX: A memristor-based Gaussian random number generator

Generating Gaussian random numbers is essential in many applications such as cryptography, games, and computer simulations. Although software Gaussian Random Number Generators (GRNG) are widely used, hardware designs have been explored for their faster speed and lower computational cost. However, hardware GRNGs usually occupy large silicon areas when implemented in Complementary Metal Oxide Semiconductor (CMOS) technology, especially for their essential Uniform Random Number Generator (URNG) part. Here, we present a memristor-based GRNG, named WALLAX, conceived from the Wallace method to generate random numbers iteratively. This GRNG circuit benefits not only from the fully parallel analog-based Vector Matrix Multiplication (VMM) feature of memristive crossbars but also harness the intrinsic stochastic switching behaviour of the memristive devices to efficiently produce truly random numbers. The vector-matrix multiplication of WALLAX is implemented on the memristive crossbar, while its random fetching step is realized by a URNG based on the stochastic switching nature of memristors. WALLAX successfully passes all the tests in the NIST 800-22 randomness test suite with 105 numbers generated and five goodness-of-fit tests with various pool sizes and effectively reduces the power and area consumption by 68.78% and 70.0% compared to digital implementations of the same GRNG method. The impact brought by memristor non-idealities is investigated by simulating the proposed structure with 1000 pools under various scenarios. Wire resistance and the stuck of state, each result in a 2.2% and 12.3% reduction in test pass rate within the tested range, respectively.

A Scoping Review of Cerebral Doppler Arterial Waveforms in Infants.

Cerebral Doppler ultrasound has been an important tool in pediatric diagnostics and prognostics for decades. Although the Doppler spectrum can provide detailed information on cerebral perfusion, the measured spectrum is often reduced to simple numerical parameters. To help pediatric clinicians recognize the visual characteristics of disease-associated Doppler spectra and identify possible areas for future research, a scoping review of primary studies on cerebral Doppler arterial waveforms in infants was performed. A systematic search in three online bibliographic databases yielded 4898 unique records. Among these, 179 studies included cerebral Doppler spectra for at least five infants below 1 y of age. The studies describe variations in the cerebral waveforms related to physiological changes (43%), pathology (62%) and medical interventions (40%). Characteristics were typically reported as resistance index (64%), peak systolic velocity (43%) or end-diastolic velocity (39%). Most studies focused on the anterior (59%) and middle (42%) cerebral arteries. Our review highlights the need for a more standardized terminology to describe cerebral velocity waveforms and for precise definitions of Doppler parameters. We provide a list of reporting variables that may facilitate unambiguous reports. Future studies may gain from combining multiple Doppler parameters to use more of the information encoded in the Doppler spectrum, investigating the full spectrum itself and using the possibilities for long-term monitoring with Doppler ultrasound.

An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET

Bayesian neural networks (BNNs) have been proposed to address the problems of overfitting and overconfident decision making, common in conventional neural networks (NNs), due to their ability to model and express uncertainty in their predictions. However, BNNs require multiple inference passes to produce the necessary posterior distributions used to generate these highly desirable uncertainty estimates. As such, BNNs require not only an efficient, high-performance multiply-accumulation (MAC) operation but also an efficient Gaussian random number generator (GRNG) with high-quality statistics. In this article, an NN accelerator chip, leveraging a multi-bit analog compute-in-memory (CiM) static random-access memory (SRAM) macro, with a tightly coupled and highly efficient GRNG scheme, is presented in the Intel 22FFL process. The CiM macro achieves a peak energy efficiency of 32.2 TOP/sW, with 8-bit precision, while ensuring accurate on-chip matrix-vector multiplications (MVMs) with a computation error less than 0.5%. The variable precision GRNG achieves a peak throughput of 7.31 GSamp/s for an energy efficiency of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim$</tex-math> </inline-formula> 1 TSamp/J. Overall, our proposed system achieves a peak energy efficiency of 1170 GOP/s/W, a 35–133 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> improvement over the state-of-the-art BNN accelerators, with 98.14% accuracy for the MNIST dataset.

B[formula omitted]N[formula omitted]: Resource efficient Bayesian neural network accelerator using Bernoulli sampler on FPGA

A resource efficient hardware accelerator for Bayesian neural network (BNN) named B2N2, Bernoulli random number based Bayesian neural network accelerator, is proposed. As neural networks expand their application into risk sensitive domains where mispredictions may cause serious social and economic losses, evaluating the NN’s confidence on its prediction has emerged as a critical concern. Among many uncertainty evaluation methods, BNN provides a theoretically grounded way to evaluate the uncertainty of NN’s output by treating network parameters as random variables. By exploiting the central limit theorem, we propose to replace costly Gaussian random number generators (RNG) with Bernoulli RNG which can be efficiently implemented on hardware since the possible outcome from Bernoulli distribution is binary. We demonstrate that B2N2 implemented on Xilinx ZCU104 FPGA board consumes only 465 DSPs and 81661 LUTs which corresponds to 50.9% and 14.3% reductions compared to Gaussian-BNN (Hirayama et al., 2020) implemented on the same FPGA board for fair comparison. We further compare B2N2 with VIBNN (Cai et al., 2018), which shows that B2N2 successfully reduced DSPs and LUTs usages by 50.9% and 57.9%, respectively. Owing to the reduced hardware resources, B2N2 improved energy efficiency by 7.50% and 57.5% compared to Gaussian-BNN (Hirayama et al., 2020) and VIBNN (Cai et al., 2018), respectively.

Gaussian Random Number Generator With Reconfigurable Mean and Variance Using Stochastic Magnetic Tunnel Junctions

Generating high-quality random numbers with a Gaussian probability distribution function is an important and resource-consuming computational task for many applications in the fields of machine learning and Monte Carlo algorithms. Recently, complementary metal&#x2013;oxide&#x2013;semiconductor (CMOS)-based digital hardware architectures have been explored as specialized Gaussian random-number generators (GRNGs). These CMOS-based GRNGs have a large area and require entropy sources at their input that increase the computing cost. In this letter we present a GRNG that works on the principle of the Boltzmann law in a physical system made from an interconnected network of thermally unstable magnetic tunnel junctions. The presented hardware can produce multibit Gaussian random numbers at gigahertz speed and can be configured to generate distributions with a desired mean and variance. An analytical derivation of the required interconnection and bias strengths is provided, followed by numerical simulations to demonstrate the functionalities of the GRNG.

Design of Gaussian modulator for continuous-variable quantum key distribution

The continuous-variable quantum key distribution experimental system requires the randomness and speed of a Gaussian modulator. We present the hardware design for a Gaussian random number (GRN) generator based on the Box–Muller method, which can be implemented on a field-programmable gate array (FPGA). An external high-speed true random number generator application-specific integrated circuit (ASIC) is used to this end. The ASIC operates faster and more independently compared with other Gaussian algorithms based on a linear feedback shift register. The trigonometric and logarithmic functions are calculated using the nonuniform piecewise linear approximation. The calculation of the Gaussian random modulus and phase value is realized using this hardware. Compared with an arbitrary waveform generator, the GRN can be uploaded to a computer to estimate the security key rate. Furthermore, the GRN generator accurately provides a Gaussian probability density function that passes the Jarque–Bera inspection and Lilliefors tests. The proposed FPGA-based system is demonstrated to convert eight-channel 320-Mbps uniform random numbers to 40-MHz 16-bit GRN in real time. Finally, the control of the optical module and Gaussian modulation is realized via the FPGA-based outputs of four dual-channel, 16-bit, 1-giga samples per second digital-to-analog converters.

Random Walk of Foraging

The model of vibration driven random walk is adapted to description of foraging performed by simple organisms. Stochastic properties of foraging are described by the Gaussian random number generator, while the attraction of food is represented by a deterministic signal that directs walkers from surroundings to the food. This attraction causes transition from the Gaussian random walk to the Levy flight.

Gaussian random number generator: Implemented in FPGA for quantum key distribution

AbstractQuantum key distribution is the process of using quantum communication to establish a shared key between two parties. It has been demonstrated the unconditional security and effective communication of quantum communication system can be guaranteed by an excellent Gaussian random number (GRN) generator with high speed and an extended random period. In this paper, we propose to construct the Gaussian random number generator by using field‐programmable gate array (FPGA), which is able to process large data in high speed. We also compare three algorithms of GRN generation: Box‐Muller algorithm, polarization decision algorithm, and central limit algorithm. We demonstrate that the polarization decision algorithm implemented in FPGA requires less computing resources and also produces a high‐quality GRN through the null hypothesis test.

ASIC Implementation of a Nonlinear Dynamical Model for Hippocampal Prosthesis.

A hippocampal prosthesis is a very large scale integration (VLSI) biochip that needs to be implanted in the biological brain to solve a cognitive dysfunction. In this letter, we propose a novel low-complexity, small-area, and low-power programmable hippocampal neural network application-specific integrated circuit (ASIC) for a hippocampal prosthesis. It is based on the nonlinear dynamical model of the hippocampus: namely multi-input, multi-output (MIMO)-generalized Laguerre-Volterra model (GLVM). It can realize the real-time prediction of hippocampal neural activity. New hardware architecture, a storage space configuration scheme, low-power convolution, and gaussian random number generator modules are proposed. The ASIC is fabricated in 40 nm technology with a core area of 0.122 mm[Formula: see text] and test power of 84.4 [Formula: see text]W. Compared with the design based on the traditional architecture, experimental results show that the core area of the chip is reduced by 84.94% and the core power is reduced by 24.30%.

VIBNN

Bayesian Neural Networks (BNNs) have been proposed to address the problem of model uncertainty in training and inference. By introducing weights associated with conditioned probability distributions, BNNs are capable of resolving the overfitting issue commonly seen in conventional neural networks and allow for small-data training, through the variational inference process. Frequent usage of Gaussian random variables in this process requires a properly optimized Gaussian Random Number Generator (GRNG). The high hardware cost of conventional GRNG makes the hardware implementation of BNNs challenging. In this paper, we propose VIBNN, an FPGA-based hardware accelerator design for variational inference on BNNs. We explore the design space for massive amount of Gaussian variable sampling tasks in BNNs. Specifically, we introduce two high performance Gaussian (pseudo) random number generators: 1) the RAM-based Linear Feedback Gaussian Random Number Generator (RLF-GRNG), which is inspired by the properties of binomial distribution and linear feedback logics; and 2) the Bayesian Neural Network-oriented Wallace Gaussian Random Number Generator. To achieve high scalability and efficient memory access, we propose a deep pipelined accelerator architecture with fast execution and good hardware utilization. Experimental results demonstrate that the proposed VIBNN implementations on an FPGA can achieve throughput of 321,543.4 Images/s and energy efficiency upto 52,694.8 Images/J while maintaining similar accuracy as its software counterpart.

Enhanced Box-Muller method for high quality Gaussian random number generation

Fast and high-quality Gaussian random number generation (GRNG) is a key capability for simulations across a wide range of disciplines. In this article, we present an enhanced Box-Muller method for GRNG using one uniform variable. Its probability density function (PDF) is given in closed form as a function of one parameter. In this article, the theoretical basis of this method is quite thoroughly discussed and is evaluated using several different statistical tests, including the chi-square test and the Anderson-Darling test. The simulations results show good performances of this method which generates accurately a true Gaussian PDF even at very high σ (standard deviations) values in comparison with the standard Box-Muller method.

Enhanced Box-Muller method for high quality Gaussian random number generation

Fast and high-quality Gaussian random number generation (GRNG) is a key capability for simulations across a wide range of disciplines. In this article, we present an enhanced Box-Muller method for GRNG using one uniform variable. Its probability density function (PDF) is given in closed form as a function of one parameter. In this article, the theoretical basis of this method is quite thoroughly discussed and is evaluated using several different statistical tests, including the chi-square test and the Anderson-Darling test. The simulations results show good performances of this method which generates accurately a true Gaussian PDF even at very high σ (standard deviations) values in comparison with the standard Box-Muller method.

Gaussian Random Number Generation

Some excellent surveys of the Gaussian random number generators (GRNGs) from the algorithmic perspective exist in the published literature to date (e.g., Thomas et al. [2007]). In the last decade, however, advancements in digital hardware have resulted in an ever-decreasing hardware cost and increased design flexibility. Additionally, recent advances in applications like gaming, weather forecasting, and simulations in physics and astronomy require faster, cheaper, and statistically accurate GRNGs. These two trends have contributed toward the development of a number of novel GRNG architectures optimized for hardware design. A detailed comparative study of these hardware architectures has been somewhat missing in the published literature. This work provides the potential user a capsulization of the published hardware GRNG architectures. We have provided the method and theory, pros and cons, and a comparative summary of the speed, statistical accuracy, and hardware resource utilization of these architectures. Finally, we have complemented this work by describing two novel hardware GRNG architectures, namely, the CLT-inversion and the multihat algorithm, respectively. These new architectures provide high tail accuracy ( 6σ and 8σ , respectively) at a low hardware cost.

Novel quantum inspired binary neural network algorithm

In this paper, a quantum based binary neural network algorithm is proposed, named as novel quantum binary neural network algorithm (NQ-BNN). It forms a neural network structure by deciding weights and separability parameter in quantum based manner. Quantum computing concept represents solution probabilistically and gives large search space to find optimal value of required parameters using Gaussian random number generator. The neural network structure forms constructively having three number of layers input layer: hidden layer and output layer. A constructive way of deciding the network eliminates the unnecessary training of neural network. A new parameter that is a quantum separability parameter (QSP) is introduced here, which finds an optimal separability plane to classify input samples. During learning, it searches for an optimal separability plane. This parameter is taken as the threshold of neuron for learning of neural network. This algorithm is tested with three benchmark datasets and produces improved results than existing quantum inspired and other classification approaches.

The Table-Hadamard GRNG

Gaussian random number generators (GRNGs) are an important component in parallel Monte Carlo simulations using FPGAs, where tens or hundreds of high-quality Gaussian samples must be generated per cycle using very few logic resources. This article describes the Table-Hadamard generator, which is a GRNG designed to generate multiple streams of random numbers in parallel. It uses discrete table distributions to generate pseudo-Gaussian base samples, then a parallel Hadamard transform to efficiently apply the central limit theorem. When generating 64 output samples, the Table-Hadamard requires just 130 slices per generated sample, which is a third of the resources needed by the next best technique, while still providing higher statistical quality.

Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI

Gaussian random numbers (GRNs) generated by central limit theorem (CLT) suffer from errors due to deviation from ideal Gaussian behavior for any finite number of additions. In this paper, we will show that it is possible to compensate the error in CLT, thereby correcting the resultant probability density function, particularly in the tail regions. We will provide a detailed mathematical analysis to quantify the error in CLT. This provides a design space with more than four degrees of freedom to build a variety of GRN generators (GRNGs). A framework utilizes this design space to generate customized hardware architectures. We will demonstrate designs of five different architectures of GRNGs, which vary in terms of consumed memory, logic slices, and multipliers on field-programmable gate array. Similarly, depending upon application, these architectures exhibit statistical accuracy from low ( ${\rm {{4}}} \sigma $ ) to extremely high ( ${\rm {{12}}} \sigma $ ). A comparison with previously published designs clearly indicate advantages of this methodology in terms of both consumed hardware resources and accuracy. We will also provide synthesis results of same designs in application-specific integrated circuit using 65-nm standard cell library. Finally, we will highlight some shortcomings associated with such architectures followed by their remedies.

Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs

The multivariate Gaussian distribution is used to model random processes with distinct pair-wise correlations, such as stock prices that tend to rise and fall together. Multivariate Gaussian vectors with length n are usually produced by first generating a vector of n independent Gaussian samples, then multiplying with a correlation inducing matrix requiring O(n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) multiplications. This paper presents a method of generating vectors directly from the uniform distribution, removing the need for an expensive scalar Gaussian generator, and eliminating the need for any multipliers. The method relies only on small read-only memories and adders, and so can be implemented using only logic resources (lookup-tables and registers), saving multipliers, and block-memory resources for the numerical simulation that the multivariate generator is driving. The new method provides a ten times increase in performance (vectors/second) over the fastest existing field-programmable gate array generation method, and also provides a five times improvement in performance per resource over the most efficient existing method. Using this method, a single 400-MHz Virtex-5 FPGA can generate vectors ten times faster than an optimized implementation on a 1.2-GHz graphics processing unit, and a hundred times faster than vectorized software on a general purpose quad core 2.2-GHz processor.

FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options

In this paper we present an FPGA implementation of a Monte-Carlo method for pricing Asian options using Impulse C and floating-point arithmetic. In an Altera Stratix-V FPGA, a 149x speedup factor was obtained against an OpenMP-based solution in a 4-core Intel Core i7 processor. This speedup is comparable to that reported in the literature using a classic HDL-based methodology, but the development time is significantly reduced. Additionally, the use of a HLL-based methodology allowed us to implement a high-quality Gaussian random number generator, which produces more precise results than those obtained with the simple generators usually present in HDL-based designs.

Design and Implementation of a FPGA Based Gaussian Random Number Generator

A good FPGA based Gaussian Random Number Generator has to be reconfigurable for different applications,while running fast and acquiring a high throughput per slice.In this paper,a hardware structure of the Transform Module is proposed.The configuration process and principle of the period and output bit-width of uniform random numbers are introduced.For the generation of Gaussian random numbers,methods for bit-width optimization of the fixed point operands are introduced in details.Implementation results on Xilinx Vertex 5 FPGA show that the proposed hardware design could acquire a frequency as high as 491 MHz,while the corresponding throughput is 9.82×108samples/second and the throughput per slice is 2.085×106samples/second/slice.DIEHARD test suit,χ 2 and K-S method are used to test the quality of the generated random numbers here.

An Optimized Hardware Architecture of a Multivariate Gaussian Random Number Generator

Monte Carlo simulation is one of the most widely used techniques for computationally intensive simulations in mathematical analysis and modeling. A multivariate Gaussian random number generator is one of the main building blocks of such a system. Field Programmable Gate Arrays (FPGAs) are gaining increased popularity as an alternative means to the traditional general purpose processors targeting the acceleration of the computationally expensive random number generator block. This article presents a novel approach for mapping a multivariate Gaussian random number generator onto an FPGA by optimizing the computational path in terms of hardware resource usage subject to an acceptable error in the approximation of the distribution of interest. The proposed approach is based on the eigenvalue decomposition algorithm which leads to a design with different precision requirements in the computational paths. An analysis on the impact of the error due to truncation/rounding operation along the computational path is performed and an analytical expression of the error inserted into the system is presented. Based on the error analysis, three algorithms that optimize the resource utilization and at the same time minimize the error in the output of the system are presented and compared. Experimental results reveal that the hardware resource usage on an FPGA as well as the error in the approximation of the distribution of interest are significantly reduced by the use of the optimization techniques introduced in the proposed approach.