Gate Metal Oxide Semiconductor Research Articles

Comparative Study of Different High Voltage Switches Used in Pulsed High Voltage Application

High-voltage switches play a crucial role in pulsed power applications, where the efficient and reliable control of highvoltage pulses is required. This study aims to compare different types of high-voltage switches commonly used in pulsed power systems including electromechanical switches, vacuum switches, gas-filled switches, triggered spark gaps and solidstate switches. The comparison study focuses on key performance parameters such as voltage handling capability, current carrying capacity, turn-on time, and repetition rates are considered to provide a comprehensive study and analysis of the switch’s suitability for different pulsed power applications. Gas-filled switches such as spark gaps, thyratrons and ignitrons have been used in pulsed power systems due to their high voltage handling capability and low switching losses. However, they suffer from a limited lifetime and require maintenance and periodic replacement. Solid-state switches, i.e. Silicon-Controlled Rectifiers (SCRs), Insulated Gate Bipolar Transistors (IGBTs) and Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) offer advantages in terms of longevity, reliability, and reduced maintenance. However, they have limitations in high-voltage applications and exhibit higher switching losses. The findings of this comparison study will assist researchers, engineers, and system designers in selecting the most appropriate high-voltage switch for pulsed power applications, considering the specific requirements and constraints of the system. This will ultimately contribute to the advancement and optimization of pulsed power technologies across a wide range of scientific, industrial, and strategic applications.

Relaxation kinetics of interface states and bulk traps in atomic layer deposited ZrO2/β-Ga2O3 metal-oxide-semiconductor capacitors

The study of interface states and bulk traps and their connection to device instability is highly demanded to achieve reliable β-Ga2O3 metal-oxide-semiconductor (MOS) devices. However, a comprehensive analysis of the capture/emission behavior of interface states and bulk traps can be challenging due to widespread time constant distribution. In this study, using capacitance transient measurement tools, trap states of the ZrO2/β-Ga2O3 MOS gate stack were explicitly investigated, particularly its bias- and temperature-dependent relaxation kinetics. As forward bias is enlarged, it is observed that the interface state density (Dit) increases by 12.6%. Two bulk traps with discrete levels identified as 0.43 eV (E1) and 0.74 eV (E2) below the conduction band minimum were extracted by deep-level transient spectroscopy. It is further revealed that the emission processes of E1 and E2 are thermally enhanced, while the capture processes remain insensitive to temperature. The electric-field dependence of E1 indicates that the dominant mechanism follows the rule of Poole–Frenkel emission. The capacitance–voltage (C–V) hysteresis deteriorated at a higher forward bias due to the higher trap density and increased population of trapped charges. These findings provide an important framework for future device optimization to improve the reliability and performance of β-Ga2O3 MOS devices.

Optimizing the initial weights of a PID neural network controller for voltage stabilization of microgrids using a PEO-GA algorithm

This paper proposes an adaptive PID neural network (PIDNN) controller for direct and quadrature voltage control of three-phase inverters for islanded microgrids. A hybrid metaheuristic optimization algorithm is proposed for the initial weight selection of the proposed PIDNN controller using a discrete-time simulation model incorporating the nonlinearity of the insulated gate bipolar transistor (IGBT) or metal oxide semiconductor field effect transistor (MOSFET) switches of the inverter. The proposed hybrid optimization (HO) approach is a combination of population extremal optimization (PEO) and genetic algorithm (GA). It turned out that the proposed HO-PIDNN control scheme excelled the PEO, GA, and particle swarm optimization-based PIDNN controllers in terms of the objective function value, which is composed of the integral time absolute tracking error of the output voltage and a chattering penalty factor. Also, the control system outperformed the model reference adaptive PID control technique from the literature.

Dependence of reverse leakage on the edge termination process in vertical GaN power device

The trench gate metal oxide semiconductor field effect transistor (MOSFET) represents a prominent device architecture among the Gallium Nitride (GaN) based vertical devices currently investigated for the next generation of power electronics. A low leakage current level in off-state under high drain bias is of great importance for vertical transistors since it is a crucial feature for high breakdown voltage and device reliability. The off-state drain leakage originates from different sources in the vertical trench gate MOSFET. Besides the trench gate module, the leakage paths at the dry-etched sidewall of the lateral edge termination can also significantly contribute to the off-state drain-current. In this report, the influence of each relevant process step on the drain leakage current in off-state that is related to the lateral edge termination is investigated utilizing specific test structures on high-quality GaN epitaxial material which mimic the lateral edge termination of the MOSFET. Electrical characterization reveals the sensitivity of the leakage current to plasma-related processes. A termination technology is presented that results in low leakage current while including thick dielectric layers from plasma-assisted deposition as intended for fabrication of a field plate structure over the edge termination.

A 4H-SiC semi-super-junction shielded trench MOSFET: p-pillar is grounded to optimize the electric field characteristics

A 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor (UMOSFET) with semi-super-junction shielded structure (SS-UMOS) is proposed and compared with conventional trench MOSFET (CT-UMOS) in this work. The advantage of the proposed structure is given by comprehensive study of the mechanism of the local semi-super-junction structure at the bottom of the trench MOSFET. In particular, the influence of the bias condition of the p-pillar at the bottom of the trench on the static and dynamic performances of the device is compared and revealed. The on-resistance of SS-UMOS with grounded (G) and ungrounded (NG) p-pillar is reduced by 52% (G) and 71% (NG) compared to CT-UMOS, respectively. Additionally, gate oxide in the GSS-UMOS is fully protected by the p-shield layer as well as semi-super-junction structure under the trench and p-base regions. Thus, a reduced electric-field of 2 MV/cm can be achieved at the corner of the p-shield layer. However, the quasi-intrinsic protective layer cannot be formed in NGSS-UMOS due to the charge storage effect in the floating p-pillar, resulting in a large electric field of 2.7 MV/cm at the gate oxide layer. Moreover, the total switching loss of GSS-UMOS is 1.95 mJ/cm2 and is reduced by 18% compared with CT-UMOS. On the contrary, the NGSS-UMOS has the slowest overall switching speed due to the weakened shielding effect of the p-pillar and the largest gate-to-drain capacitance among the three. The proposed GSS-UMOS plays an important role in high-voltage and high-frequency applications, and will provide a valuable idea for device design and circuit applications.

A 4H-SiC trench IGBT with controllable hole-extracting path for low loss

A novel 4H-SiC trench insulated gate bipolar transistor (IGBT) with a controllable hole-extracting (CHE) path is proposed and investigated in this paper. The CHE path is controlled by metal semiconductor gate (MES gate) and metal oxide semiconductor gate (MOS gate) in the p-shield region. The grounded p-shield region can significantly suppress the high electric field around gate oxide in SiC devices, but it weakens the conductivity modulation in the SiC trench IGBT by rapidly sweeping out holes. This effect can be eliminated by introducing the CHE path. The CHE path is pinched off by the high gate bias voltage at on-state to maintain high conductivity modulation and obtain a comparatively low on-state voltage (V ON). During the turn-off transient, the CHE path is formed, which contributes to a decreased turn-off loss (E OFF). Based on numerical simulation, the E OFF of the proposed IGBT is reduced by 89% compared with the conventional IGBT at the same V ON and the V ON of the proposed IGBT is reduced by 50% compared to the grounded p-shield IGBT at the same E OFF. In addition, the average power reduction for the proposed device can be 51.0% to 81.7% and 58.2% to 72.1% with its counterparts at a wide frequency range of 500 Hz to 10 kHz, revealing a great improvement of frequency characteristics.

Low-voltage bulk-driven flipped voltage follower-based transconductance amplifier

A low voltage high performance design of operational transconductance amplifier is proposed in this paper. The proposed architecture is based on bulk driven quasi-floating gate metal oxide semiconductor field effect transistor (MOSFET) which supports low voltage operation and improves the gain of the amplifier. Besides to this the tail current source requirement of operational transconductance amplifier (OTA) is removed by using the flipped voltage follower structure at the input pair along with bulk driven quasi-floating gate MOSFET. The proposed operational transconductance amplifier shows a five-fold increase in direct current (DC) gain and 3-fold increase in unity gain bandwidth when compared with its conventional bulk driven architecture. The metal oxide semiconductor (MOS) model used for amplifier design is of 0.18 um complementary metal oxide semiconductor (CMOS) technology at supply of 0.5 V.

An Accurate Drain Current Model of Dual Material Double Gate Metal Oxide Semiconductor Field Effect Transistor

An Accurate Drain Current Model of Dual Material Double Gate Metal Oxide Semiconductor Field Effect Transistor

Fabrication and characterization of a self-aligned gate stack for electronics applications

A metal–oxide–semiconductor (MOS) gate stack that is self-aligned with the underlying silicon doping profile is demonstrated. We combine a new hybrid bottom-up patterning technique with atomic layer deposition (ALD) to selectively deposit a platinum-hafnium dioxide-silicon MOS gate stack. A poly(methyl methacrylate) (PMMA) brush is blanket grown from a Si(100) surface and selectively removed from the lightly doped (∼1018 cm−3) regions using a doping-selective KOH etch. The PMMA brush that remains on the heavily doped (∼1020 cm−3) regions effectively blocks the ALD of both HfO2 and platinum. MOS capacitors exhibit promising capacitance-voltage characteristics with a HfO2 dielectric constant of ∼25 and an average interface state density of 2.1 × 1011 eV−1 cm−2 following forming gas anneal.

Construction of nano information storage model based on sensor bus

The size of semiconductor devices was decreasing, which brings severe challenges to traditional microelectronic technology. The improved memory model of floating gate MOS (metal–oxidesemiconductor) structure was proposed and applied. Based on this, the nano information storage model based on sensor bus was constructed. The sensor bus structure based on CAN (Controller Area Network) technology was designed by using the on-site regional control network and object connection embedding technology. The three-phase data acquisition system with the energy metering chip CS5490 as the core was used to collect the signals of the voltage and current sensors, and the CAN sensor bus controller was used to transmit the collected signals. The transmitted signal was stored in the information storage model of the nanocrystalline floating gate structure, which uses metal nanocrystals with the higher work function to store the charge. Increase the barrier between the storage node and the gate dielectric to improve program/erase and information retention. Experimental results show that the constructed model has longer data retention time while having low operating voltage and low power consumption.

Principles and impacts of dynamic threshold voltage in a p-GaN gate high-electron-mobility transistor

GaN power transistors are attracting increasing attention for next-generation power switching applications. However, GaN power transistors should not be regarded as a direct replacement for silicon power metal–oxide–semiconductor field-effect transistors, since the unique properties of GaN power transistors require special treatment. In this work we review a unique and critical property of GaN power transistors, the dynamic threshold voltage (V th). GaN power transistors feature a p-GaN gate structure, while the gate metal contacts the p-GaN layer through a Schottky junction. This unique p-GaN gate structure is distinctively different from the silicon metal–oxide–semiconductor gate structure in that the p-GaN layer is actually a floating region without direct electrical contact to the external electrodes of the device. The floating p-GaN layer enables a charge storage process during the switching operation of a p-GaN gate high-electron-mobility transistor. Through carefully designed experiments, the strong correlation between charge storage and the dynamic V th shift has been revealed; this also serves as an approach to accurately predict the dynamic V th during switching operation. The influence of the dynamic V th on power switching applications is discussed. For example, with a positive dynamic V th shift, the reverse conduction voltage of a GaN power transistor is significantly increased, adding to the power loss. This positive V th shift also demands a sufficiently high gate drive voltage to ensure that the GaN power transistor can be fully turned on, which reduces the safety margin for the gate reliability of the device. To design a GaN based power switching circuit, accurate simulation of the device/circuit characteristics is necessary. Circuit simulations that do not consider the dynamic V th lead to a large deviation from the measurement circuit characteristics. We demonstrate that by incorporating the dynamic V th into the circuit model this deviation can be effectively eliminated.

Improved 4H-SiC UMOSFET with super-junction shield region* *Project supported by the National Natural Science Foundation of China (Grant Nos. 61774052 and 61904045), the Youth Foundation of the Education Department of Jiangxi Province, China (Grant No. GJJ191154), and the Youth Foundation of Ping Xiang University, China (Grant No. 2018D0230).

This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor (MOSFET) (UMOSFET) fitted with a super-junction (SJ) shielded region. The modified structure is composed of two n-type conductive pillars, three p-type conductive pillars, an oxide trench under the gate, and a light n-type current spreading layer (NCSL) under the p-body. The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer, thus improving the specific on-resistance (R on,sp). There are three p-type pillars in the modified structure, with the p-type pillars on both sides playing the same role. The p-type conductive pillars relieve the electric field (E-field) in the corner of the trench bottom. Two-dimensional simulation (silvaco TCAD) indicates that R on,sp of the modified structure, and breakdown voltage (V BR) are improved by 22.2% and 21.1% respectively, while the maximum figure of merit () is improved by 79.0%. Furthermore, the improved structure achieves a light smaller low gate-to-drain charge (Q gd) and when compared with the conventional UMOSFET (conventional-UMOS), it displays great advantages for reducing the switching energy loss. These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance, which also enables the charge carriers to be extracted quickly. In the end, under the condition of the same total charge quantity, the simulation comparison of gate charge and OFF-state characteristics between Gauss-doped structure and uniform-doped structure shows that Gauss-doped structure increases the V BR of the device without degradation of dynamic performance.

Quantum Modelling of Nanoscale Silicon Gate-All-Around Field Effect Transistor

The paper introduces an analytical model for gate all around (GAA) or Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (SG-MOSFET) inclusive of quantum mechanical effects. The classical oxide capacitance is replaced by the capacitance incorporating quantum effects by including the centroid parameter. The quantum variant of inversion charge distribution function, inversion layer capacitance, drain current, and transconductance expressions are modeled by employing this model. The established analytical model results agree with the simulated results, verifying these models' validity and providing theoretical supports for designing and applying these novel devices.

Numerical simulation and parametric assessment of GaN buffered trench gate MOSFET for low power applications

This study presents numerical simulation of a novel gallium nitride buffered trench gate (GaN-BTG) metal oxide semiconductor field effect transistor (MOSFET) for high-speed and low-power applications. The electrical characteristics of GaN-BTG-MOSFET are compared with BTG MOSFET and conventional trench gate MOSFET. A comparative study of different performance factors such as electric field, electron velocity, threshold voltage (V th), electron mobility, and sub-threshold swing (SS) of these devices has been performed. Results reveal a 43.85% improvement in SS and 9.83% decrement in V th for GaN-BTG-MOSFET. Furthermore, the frequency analysis has been performed in terms of scattering (S) parameters, cut-off frequency (f T) and maximum oscillator frequency (f MAX) to show how the device is also suitable for radio frequency applications. Furthermore, the study of parametric variation of GaN-BTG-MOSFET with the change in channel length, oxide thickness (t ox), and doping concentration has also been presented. Results show that GaN-BTG-MOSFET can act as a promising structure for further scaling down of the trenched MOSFET and assures better performance for sub-20 nm trenched MOSFET.

Effect of Gate Engineering and Channel Length Variation in Surrounding Gate MOSFETs

In this paper, the digital and analog performance for Double Material Gate Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (DM SG MOSFET) has been analyzed. A detailed study of DM SG MOSFET is performed for different channel length ratio's. The comparison analysis on surface potential, electric field, transfer characteristics, output characteristics, transconductance and output conductance is carried with respect to the silicon dioxide and hafnium dioxide based device. It has been found from the simulation results that HfO2 dielectric used DM SG TFET provides better performance than SiO2 dielectric used DM SG TFET. Also it has been observed from the presented results that the transconductance is 45.32 at 1:3 channel length ratio for DG SG MOSFET.

Analysis of D.C Parameters of Short-Channel Heterostructure Double Gate Junction-Less MOSFET Circuits Considering Quantum Mechanical Effects

In this article, the electrical behavior of short channel SiGe Heterostructure Junction-Less DG-MOSFET have been studied by incorporating the quantum mechanical effect and short channel effects. Analytical model and simulation result shows how the device process parameters like gate oxide thickness, silicon thickness, channel doping concentration, channel or gate length etc. have an impact on the D.C parameters like threshold voltage, surface potential. DIBL and threshold voltage of the nanoscale JL-MOSFET are also analyzed by considering the QME to raise the accuracy of the derived models. Extensive simulations are performed in SILVACO ATLAS TCAD tool to validate the proposed models. It is quite evident that the derived models and simulation results are in good agreement for a wide variation of process parameters. Schrodinger model has been used in ATLAS simulation platform to validate the derived analytical model considering QME. However, comprehensive analysis of the short channel SiGe Hetero-structure Junction-Less Double Gate Metal Oxide Semiconductor Field Effect Transistor gives a better view and understanding of D.C characteristics of the device. At the end, D.C characteristics (power dissipation, propagation delay, power-delay product) of an inverter circuit has been taken under consideration to check the impact of QMEs on circuit performance.

Comparison of Strain Effect between Aluminum and Palladium Gated MOS Quantum Dot Systems

As nano-scale metal-oxide-semiconductor devices are cooled to temperatures below 1 K, detrimental effects due to unintentional dots become apparent. The reproducibility of the location of these unintentional dots suggests that there are other mechanisms in play, such as mechanical strains in the semiconductor introduced by metallic gates. Here, we investigate the formation of strain-induced dots on aluminum and palladium gated metal oxide semiconductor (MOS) quantum devices using COMSOL Multiphysics. Simulation results show that the strain effect on the electrochemical potential of the system can be minimized by replacing aluminum with palladium as the gate material and increasing the thickness of the gate oxide.

A high gain and high bandwidth three stage amplifier using FGMOS and 0.5 V dual supply

A novel CMOS transistor implementation of three stage amplifier is presented in this work. The floating gate metal oxide semiconductor (FGMOS) transistor current mirror is exploited here to minimize supply requirements and to overcome the bandwidth reduction due to FGMOS transistor, frequency compensation techniques have been applied in subsequent stages. This amplifier is useful for application of low-voltage low-power VLSI as it requires a dual supply of only ± 0.5 V. The power consumption is 0.157 mW and slew rate is 6.5 V/μs. The gain bandwidth product of the circuit is calculated as 59.1 MHz and dc gain is 111.5 dB. All simulations are carried out in 180 nm technology with spice tools.

Implementation of VLSI Architecture for Montgomery Modular Multiplier

The paper proposes a Montgomery Modular Multiplier (MMM) using a simple and efficient Montgomery multiplication algorithm. Here a modification in the form of using hybrid full adders in the Carry Save adder is proposed. The hybrid full adder is designed using a conventional Complementary Metal Oxide Semiconductor and transmission gate logic. There is about 54% and 55% reduction of area (no. of components) in Radix 2 MMM and Semi-Carry-Save (SCS) based MMM with hybrid full adders. There is significant reduction in the power dissipation of 52% for Radix 2 MMM and 46% of SCS based MMM when hybrid adders are used instead of C-CMOS Full-Adders. The delay is also reduced by 47% in SCS based MMM as compared to that of Radix 2 MMM. The software used are Xilinx ISE 14.2 and Mentor Graphics Pyxis Schematic in 180-nm technology.

Performance Analysis Of Double-Gate Carbon-Nanotube FET And MOSFET For High Speed Integrated Circuits Design

This paper explains the detailed structure as well as performance of DG-CNTFET (Double Gate Carbon Nanotube Field Effect Transistor) and its performance is compared with the DG-MOSFET (Double Gate Metal Oxide Semiconductor Field Effect Transistor). Various parameters like I-V characteristics, ON current, OFF current and ON to OFF current ratio have been evaluated using nano-TCAD ViDES. Also, the transport description of DG-MOSFET and DG-CNTFET has been described in detail. It has been observed that DG-CNTFET has lower OFF current and higher ON current in comparison to the DG-MOSFET. The higher ON current of DG-CNTFET depicts that it requires less time to turn on the device in comparison with DG-MOSFET. Also, OFF current of the DG-CNTFET is lesser as compared to MOSFET. The DG-CNTFET’s higher ON to OFF current ratio outperforms the DG-MOSFET in term of switching speed of the device. It is proposed that CNTFET can be used as an alternative of MOSFETs for high speed Integrated Circuit (IC) design.