Gate Voltage Shift Research Articles

Charge trapping properties in thin oxynitride gate dielectrics prepared by rapid thermal processing

In this letter, effects of post-nitridation anneals on charge trapping properties and charge-to-breakdown (Qbd) of thin (∼8.6 nm) rapidly thermal nitrided (RTN) gate SiO2 have been studied. Post-nitridation anneals consist of either rapid thermal reoxidation (RTO) in pure O2 or rapid thermal anneal (RTA) in pure N2 ambient. Both the gate voltage shift (ΔVg) and flatband voltage shift (ΔVfb) have been used to characterize the charge trapping properties under Fowler–Nordheim electron injection. It is found that both RTO and RTA reduce ΔVfb and/or ΔVg resulting from the reduction of trapped electrons as well as high-field stress-induced positive charge generation. Positive charge generation resulting from either donor-type interface state generation or trapped holes is discussed. Qbd of RTN SiO2 has been improved after RTO, and can be even larger than that of the thermal SiO2. RTA of RTN SiO2 in N2 also improves Qbd; however, the charge trapping behavior is different from that of RTO/RTN SiO2. The physical mechanism is discussed to account for the observation.

Effects of rapid thermal oxidation on electrical characteristics of chemical-vapor-deposited SiO2 gate dielectrics

In this paper, effects of rapid thermal oxidation (RTO) on electrical characteristics of thin (200 Å) chemical-vapor-deposited (CVD) SiO2 have been studied. Current density-electric field (J-E) characteristics, flat-band voltage, and gate voltage shifts under constant-current stressing were also examined. Results show that RTO improves the charge trapping property of as-deposited CVD oxides. In addition, RTO of CVD oxides also increases the electron injection barrier height of the as-deposited samples at the cathode and produces devices with lower leakage current and tighter breakdown distribution.

Thermal reemission of trapped electrons in SiO2

Electron trapping by neutral trap centers in SiO2 was studied at 77 K and at room temperature, using n-channel silicon-gate IGFET structures. The electrons were injected in the dark using the forward-bias pulsed injection method. The results show that electron trapping by the neutral centers was one to two orders of magnitude more efficient at 77 K than at room temperature; which may be compared with the previously reported electron trapping by Coulomb-attractive centers where the capture cross sections at room temperature and at 77 K were about the same. For injected electron concentrations of less than 1016 cm−2, more than 90% of the electron trapping at 77 K was due to shallow-level centers where the captured electrons were thermally reemitted as the samples were warmed to room temperature. The concentrations of these shallow-level traps in dry, wet, and HCl oxides were about the same, regardless of whether the aluminum evaporation was by electron-beam or by rf heating in a tantalum boat. The capture cross section of these traps at 77 K was estimated to be about 10−15 cm2 at Eox=1×106 V/cm, decreasing slowly with increases in the oxide field. Thermally stimulated reemission measurements were made by monitoring the gate voltage shifts at constant channel conductance. Analyses of the results indicated a broad energy distribution for these shallow-level traps, with a peak at 300±50 meV below the conduction-band edge of SiO2 and a half-width of about 200 meV. A small portion of the enhanced trapping at 77 K was attributable to deep-level centers where the captured electrons were not thermally reemitted at room temperature.

Determination of surface state density from gm − VG characteristics of MOSFETs

The g m - V g characteristics of a MOSFET measured at the room temperature in the transition region between the normal and the low level current regions are compared with the theoretical curve to obtain the surface state density, ρ SS , within a small surface potential interval near the threshold voltage. It is further shown theoretically that the peak value of g m , g m0 , reduces against the increase of ρ SS by the factor 1/(1 + αρ SS ) where α is a constant, and good agreement is obtained between theory and experiment by using the devices in which surface states are produced by the RF sputter coating with SiO 2. The gate voltage corresponding to g m0 or g m0 10 is shown to be linearly dependent on ρ SS , but the gate voltage shift is considerably small at the lower current level, indicating the surface state density increasing sharply towards the valence band edge.

Threshold shift calculations for ion implanted MOS devices

The solutions of Poisson's equation applicable to ion implanted MOS devices have been used to generate capacitance-voltage relationships for capacitors and threshold voltage shifts for transistors. The calculations agree well with previously published transistor data for profiles centered near Si-SiO 2 interface. These shallow implants (< 0.1 μm) are easily controlled by the gate and yield voltage shifts equal to that expected for all of the charge lumped at the silicon surface. In addition, the observed saturation of gate voltage shift for deeper implants in enhancement mode transistors can be duplicated by the calculations provided that the stopping power of SiO 2 is reduced as has been proposed elsewhere. Further, it has been predicted that gate control will be lost for depletion mode transistors with sufficiently deep implants. This is caused by the formation of a deep channel which is isolated from gate control by an induced surface charge layer. The inability of the gate field to pinch off the channel defeats device use for transistor inverter loads.