Gate Voltage Condition Research Articles

Study on memory characteristics of fin-shaped feedback field effect transistor

The nonvolatile and volatile memory characteristics of feedback field-effect transistors (FBFETs) with nitride charge storage layers were theoretically studied. Because of the electrons and holes stored in the nitride layer, the threshold voltage (V TH) window of 0.6 V was opened/observed. And, with the help of the formation of a positive feedback loop in the p+–n+–p–n+ doped silicon region in FBFET, it turned out that the read delay time of the FBFET for nonvolatile memory applications can be shorter than 1 ns. On the other hand, for the volatile memory applications, the FBFET can implement (a) non-destructive read operations owing to the self-sustaining feedback loop characteristic, and (b) a significantly long retention time which can suppress the power dissipation in refresh. Furthermore, the operation scheme of volatile memory mode can be simplified by setting gate voltage conditions for the hold and read operations to be identical to each other. The FBFET showed its on-state drive current of 6 × 10−5 A μm−1 and the on-/off-current ratio of 109. The potential of merging nonvolatile and volatile memory devices in a single cell is discussed and demonstrated in this work.

Analog synaptic behavior of mobile ion source-limited electrochemical RAM using CuOx oxide electrode for deep learning accelerator

We demonstrate the synaptic characteristics of analogously modulated channel currents in Cu-ion-actuated electrochemical RAM (ECRAM) based on an HfOx electrolyte and a WOx channel. Uncontrolled synaptic response is found as a function of the gate pulse when a Cu-rich gate electrode delivers mobile ions, presumably due to many ions injected from the infinite ion reservoir. As a result, we propose a CuOx oxide electrode to limit ion sources, which is indirectly validated by a physical examination of the degree of chemical bonding between Cu and oxygen, thereby boosting gate controllability over the channel. In addition, the HfOx electrolyte needs to be designed to facilitate the adequate migration of Cu ions, considering thickness and film quality. Using material stack engineering, the channel current of optimized CuOx/HfOx/WOx ECRAM can be steadily tuned via repeated identical gate pulses. The channel current and its change are proportional to the device area and the amount of migrated ions relevant to the gate pulse conditions, respectively. The homogeneous flow of ions across the entire area can, thus, be used to explain the obtained analog switching. The gate-controllable synaptic behavior of the ECRAM accelerates deep neural network training based on backpropagation algorithms. An improved pattern recognition accuracy of ∼88% for handwritten digits is achieved by linearly tuned multiple current states with more than 100 pulses and asymmetric gate voltage conditions in a three-layer neural network validated in simulation.

Electrical performances degradations and physics based mechanisms under negative bias temperature instability stress for p-GaN gate high electron mobility transistors

In this paper, an in-depth evaluation of the negative bias temperature instability (NBTI) in p-GaN gate high electron mobility transistors with Schottky-type gate contact has been reported in detail. The measured results reveal that the threshold voltage (V th) positively shifts by 0.35 V and the on-state drain-source resistance (R dson) increases by 24.2 mΩ within 1 h at room temperature, even under the minimum allowed operating gate-voltage condition (V gs = −10 V) in the datasheet of the commercial device. With the help of energy band theory and experimental analyses, donor-type traps are demonstrated to dominate the degradation by reducing the positive charges in the p-GaN cap. Moreover, further quantitative analysis has been performed by the conductance–frequency measurements method. Considering the risk of degradation induced by NBTI, it turns necessary for the system designers to choose a more suitable negative bias operating condition so as to extend the robustness of the entire power system.

The Effect of Hydrophobin Protein on Conductive Properties of Carbon Nanotube Field-Effect Transistors: First Study on Sensing Mechanism.

Hydrophobin is a surface active protein having both hydrophobic and hydrophilic functional domains which has previously been used for functionalization and solubilization of graphene and carbon nanotubes. In this work, field-effect transistors based on single nanotubes have been employed for electronic detection of hydrophobin protein in phosphate buffer solution. Individual nanotubes, single- and multiwalled, are characterized by atomic force microscopy after being immersed in protein solution, showing a relatively dense coverage with hydrophobin. We have studied aspects such as nanotube length (0.3-1.2 µm) and the hysteresis effect in the gate voltage dependent conduction. When measured in ambient condition after the exposure to hydrophobin, the resistance increase has a strong dependence on the nanotube length, which we ascribe to mobility degradation and localization effects. The change could be exceptionally large when measured in-situ in solution and at suitable gate voltage conditions, which is shown to relate to the different mechanism behind the hysteresis effect.

Analysis and modeling of the gate leakage current in advanced nMOSFET devices with severe gate-to-drain dielectric breakdown

The gate leakage current in advanced metal gate/high-K (EOT≈0.6nm) nMOSFETs with severe gate-to-drain dielectric breakdown is investigated in detail. Even though several models have been proposed in the past to deal with this issue, they are mainly intended to be used in circuit simulation environments. On the contrary, we report in this work an analytic expression for the gate current based on the solution of the generalized diode equation. The model has been tested not only for positive drain and gate voltage conditions but also for negative biases.

Influence of Embedded a-Si:H Layer Location on Floating-gate a-Si:H TFT Memory Functions

AbstractThe influence of the location of the embedded a-Si:H layer in the gate dielectric film of the floating-gate a-Si:H TFT on the charge trapping and detrapping mechanisms has been investigated. The thin channel-contact SiNx gate dielectric layer favors both hole and electron trappings under the proper gate voltage condition. The sweep gate voltage affect the locations and shapes of forward and backward transfer characteristics curves, which determines the memory function. In order to achieve a large memory window, both the location of the embedded a-Si:H layer and the gate voltage sweep range need to be optimized.

An organic nonvolatile memory using space charge polarization of a gate dielectric

We realize a nonvolatile and rewritable memory effect in an organic field-effect transistor (OFET) structure using polymethylmethacryrate (PMMA) dispersed with 10-methyl-9-phenylacridinium perchlorate (MPA +ClO 4 −) as a gate dielectric. Applying a voltage between a top source-drain electrode and a bottom gate electrode induces electrophoresis of two ions of MPA + and ClO 4 − towards the corresponding electrodes in the memory devices. The drain currents of the memory devices markedly increase from 10 − 9 A to 10 − 2 A under no gate voltage condition due to the strong space charge polarization effect. Our memory devices have excellent electrical bistability and retention characteristics, i.e. the memory on/off ratio reached 10 7 and the drain current maintained 40% of the initial value after 10 4 s.

A Ferroelectric Gate Field Effect Transistor with a ZnO/Pb(Zr,Ti)O3 Heterostructure Formed on a Silicon Substrate

We have developed a ferroelectric gate field effect transistor (FeFET) with a stacked oxide structure of ZnO/Pb(Zr,Ti)O3 (PZT)/SrRuO3 (SRO) on a Pt/SiO2-coated silicon substrate. The PZT film which acted as a ferroelectric gate insulator was completely oriented in the (111) direction. The well oriented PZT film was realized by the insertion of the SRO layer, which electrically acted, together with the bottom Pt layer as a bottom gate electrode. In order to realize a sharp heterointerface of ZnO/PZT, we applied chemical–mechanical-polishing (CMP) to the PZT surface giving rise to a minimized surface roughness of less than 0.65 nm (rms). The ZnO film stacked on the smooth PZT surface exhibited a c-axis orientation. Subsequently, the source and drain electrodes of Pt/Ti were formed on the ZnO surface. With a drain-to-source voltage of 0.1 V, the conduction current through the ZnO/PZT heterointerface was characterized. A large on/off current ratio (Ion/Ioff) higher than 105 was obtained between the gate voltage conditions of +10 and -10 V owing to the polarization reversal of the PZT gate. Notably, the on/off ratio was stable for more than 105 s without the application of gate bias.

Effects of nitrogen-incorporated interface layer on the transient characteristics of hafnium oxide n-metal–oxide–semiconductor field-effect transistors

In this letter, we present the effects of the nitrogen-incorporated interface on threshold voltage shift (ΔVth), which was induced by charge trapping and detrapping in hafnium oxide (HfO2) n-metal–oxide–semiconductor field-effect transistors. Under the various gate voltage conditions, the nitrogen-incorporated interface showed a smaller ratio of interface charge density to total charge density (Nit∕Ntotal) due to its thinner interface thickness and lower energy band offset. In addition, the degradations of the interface quality and the mobility under the stress condition were less severe for the nitrogen-incorporated interface devices.

New understanding of LDD NMOS hot-carrier degradation and device lifetime at cryogenic temperatures

This work shows that the worst-case gate voltage stress condition for LDD nMOSFETs is a strong function of the channel length, drain voltage, and operating temperature. A new cross-over behavior of the worst-case gate voltage condition is reported at low temperatures. New understanding of the hot-carrier mechanisms at low temperatures is also discussed. Low temperature effects such as freeze-out are shown to have important contributions to the hot-carrier behavior at low temperatures. A trend is identified for the first time which suggests important consequences for the hot-carrier reliability of deep sub-micron channel length MOSFETs under normal operating temperatures.

The generation and characterization of electron and hole traps created by hole injection during low gate voltage hot-carrier stressing of n-MOS transistors

Hot-carrier stressing carried out on conventional and MDD n-MOS transistors under low gate voltage conditions (V/sub g/<or=V/sub d//4) is discussed. Following the stress, the devices were subjected to short alternate phases of electron and hole injection into the oxide in order to identify the damage species generated. It is shown that the damage created consists principally of hole and electron oxide traps. This is confirmed using the charge pumping technique. Maximum damage is obtained for conditions of maximum hole injection, indicating that hot holes are responsible for both types of defects. Comparison with maximum interface state damage shows that degradation due to electron traps can be significantly greater than interface state creation in the stressing of n-MOS devices at high drain voltages. The damage is shown to be localized. Two-dimensional simulation of localized charge placed close to the drain junction suggests that equal quantities of positive and negative charge might be created by this stressing. Measurements of capture cross sections for electron trapping reveal two cross sections, sigma (1) approximately=3*10/sup -15/ and sigma (2) approximately=3*10/sup -16/ cm/sup 2/.<<ETX>>

Interfacial Dopants for Dual-Dielectric, Charge-Storage Cells

When a suitable interfacial dopant, such as W, is introduced at the interface between the dielectrics of a DDC cell, the write-erase characteristics of the cell are greatly improved. The useful range of the dopant concentration is determined to lie between about 1014 to 1015 atoms/cm2. The interfacial dopant allows the fabrication of a DDC cell with relatively thick SiO 2 layers (> 50 A). The result is a substantially permanent memory cell that can still be subjected to electrical write-erase at reasonable gate-voltage conditions.