Gate Stack MOSFET Research Articles

Study of DC and Analog/RF Performances Analysis of Short Channel Surrounded Gate Junctionless Graded Channel Gate Stack MOSFET

Study of DC and Analog/RF Performances Analysis of Short Channel Surrounded Gate Junctionless Graded Channel Gate Stack MOSFET

Exploring the Threshold Voltage Characteristics and Short Channel Behavior of Gate Engineered Front Gate Stack MOSFET with Graded Channel

The present work focuses on formulating a detailed two dimensional analytical model of the proposed Triple Metal Stacked Front Gate Oxide Double Gate MOSFET with step graded channel (GC-TMDG MOSFET) incorporating the dual benefits of gate and channel engineering techniques. Proper choice of a lower work function metal and lower channel doping concentration near the drain end serves the purpose of suppressing the unwanted impact ionization induced Hot Carrier Effects (HCEs) at the drain side of a nano-dimensional device, thereby making it a suitable ultra low dimensional device for future nano generation. The results obtained from analytical modeling depict a detailed comparative analysis of the proposed GC-TMDG MOSFET with its graded channel DG MOSFET counterpart to substantiate the improved performance of the proposed device in terms of surface potential, electric field, threshold voltage roll off, Drain Induced Barrier Lowering and drain current behavior. The analytical results are found to be in good agreement with 2D ATLAS simulator data, thereby validating our analytical model.

(Invited) Past, Present, and Future of High-k/Metal Gate Technologies

The SiO2 based gate insulator and poly Si gate electrode had been used almost 4o years for (C)MOS integrated circuits from 1970 to 2010 because of their extraordinary good properties of both the interfaces at the substrate and gate electrode. Thus, most of the people had not believed the replacement of SiO2/poly Si gate stack by that of high-k/metal in the products would be impossible, although the demand to introduce the high-k gate oxide became stronger due to the high tunneling gate leakage current when decreasing the gate oxide thickness with the scaling. However, the operation of high k/metal gate stack MOSFETs were demonstrated by several different organizations at the same time at IEDM 1999. Since then, many R & D organizations seriously participated to the research and development of high-k/metal gate stack for MOSFETs. It was in 2001, when Prof. Samares Kar proposed to create an ECS symposium on “Physics and Technology of High-k Gate Dielectrics”. Then, the 1st symposium was held in Salt Lake City, Utah, U.S.A. on October 20-14, 2002. At that time total number of the presentations at the symposium was 34. The, number increased to 56 in the 2nd symposium in Cancun, Mexico, 2003, and 75, in the 3rd symposium in Los Angeles, in 2006, and so on. In 2007, Intel introduces HfO2 based high-kmaterial for the 1st time into their product. Later, the symposium was renamed with Semiconductors, dielectrics and metals for Nanoelectronics and still continues and contributed to give opportunities to the researchers and engineers for the paper presentation and discussion. Prof. Samares Kar has been the leading organizer of the symposium, maintaining rigorous standards to make the symposium one of the most successful in ECS. However, it was very sad that Prof. Samares Kar passed away on January 13, 2017 at his home in Kolkata, India. We would like to express our sincere appreciation for the hard work and rigorous drive towards the advancement of the symposium by giving presentations for the past, present and future of high-k stack technologies.

Gate current modelling through high-k gate stack MOSFET for very-large-scale integration logic circuit analysis

In this paper, we present a computationally efficient model for gate tunnelling current through different high-k gate dielectrics stack structures by adjusting two fitting parameters. The proposed model can be used in circuit simulator due to its simplicity in implementation. Various materials of high-k gate dielectrics stack have been examined and compared to analyse the reduction of gate leakage current by considering the effects of interfacial oxide thickness, type of gate stack, on current, off current, drain induced barrier lowering and sub-threshold slope. Consequently an optimised high-k gate dielectrics stack structure is proposed and used to analyse the gate leakage current in CMOS (complementary metal oxide semiconductor) based universal logic gates. The results obtained have been verified with Sentaurus simulation for the purpose of validation.

Gate Current Modelling through High-K Gate Stack MOSFET for Very-Large-Scale Integration Logic Circuit Analysis

In this paper, we present a computationally efficient model for gate tunnelling current through different high-k gate dielectrics stack structures by adjusting two fitting parameters. The proposed model can be used in circuit simulator due to its simplicity in implementation. Various materials of high-k gate dielectrics stack have been examined and compared to analyse the reduction of gate leakage current by considering the effects of interfacial oxide thickness, type of gate stack, on current, off current, drain induced barrier lowering and sub-threshold slope. Consequently an optimised high-k gate dielectrics stack structure is proposed and used to analyse the gate leakage current in CMOS (complementary metal oxide semiconductor) based universal logic gates. The results obtained have been verified with Sentaurus simulation for the purpose of validation.

Identification of electron trap location degrading low-frequency noise and PBTI in poly-Si/HfO 2/interface-layer gate-stack MOSFETs

Identification of electron trap location in HfO 2/interface-layer (IFL) of poly-Si/TiN/HfO 2/SiO 2 gate-stacked MOSFETs is successfully demonstrated through analysis of low-frequency noise and PBTI characteristics with respect to nitrogen incorporation into the gate dielectrics in fabrication process. It is found that the electron trap existing in the bulk-IFL dominantly degrades low-frequency noise (LFN) and positive bias temperature instability (PBTI). The pre-existing electron trap is considered to be generated by N incorporation into the IFL in the fabrication process of gate-first process.

Gate Current Modeling and Optimization of High-k Gate Stack MOSFET Structure in Nano Scale Regime

In this paper, an analytical model has been developed for gate tunneling current in nano scale MOSFET with high-k dielectric stack as gate insulator. A computationally efficient model for gate tunneling current through different high-k gate stack structure is presented. The proposed model has been successfully used for different gate stack dielectric simply by adjusting two fitting parameters. The model predictions are compared with the two-dimensional Santaurus device simulation. Good agreement between the model predictions and device simulation results has been obtained. The effects of interfacial oxide thickness, type of gate stack and reverse gate stack on the gate tunneling current have also been studied as a function of gate voltages for a given equivalent oxide thickness (EOT) of 1.0 nm. It was also shown that smaller inter oxide layer thickness reduces gate leakages current with the introduction of high-k gate stack structure in place of individual high-k dielectric or SiO2.

Carrier transport mechanism in La-incorporated high- k dielectric/metal gate stack MOSFETs

In this paper, carrier transport mechanism of MOSFETs with HfLaSiON was analyzed. It was shown that gate current is consisted of Schottky emission, Frenkel–Poole (F–P) emission and Fowler–Nordheim (F–N) tunneling components. Schottky barrier height is calculated to be 0.829 eV from Schottky emission model. Fowler–Nordheim tunneling barrier height was 0.941 eV at high electric field regions and the trap energy level extracted using Frenkel–Poole emission model was 0.907 eV. From the deviation of weak temperature dependence for gate leakage current at low electric field region, TAT mechanism is also considered.

Analysis of Remote Coulomb Scattering Limited Mobility in MOSFET with CeO2/La2O3 Gate Stacks

Remote Coulomb Scattering (RCS) limited mobility in CeO2 capped La2O3 high-k MOSFETs was studied. The RCS mobility was calculated by quantum mechanical calculations. Experimental mobility data has been measured from nMOSFETs with ultrathin gate oxide with thickness of 1.5nm, and has been compared to the calculated RCS mobility. The result shows that the mobility degradation in CeO2 / La2O3 gate stack MOSFETs might be due to the RCS.

A low-frequency noise model for advanced gate-stack MOSFETs

A new unified noise model is presented that accurately predicts the low-frequency noise spectrum exhibited by MOSFETs with high dielectric constant (high- k), multi-stack gate dielectrics. The proposed multi-stack unified noise (MSUN) model is based on number and correlated mobility fluctuations theory developed for native oxide MOSFETs, and offers scalability with respect to the high- k/interfacial layer thicknesses. In addition, it incorporates the various electronic properties of high- k/interfacial layer materials such as energy barrier heights between different gate layers, and dielectric trap density with respect to band energy and position in the dielectric. For verification of the new model, the low-frequency noise, DC and conventional split C–V measurements were performed in the 78–350 K temperature range on TaSiN/HfO 2 n-channel MOSFETs. The interfacial layer in these devices was either thermal SiO 2 by Stress Relieved Pre-Oxide (SRPO) pretreatment or chemical SiO 2 resulting from standard RCA (Radio Corporation of America) clean process. Using the experimental noise data, the channel carrier number fluctuations mechanism was at first established to be the underlying mechanism responsible for the noise observed at all temperatures considered. Secondly, the normalized noise exhibited a weak dependence on temperature implying that the soft optical phonons, although known to result in mobility degradation, have no effect on the noise characteristics in these high- k gate stack MOSFETs. Finally, the new model was shown to be in excellent agreement with the measured noise in 1–100 Hz frequency range at temperatures of 78–350 K for both gate stacks.

Hot-Carrier Reliability and Analog Performance Investigation of DMG-ISEGaS MOSFET

Dual-material-gate (DMG) insulated shallow extension gate-stack MOSFET involving dielectric pocket (DP) and DMG assimilation onto the conventional MOSFET has been studied. Simulations reveal a reduction in substrate leakage current, linearity improvement, enhancement in - g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> , early voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EA</sub> ), and g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> , down to 50-nm gate length as an outcome of this DP and DMG integration.

Analysis of the post-breakdown current in HfO 2/TaN/TiN gate stack MOSFETs for low applied biases

A thorough analysis of the post-breakdown current-voltage characteristics in HfO 2high- κ/TaN/TiN gate stacks for low positive applied biases reveals an apparent band gap narrowing of the silicon substrate at the very location of the leakage site. This effect may be caused by the migration of gate material through the percolation path during the breakdown runaway. Additionally, the voltage dependence of the current suggests that the origin of the leakage current is thermal generation within the depletion region close to the breakdown spot. A simple analytical model to deal with this current is proposed.

Impact of Polarons on the Mobility of Non-Ideal Metal/High-k Gate Stack MOSFETs

not Available.

Nano-characterisation of dielectric breakdown in the various advanced gate stack MOSFETs

Nano-scale physical analysis of breakdown in nano-scale high-κ gate stacks consisting of either polycrystalline-silicon or metal as gate electrode shows that the microstructural defects and damages induced by breakdown in the high-κ gate dielectric are different from that of conventional SiOxNy/poly-Si and Si3N4/poly-Si gate stacks. Chemical analysis using transmission electron microscopy provides useful information about the nature and evolution of the breakdown induced defects in different gate stacks metal-oxide-semiconductor field effect transistors. Together with electrical characterisation, the possible gate leakage conduction mechanism(s) in various dielectric breakdown has been established. This paper reviews the breakdown conduction mechanism(s) and induced defects in high-κ gate stacks in comparison to conventional gate dielectrics. The impacts of the new failure mechanisms on the performance and reliability of various gate stacks are discussed.