Gate Oxide Materials Research Articles

Effects of insertion of an h-AlN monolayer spacer in Pt-WSe2-Pt field-effect transistors

The growth of two-dimensional hexagonal aluminum nitride (h-AlN) on transition metal dichalcogenide (TMD) monolayers exhibits superior uniformity and smoothness compared to HfO2\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$_{2}$$\\end{document} on silicon substrate. This makes an h-AlN monolayer an ideal spacer between the gate oxide material and the WSe2 monolayer in a two-dimensional field effect transistor (FET). From first principles approaches, we calculate and compare the transmission functions and current densities of Pt–WSe2–Pt nanojunctions without and with the insertion of an h-AlN monolayer as a spacer in the gate architecture. The inclusion of h-AlN can alter the characteristics of the Pt–WSe2–Pt FET in response to the gate voltage (Vg\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$V_\ ext {g}$$\\end{document}). The FET without (or with) h-AlN exhibits the characteristics of a P-type (or bipolar) transistor: an on/off ratio of around 2.5×106\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$2.5 \ imes 10^{6}$$\\end{document} (or 1.7×106\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$1.7 \ imes 10^{6}$$\\end{document}); and an average subthreshold swing (S.S.) of approximately 109 mV/dec.\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ ext {dec.}$$\\end{document} (or 112 mV/dec.\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\ ext {dec.}$$\\end{document}), respectively. We observe that Vg\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$V_\ ext {g}$$\\end{document} shifts the profile of the transmission function by an energy of α(eVg)\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\alpha (e V_{\ ext {g}})$$\\end{document}, where α\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\alpha$$\\end{document} represents the gate-controlling efficiency. We observed that αin=83%\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\alpha _{\ ext {in}}=83\\%$$\\end{document} and αout=33%\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\alpha _{\ ext {out}}=33\\%$$\\end{document}, corresponding to whether the Fermi energy is located inside or outside the band gap. Therefore, we construct an effective gate model based on the Landauer formula, with the transmission function at Vg=0\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$V_\ ext {g}=0$$\\end{document} as the baseline. Our model generates results that are consistent with those obtained through first principles calculations. The relative error in current densities between model and first-principles calculations is within [ln(10)S.S.]|ΔVGeff|\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$[\\frac{ln(10)}{S.S.}] | \\Delta V_{\ ext {G}}^{\ ext {eff}} |$$\\end{document}. The 2D atomistic FETs show excellent device specifications and the ability to compete with existing transistors based on traditional silicon technology. Our findings could help advance the design of TMD-based FETs.

Parametric Analysis of Indium Gallium Arsenide Wafer-based Thin Body (5 nm) Double-gate MOSFETs for Hybrid RF Applications.

The electrical behavior of a high-performance Indium Gallium Arsenide (In- GaAs) wafer-based n-type Double-Gate (DG) MOSFET with a gate length (LG1= LG2) of 2 nm was analyzed. The relationship of channel length, gate length, top and bottom gate oxide layer thickness, a gate oxide material, and the rectangular wafer with upgraded structural characteristics and the parameters, such as switch current ratio (ION/IOFF) and transconductance (Gm) was analyzed for hybrid RF applications. This work was carried out at 300 K utilizing a Non-Equilibrium Green Function (NEGF) mechanism for the proposed DG MOSFET architecture with La2O3 (EOT=1 nm) as gate dielectric oxide and source-drain device length (LSD) of 45 nm. It resulted in a maximum drain current (IDmax) of 4.52 mA, where the drain-source voltage (VDS) varied between 0 V and 0.5 V at the fixed gate to source voltage (VGS) = 0.5 V. The ON current(ION), leakage current (IOFF), and (ION/IOFF) switching current ratios of 1.56 mA, 8.49Í10-6 μA, and 18.3Í107 μA were obtained when the gate to source voltage (VGS) varied between 0 and 0.5 V at fixed drain-source voltage (VDS)=0.5V. The simulated result showed the values of maximum current density (Jmax), one and twodimensional electron density (N1D and N2D), electron mobility (μn), transconductance (Gm), and Subthreshold Slope (SS) are 52.4 μA/m2, 3.6Í107 cm-1, 11.36Í1012 cm-2, 1417 cm2V-1S-1, 3140 μS/μm, and 178 mV/dec, respectively. The Fermi-Dirac statistics were employed to limit the charge distribution of holes and electrons at a semiconductor-insulator interface. The flat-band voltage (VFB) of - 0.45 V for the fixed threshold voltage greatly impacted the breakdown voltage. The results were obtained by applying carriers to the channels with the (001) axis perpendicular to the gate oxide. The sub-band energy profile and electron density were well implemented and derived using the Non-Equilibrium Green's Function (NEGF) formalism. Further, a few advantages of the proposed heterostructure-based DG MOSFET structure over the other structures were observed. This proposed patent design, with a reduction in the leakage current characteristics, is mainly suitable for advanced Silicon-based solid-state CMOS devices, Microelectronics, Nanotechnologies, and future-generation device applications.

Fabrication and characterization of HfxAl(1-x)Oy ceramic targets and thin films by RF sputtering

The potential of HfO2 as a memory semiconductor material with ferroelectric properties in thin-film deposition has been recently analyzed. In this study, the preparation, composition, and physical properties of Al-doped hafnium oxides were analyzed. HfxAl(1-x)Oy (HAO) [x = 0.33, 0.5, and 0.67] powders were prepared by controlling the ratio of Hf to Al and using ball milling. The HAO powder was calcined at 1000 °C in a furnace and then sintered in a temperature range of 1000–1600 °C by a solid-state reaction method to fabricate high-quality targets with high densities. The density and crystal size increased with the sintering temperature. The 1600-°C Hf0.67Al0.33Oy target was optimal for thin-film deposition. In addition, the target properties were affected by an increase in the HfO2 content x. The crystal structures and sizes, surface free energies, contact angles, and band gaps of the HAOs were evaluated to analyze their potential as high-k dielectric materials. HAO is a promising high-k dielectric and memory material, valuable for further studies on ferroelectric gate oxide materials. This study contributes to the increasing number of studies on the ferroelectricity of HfO2 thin films and provides a fundamental understanding of this material and its potential for novel device applications.

Oppositely-Doped Core-Shell Junctionless Nanowire FET: Design and Investigation

Junctionless Nanowire Field Effect Transistor (JL-NWFET) has garnered significant attention in recent years owing to its simplified fabrication process, achieved through uniform doping across the device. However, JL-NWFET suffers from certain drawbacks, including low drive current, insufficient volume depletion, and lateral band-to-band tunneling. To address these issues, this paper proposes Improved JL-NWFET with an oppositely doped core–shell structure along with a Dual Material gate (DMG) and high-k spacer. Furthermore, Improved JL-NWFET is optimized for parameters such as core thickness, gate oxide material, spacer material, and spacer length. The performance of Improved JL-NWFET is also evaluated in comparison with other structural variants of JL-NWFET. Notably, Improved JL-NWFET showcases an enhancement of 23.1% and 20% in ON-state current (I ON ) and transconductance (g m ), respectively when compared to the conventional JL-NWFET. Furthermore, the Subthreshold Slope (SS) experiences an 88% improvement in the Improved JL-NWFET as opposed to the JL-NWFET. Additionally, the OFF-state leakage current (I OFF ) undergoes a fivefold reduction, leading to a sixfold increase in the I ON /I OFF ratio compared to the JL-NWFET. Among all the variants of JL-NWFET devices analyzed in this paper, Improved JL-NWFET stands out with its exceptional performance characteristics.

Impact of Nanowire Radius and Channel Thickness with High-k Gate Dielectric in GAA-JLT

As the transistor’s size becomes smaller, degradation in the short-channel effects (SCEs) becomes more apparent. This leads to research work on multi-gate transistors such as the Fin-Field Effect Transistor (FinFET) and Gate-All-Around (GAA) transistor, where the 3D architecture have been shown to have superior performance as compared to conventional planar transistor. Transistor without junctions (JLT) which realizes a single type of doping has also been gaining popularity for biosensor applications due to its superior electrostatic performances in terms of Drain-Induced Barrier Lowering (DIBL), off-state leakage current (Ioff) and Subthreshold Slope (SS). In this work, the impact of changes in parameters such as the gate oxide material, nanowire radius and channel thickness toward the performance of a Gate-all-around JLT (GAA-JLT) have been studied using TCAD simulator. It was found that smaller nanowire radius and thicker channel produces lower DIBL, Ioff and SS, with the use of HfO2 as gate oxide materials shows better results than Si3N4. Meanwhile, the impact of parameters variations seemed to be negligible on the on-state current (Ion). The outcome of this work can be used as a basis to understand the impact of structural parameters variations towards the performance of a more complex GAA-JLT structure.

New Materials for Memory Applications by Atomic Layer Deposition

The architectures of integrated logic and memory devices have shifted from 2D to 3D layouts, enabling a continued scaling of device densities. Atomic layer deposition (ALD) allows the conformal deposition of thin films with sub-nm thickness control on high aspect ratio 3D structures. ALD has become the technique of choice for the synthesis of an increasing number of materials in advanced logic and memory devices. In the first part of this presentation, we briefly review some of the key ALD processes which enable the fabrication of state-of-the-art 3D-NAND and 2D-DRAM. Next, we present the ALD of emerging ferroelectric HfZrO developed at ASM in industrial scale ALD reactors. HfO2 has been established as the preferred gate oxide material for logic devices for almost two decades. The recent discovery of ferroelectricity in HfO2 has opened new applications for HfO2-based materials as active memory elements in DRAM and 3D-NAND. We show that ALD La:HfZrO can achieve high polarization field (2Pr > 60 uC/cm2) and high endurance (> 107 cycle) by applying interface engineering schemes and optimizing deposition processes and film composition (i.e. Hf/Zr ratio, dopant concentration).

Designing and Reliability Analysis of Radiation Hardened Stacked Gate Junctionless FinFET and CMOS Inverter

Along with radiation sensing, necessity to study and design reliable radiation hardened devices is also increasing now-a-days. These devices are tolerant to high dosage of radiations without causing any physical damage, logic damage or data loss. In the current work, stacked gate Junctionless FinFET (SG JL FinFET) is analyzed as radiation hardened device by studying the impact of radiation of Linear Energy Transfer (LET) values ranging from 2MeV.cm/mg to 10MeV.cm/mg on the device performance. The proposed radiation hardened FinFET is experimentally calibrated with pre and post irradiation data. Single event upset (SEU) study using transient analysis is carried out to study the performance of proposed radiation hardened device at microwave frequency. High-k material-hafnium dioxide is used as gate oxide material to improve radiation hardness of SG JL FinFET. Electrical parameters-drain current, surface potential and SEU generation rate are studied to analyze device characteristics. Optimization of gate oxide, doping concentration, gate metals and temperature is carried out to enhance the reliability of device in terms of radiation hardness. SG JL FinFET is exposed to different types of waves-UV rays, X-ray, and Gamma rays to study the response of device at different frequencies. The comparison of SG JL and SG Inversion Mode (IM) FinFET has been performed. Comparison of SG JL FinFET with previously reported Inverted mode FinFET, L-shaped tunnel FET and Fully Depleted Silicon on Insulator (FD-SOI) MOSFET is carried out to find most suitable device which can provide highest immunity to radiation exposure. Response of JL FinFET based CMOS inverter in presence of radiation is studied and is also compared with other available CMOS inverters.

A Proposed Nonaligned Double Gate Junction FET Device and its Performance Improvement Using High-k Gate Oxide Material

This paper presents the effect of dielectric materials i.e., hafnium dioxide (HfO2, high-[Formula: see text] and silicon dioxide (SiO2, low-[Formula: see text], as gate-oxide material for the nonaligned double gate junction [Formula: see text]-channel field effect transistor (NADG-NFET). The NADGNFET device proposed in this work lowers the second order effects and improves the transistor linear performance at radio frequency. The device response with gate-oxide material is investigated by using two dielectric materials on the obtained current–voltage characteristics, intrinsic gain, and linearity parameter. The device simulations were done using a 2D-sentaurus TCAD tool. The results were examined in terms of DIBL (drain-induced barrier lowering), SS (subthreshold swing), [Formula: see text] current, [Formula: see text] ratio, the Intrinsic gain ([Formula: see text], and intermodulation distortion power-3 (IMD3) parameter. It has been found that high-[Formula: see text] dielectric decreases the DIBL by 40%, improves the [Formula: see text] ratio by 8 times, and also improves the intrinsic gain by 38% compared to low-[Formula: see text] dielectric material. However, the high frequency parameter result was better with low-[Formula: see text] dielectric material. This gives a trade-off in the device applications. The IMD3 plot shows that using the two gate-oxide material will give the same performance to the radio frequency (RF) signal.

Combined Influence of Gate Oxide and Back Oxide Materials on Self-Heating and DIBL Effect in 2D MOS2-Based MOSFETs

In this paper, degradation effects, such as self-heating effect (SHE) and drain-induced barrier lowering (DIBL) effect in 2D MoS2-based MOSFETs are investigated through simulations. The SHE is simulated based on the thermodynamic transport model. The dependence of the DIBL effect and the lattice temperature in the middle of the channel on the gate length is considered for transistors with different gate oxide and back oxide (BOX) materials. The effects of Al2O3 and HfO2 as gate oxide and SiO2 and HfO2 as BOX materials are compared. Transistors, in which the channel is fully and partially (i.e., just below the gate) covered by a gate oxide, are considered. It is shown that the transistors with Al2O3 as gate oxide and SiO2 as BOX materials have higher immunity to DIBL effect and transistors with HfO2 as gate oxide and HfO2 as BOX materials have higher immunity to SHE.

Si–Ge based vertical tunnel field-effect transistor of junction-less structure with improved sensitivity using dielectric modulation for biosensing applications

A dielectric modulation strategy for gate oxide material that enhances the sensing performance of biosensors in junction-less vertical tunnel field effect transistors (TFETs) is reported. The junction-less technique, in which metals with specific work functions are deposited on the source region to modulate the channel conductivity, is used to provide the necessary doping for the proper functioning of the device. TCAD simulation studies of the proposed structure and junction structure have been compared, and showed an enhanced rectification of 104 times. The proposed structure is designed to have a nanocavity of length 10 nm on the left- and right-hand sides of the fixed gate dielectric, which improves the biosensor capture area, and hence the sensitivity. By considering neutral and charged biomolecules with different dielectric constants, TCAD simulation studies were compared for their sensitivities. The off-state current I OFF can be used as a suitable sensing parameter because it has been observed that the proposed sensor exhibits a significant variation in drain current. Additionally, it has been investigated how positively and negatively charged biomolecules affect the drain current and threshold voltage. To explore the device performance when the nanogaps are fully filled, half filled and unevenly filled, extensive TCAD simulations have been run. The proposed TFET structure is further benchmarked to other structures to show its better sensing capabilities.

Performance Analysis of Gate Engineered High-K Gate Oxide Stack SOI Fin-FET for 5 nm Technology

Abstract: This paper analyses the performance of 5 nm gate length gate engineered oxide stack silicon on insulator (SOI) fin field-effect transistor (OS-Fin-FET) for the first time. The high dielectric (High-K) value of the material-based gate oxide stack structure increases both the analog and the radio frequency (RF) performance of the Fin-FET device when compared to standard single gate oxide material structures. The work function of the engineered gate structure further helps in advancing the performance of the device in terms of on current (Ion), off current (Ioff) and the ratio of Ion/Ioff. The proposed OS-FinFET device improves on current (Ion) of the device by 12% in comparison to the high-K dielectric gate oxidebased FinFET device. Simulation of the device is further extended to study different electrical characteristics of the proposed device under other biasing conditions, to estimate enhanced analog and RF performance where the device is highly suitable for low power and high-speed applications. Overall, the proposed device shows improvement in existing architectures of the devices. Technology computer-aided design (TCAD) tool is used to perform entire simulations of the proposed device with 5 nm gate length. Aim: To enhance analog and RF performance of the Fin-FET device at 5 nm gate length. Background: Design of the sub-10 nm Fin-FET device undergoes charge shearing phenomena because of the minimum distance between source and drain. This problem is addressed by using High-K spacer over substrate but it leads to increase in the channel resistance and adverse short channel effects. A combination of different high-K dielectric materials can eliminate this performance. Hence most of the studies concentrated on spacer region and failed to consider channel region. This study tries to improve analog performance of the device using the approach of gate engineering with gate stack approach. Objective: The main objective of this study is to increase on current (Ion) of the device by implementing gate engineering approach, by choosing dual work function-based gate with oxide stack approach. The High-K dielectric material-based gate oxide reduces leakage current, decreases off current which will increase the ratio of Ion/Ioff. Methods: The dual work function gate material is taken with gate oxide stack approach by considering different High-K dielectric materials like HfO2, TiO2 with thin SiO2 layer as the interactive layer. Simulation of the device is carried out using TCAD Tool and results are compared with existing literature, to validate the results. Results: The proposed architecture of the Fin-FET device delivers excellent results in terms of on current and subthreshold characteristics compared to existing literature. The proposed device gives high on current of 0.027 A and current ratio of 1.08X104. Conclusion: A complete comparative analysis is carried out with existing literature on the proposed device, where the proposed device resulted in high performance. The proposed device improves 12% compared to existing literature, which is highly suitable for low power applications.

Analytical modeling of dielectric modulated negative capacitance MoS2 field effect transistor for next‐generation label‐free biosensor

AbstractIn this paper, a dielectric modulated negative capacitance (NC) MoS2 FET‐based biosensor is proposed for label‐free detection of biomolecules such as enzymes, proteins, DNA, and so forth. Various reports present on experimental demonstration and modeling of NC MoS2 FET but it is never utilized as a dielectric modulated biosensor. So, in this work, the modeling, characterization and sensitivity analysis of dielectric modulated NC MoS2 FET is focused. For immobilization of biomolecules, a nanocavity is formed below the gate by etching some portion of the gate oxide material. The immobilization of biomolecules in the cavity leads to a variation of different electrostatic properties such as surface potential, threshold voltage, drain current, and subthreshold swing which can be utilized as sensing parameters. An analytical model for the proposed biosensor is also developed in the subthreshold region by considering the properties of two‐dimensional ferroelectric materials and benchmarked with TCAD device simulations. The effect of change of gate length and doping concentration on different electrical properties is also analyzed to estimate the optimum value of channel doping. The results prove that the proposed device can be used for next‐generation low power label‐free biosensor which shows enhanced sensitivity as compared to traditional FET‐based biosensors.

Impact of gate misalignment on the performance of CNTFET: TFET vs MOSFET

CNTFET device structures are gaining more research interest as conventional FET structures are reaching their scaling limits. One of the most crucial effects that could occur in the fabrication on the nanometer scale is the gate misalignment. In this paper, we report on a study of the impact of gate misalignment on the performance of MOSFET and TFET CNT-based device architectures. Given the fact that gate misalignment can occur on any side of the gate, extensive simulations have been carried out to account for the gate misalignment towards the source and the drain sides. We scrutinize how the misalignment influences the device performance parameters like ON-current, subthreshold swing SS, overall gate capacitance and cut-off frequency. Moreover, these “Figure of Merits” are calculated for two cases, one of which uses a single oxide all over the device various regions and the other incorporates a low-k oxide spacer material over the source and the drain regions while a high-k gate oxide material is utilized over the channel region. Simulation results show that MOSFETs are more immune to the fabrication process variations than TFETs.

(Dielectric Science & Technology Thomas Callinan Award) Materials and Processes As Enablers for Moore Moore and Beyond Moore Technologies

In this presentation, an overview will be presented of historic and recent developments achieved w.r.t. materials and processes that enabled continued performance scaling of CMOS and beyond CMOS applications. Starting from early high-k work. For decades, thermal oxidation of crystalline Silicon into SiO2 has been the gate oxide material in CMOS technology. Miniaturization for performance improvement, required the gate dielectric to decrease in thickness to support the required increase in capacitance (per unit area) and drive current (per device width). Early 2000, the thickness scaled below 1.5 nm, causing drastically increased leakage currents, high power consumption and reduced device reliability. Replacing the SiO2 gate dielectric with a high-κ (dielectric constant) material allows increased gate capacitance without the associated leakage effects. Activities involved the unit process step development of dielectric and metal deposition processes, advanced interface preparation, electrical and physical characterization and wet and dry etch process development. In a second section, emphasis will be on emerging nanomaterials. Nanotechnology is defined as the manipulation of matter with at least one dimension sized from below 100nm, thus all CMOS activities are functional nanotechnology. The latter concentrated initially on Graphene, but extended further towards Transition Metal Dicalchogenide Materials. Emphasis of the work will be on growth, functionalization, dielectric passivation and doping of these materials. Lastly, expanding on the nanomaterial know-how also progress with regard to low-k dielectrics, area selective deposition processes (for bottom-up lithography) and application of nanochemistry research for photoresist material screening, where chemical interactions at the nanoscale, related to the EUV lithography (radiation chemistry) are hampering the pattern scaling.Throughout the presentation, recognition will be given to people (PhD students) that contributed to this work and the presentation is also in honor of Prof Dolf Landheer and Professor Samares Kar with whom I organized my first ECS symposium.

Simulation and Comparison of Current-Voltage Characteristics in Double Gate Nanowire FET Using ZnO and SiO2 as Gate Oxide Materials

The aim of the project is to simulate and compare current-voltage characteristics in double gate nanowire field effect transistors made of ZnO and SiO2 gate oxides with thicknesses ranging from 1 to 30 nm. Materials and methods: The drain characteristics of double gate nanowire FET for the two gate oxides were considered for analysis. Altogether 147 drain current samples were considered for each group. Results: The two groups are subjected to an independent sample test using SPSS software, which calculates the significant mean value. The SPSS tool's chart builder is used to create a statistical graph. The mean for those in the highest quartile of drain current of ZnO based DG NW FET (drain current=0.461 mA, 95% CI:0.232-0.458 mA, p<0.05), but in SiO2 based DG NW FET (drain current=0.115 mA, 95% CI:0.232-0.458 mA, p<0.05). Conclusion: ZnO nanowire field-effect transistors have better switching characteristics and higher drain current than SiO2. The drain current is altered by varying the oxide thickness of the material. The drain current of ZnO is significantly higher than that of SiO2.

Study ofImpact of HfO2gate oxide on the Electrical Characteristics of Nanowire Junction lessTransistor

This paper proposes hafnium (IV) oxide (HfO2) as gate oxide material of the nanowire junctionless transistor (NJT) to replace the conventional silicon dioxide (SiO2). Leakage current usually increased due to an increase of tunneling of electronsin SiO2transistor when the thickness oxide (tox) of the gate material is below 2nm. The main advantages of HfO2is high dielectric constant k of 20 to 25 which is almost 6 times than that of SiO2. Similarly, HfO2has an energy band gap of 5.3 to 5.7eV. As a result, low leakage current and short channel effects (SCEs) was experienced. An increased in the gate capacitance of the device leads to improve the performance of the device without affecting the enhanced leakage current. All these was achieved by designing and simulating the device using the SDE tools of Sentaurus TCAD. Electrical characteristics was extracted using the Sdevice tools of the software. The performance was significantly increased to approximately 1010using HfO2material

Non-Linearity and RF Intermodulation Distortion Check of Ultrascale GNRFET Device Using NEGF Technique to Achieve the Highest Reliable Performance

The non-linearity and radio-frequency (RF) intermodulation distortion in ultrascale graphene-nanoribbon-field-effect-transistor (GNRFETs) is reported. The important figure of merits related to the non-linearity and the RF distortion in terms of transconductance, high-order harmonics, VIP2, VIP3, IIP3, IMD3 and 1-dB compression point have been explored to evaluate the power of ultrascale GNRFET device in RF high-performance applications. Also, the RF important parameters in the cases of total capacitance, cut-off frequency, and transconductance frequency product have been monitored. This paper presents a useful manual to improve the GNRFET RF performance while maintaining high reliability. The influence of the structural parameters of GNRFET device, such as the gate length, gate oxide thickness, gate oxide material, and GNR index on the RF parameters and non-linearity/RF intermodulation distortion have been investigated in order to determine the best setup for the ultrascale GNRFET device applicable in RF applications. The paper benefits from the numerical approach governed by a nonequilibrium-green-function coupled by a three-dimensional Poisson equation in a self-consistent manner. Also, because the ultrascale GNRFET (gate length smaller than 7.5 nm) has been analyzed, the position-energy dependent effective mass model is considered for more accurate simulation.

Enhanced infrared photoresponse of a new InGaZnO TFT based on Ge capping layer and high-k dielectric material

In this paper, a novel InGaZnO (IGZO) Infrared (IR) thin-film Phototransistor (Photo-TFT) consisting of Germanium capping layer (Ge-CL) and high-k dielectric material is proposed and numerically investigated. The role of introducing Ge-CL/IGZO heterojunction and high-k dielectric such as HfO 2 , ZrO 2 , Ta 2 O 5 and TiO 2 in achieving the dual benefit of IR photodetection ability and reduced dark noise effects is demonstrated. It is found that the proposed Ge-CL/IGZO Photo-TFT with appropriate gate oxide material can offer high detectivity of 2.3 × 10 14 Jones, superior current ratio exceeding 200 dB and high IR responsivity of 4.1 × 10 2 A/W. These enhancements are attributed to a mixture of two effects; firstly, the introduction of p-type Ge-CL leads to form a p-n junction with IGZO, thus enhancing the separation and transfer mechanisms of photo-induced electron/hole pairs. Secondly, the use of high-k dielectric materials enables better control of the channel conductivity , allowing reduced power consumption. Therefore, we believe that the use of Ge-CL with suitable high-k dielectric material pinpoints a new pathway to design high IR photoresponse sensors based on cost-effective IGZO TFT building block, which makes it potential alternative for high-performance optoelectronic systems. • A new high-performance IGZO-TFT-IR sensor is proposed. • The proposed sensor demonstrates high IR responsivity of 4.1 × 10 2 A/W. • A superb detectivity and an ultrahigh I ON /I OFF ratio are recorded. • The proposed sensor is a promising alternative for low power consumption photosensors.

Darlington Based 8T CNTFET SRAM Cells with Low Power and Enhanced Write Stability

In this paper, a novel low power and high write margin Darlington based NCNTFET Darlington 8T SRAM cell is proposed. The power consumption of the proposed Darlington SRAM cell is compared with that of conventional 6T CNTFET and conventional 8T CNTFET SRAM cells. The power consumption of the proposed Darlington SRAM cells is very less as compared to that of conventional 6T and 8T CNTFET SRAM cells for all write, hold, and read operations. The write static noise margin (WSNM) of the proposed NCNTFET Darlington 8T cell is found to increase by 70.83% than that of both conventional 6T and 8T CNTFET SRAM cell. Effect of CNTFET parameters such as chiral vectors (m,n), gate oxide thickness (Hox), dielectric constant of gate oxide material (Kox), temperature, pitch value, number of carbon nano tubes (CNTs) and supply voltage (VDD), on the power performance, drain current (ID) and drain to source voltage (VDS) of the novel proposed Darlington SRAM cell are investigated. The write, hold, and read power consumption of proposed NCNTFET Darlington 8T SRAM cell is compared with that of some of the existing SRAM cells. The simulation is carried out using Stanford University 32 nm CNTFET model.

Device Performance Optimization of Organic Thin-Film Transistors at Short-Channel Lengths Using Vertical Channel Engineering Techniques

This paper presents a finite-element-based two-dimensional numerical simulation study of the vertical channel engineering approaches for controlling the short-channel effects (SCEs) in organic transistors based on thin-film transistor technology (OTFTs). The impact of gate-oxide thickness TOx scaling and usage of high-permittivity gate dielectric material has been analyzed for a bottom-contact organic thin-film transistors at channel length of 0.7 μm. The techniques have been used to investigate the impact on drain-induced barrier lowering (DIBL), sub-threshold slope, and IOn/IOff ratio. The results have shown a significant reduction in values of DIBL and sub-threshold slope in short-channel OTFTs when either of the channel engineering techniques are employed. A high IOn/IOff ratio of the order of ~107 has been achieved using a high-permittivity gate-oxide material. It has been observed that using a high-permittivity gate dielectric material, a peak value of IOn/IOff ratio can be achieved for an equivalent oxide thickness of 5 nm. The results suggest that the desirable transistor performance can be achieved through proper selection of gate-oxide material and thickness.