Gate Oxide Lifetime Research Articles

Modeling of Charge-to-Breakdown with an Electron Trapping Model for Analysis of Thermal Gate Oxide Failure Mechanism in SiC Power MOSFETs.

The failure mechanism of thermal gate oxide in silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs), whether it is field-driven breakdown or charge-driven breakdown, has always been a controversial topic. Previous studies have demonstrated that the failure time of thermally grown silicon dioxide (SiO2) on SiC stressed with a constant voltage is indicated as charge driven rather than field driven through the observation of Weibull Slope β. Considering the importance of the accurate failure mechanism for the thermal gate oxide lifetime prediction model of time-dependent dielectric breakdown (TDDB), charge-driven breakdown needs to be further fundamentally justified. In this work, the charge-to-breakdown (QBD) of the thermal gate oxide in a type of commercial planar SiC power MOSFETs, under the constant current stress (CCS), constant voltage stress (CVS), and pulsed voltage stress (PVS) are extracted, respectively. A mathematical electron trapping model in thermal SiO2 grown on single crystal silicon (Si) under CCS, which was proposed by M. Liang et al., is proven to work equally well with thermal SiO2 grown on SiC and used to deduce the QBD model of the device under test (DUT). Compared with the QBD obtained under the three stress conditions, the charge-driven breakdown mechanism is validated in the thermal gate oxide of SiC power MOSFETs.

Optimized 750V SiC MOSFETs for Electric Vehicle Inverter Operation

We report an AEC-Q101-qualified 750V, 15 mΩ planar SiC MOSFETs with a long short circuit withstand time (SCWT) of > 9μs at VDS=400V and VGS=15V and a low specific on-resistance (RON,SP) of 2.1 mΩ.cm2 at VGS=15V designed for xEV traction inverter applications. The RDS(on) at VGS=15V increases from 15mΩ at 25 °C to 21 mΩ at 175 °C. A low turn-on (EON) and turn-off (EOFF) switching energy loss of 95.5μJ and 67μJ at IDS=75A, VDS=400V was measured at 25 °C. The gate oxide lifetime at worst case operating fields of 5MV/cm is >> 20 years.

Electrical overstress effect characterization on Power MOS Trenchfet and correlation with time dependent dielectric breakdown

In recent years, power electronics has played a fundamental role in the development of increasingly efficient circuits for energy conversion. The characterization of a Power MOSFET under a gate overstress and the correlation with the reliability performances represent a crucial point in the optimization of the trench technology where the oxidation processes of the gate oxide are critical in terms of uniformity and reproducibility of the thickness. This article explores these aspects with particular attention to the analysis of the electrical overstress effect on aging transistors parameters and the classical TDDB (time dependent dielectric breakdown) test for gate oxide integrity characterization and lifetime extrapolation.The latter actually trigger oxide breakdown which is not as relevant at operating conditions as parametric degradation which usually occurs much earlier.Moreover, a possible physical explanation to the adherence of both failure modes (breakdown and transistor aging) to the two typical failure model such as thermochemical model and anode hole injection has been subjected to analysis following fitting methods as did in the past including their reciprocal correlation.

Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

Accelerated Testing of SiC Power Devices under High-Field Operating Conditions

Power metal-oxide-semiconductor field-effect transistors (MOSFETs) experience conditions of high field during normal operation. During switching conditions, unexpected transient events may occur which force devices into avalanche or short circuit conditions. Moreover, silicon carbide devices typically experience higher fields in the gate oxide and drift regions than comparable Si devices due to channel and drift property differences. A summary of SiC MOSFET reliability and ruggedness test results are reported here. Reliability tests under high field conditions: positive-bias and negative-bias temperature instability (PBTI, NBTI) to examine threshold stability; time-dependent dielectric breakdown (TDDB) for gate oxide lifetime extrapolation; high-temperature reverse bias (HTRB); and HTRB testing under high neutron flux to determine terrestrial neutron single-event burnout (SEB) rates. High-power ruggedness evaluation is presented for SiC MOSFETs under forced avalanche conditions (unclamped inductive switching (UIS)) and under short-circuit operation to bound device safe operating areas. Overall results demonstrate the intrinsic reliability of SiC MOSFETs.

Compatibility of POCl<sub>3</sub> Gate Process with the Fabrication of Vertical 4H-SiC MOSFETs

We used the POCl3 gate technique for the fabrication of 4H-SiC vertical MOSFETs, and examined its effect on the VTH-RON tradeoff and the compatibility with device fabrication. The gate oxide film was formed by thermal dry O2 oxidation followed by POCl3 or NO annealing. The POCl3 process reduced RON by about 30% compared with the NO process for the ones having VTH of 1.1 V, being attributed to the channel mobility enhancement. Moreover, the improvement was more effective for higher VTH designs. The conventional thermal treatment after the gate process considerably spoiled the channel mobility improvement brought by the POCl3 annealing and strengthened negative charge trapping in the gate oxide. The presumed extra-formed defects also affected the EOX dependence of tBD on the TDDB tests, being expected to shorten the gate oxide lifetime under practical device operation stress. Successful insertion of the POCl3 process into production lines depends upon careful low-temperature post processing.

Gate Oxide Reliability of SiC MOSFETs and Capacitors Fabricated on 150mm Wafers

Gate oxide reliability on silicon carbide MOSFETs and large-area SiC N-type capacitors was studied for devices fabricated on 150mm SiC substrates. Oxide lifetime was measured under accelerated stress conditions using constant-voltage time-dependent dielectric breakdown (TDDB) testing, or ramped-voltage breakdown (RBD) testing. TDDB results from 1200V Gen3 MOSFETs reveal a field acceleration parameter of about 35 nm/V, similar to values reported for SiO2 on silicon. Temperature-dependent RBD tests of large capacitors from 25°C to 200°C reveal an apparent activation energy of 0.24eV, indicating that oxide lifetime increases as the temperature is decreased, as expected. Using this acceleration parameter and activation energy in the linear field model, the gate oxide lifetime from MOSFET TDDB testing extrapolates to greater than 108 hours at a gate voltage of 15 VGS at 175°C.

Silicon-Carbide Power MOSFET Performance in High Efficiency Boost Power Processing Unit for Extreme Environments

Abstract Silicon-Carbide (SiC) device technology has generated much interest in recent years. With superior thermal performance, power ratings and potential switching frequencies over its Silicon (Si) counterpart, SiC offers a greater possibility for high powered switching applications in extreme environment. In particular, SiC Metal-Oxide-Semiconductor Field-Effect Transistors' (MOSFETs) maturing process technology has produced a plethora of commercially available power dense, low on-state resistance devices capable of switching at high frequencies. A novel hard-switched power processing unit (PPU) is implemented utilizing SiC power devices. Accelerated life data is captured and assessed in conjunction with a damage accumulation model of gate oxide and drain-source junction lifetime to evaluate potential system performance at high temperature environments.

A Structural Based Thermal Model Description for Vertical SiC Power MOSFETs under Fault Conditions

The accurate prediction of the SiC MOSFET withstanding time for single fault events greatly influences the requirements for device protection circuits for these devices in power converter applications, like voltage source inverters or power electronic transformers. For this reason, a thermal model, based on the structural design and the physical dimensions of the chip as well as material properties of 4H-SiC, is proposed. This article gives a general description of the thermal behaviour of vertical SiC MOSFET under various driving and boundary conditions in case of a short-circuit event. The thermal model substitutes destructive tests of a device for an individual set of boundary conditions of an occurring fault event. The validity of the analytically parametrised thermal model is verified by experimental short-circuit tests of state-of-the-art vertical SiC MOSFETs for a set of various boundary conditions. The investigated thermal model can furthermore be used to standardise different gate-oxide degradation values from the literature for means of lifetime prediction of the gate oxide for an individual application under repetitive occurring fault or overload conditions. These manufacturer specific reported values measured with no standardised testing procedures can be translated into a maximum junction temperature, which is repeatedly reached. The thermal model therefore provides a unifying parameter for the gate-oxide lifetime calculation for an individual chip and application.

A quantitative study of Phosphorous implantation damage on the thick gate oxide of the 28 nm node

The tilted Phosphorous implantation has for a long time been adopted to form the lightly doped drain (LDD). For the first time, we report the implantation damage due to this on the thick gate oxide of the NMOSFET devices for 28nm technology. During the Time Dependent Dielectric Breakdown (TDDB) test, the breakdown time of the thick gate oxide of NMOSFET was found to be a function of implantation energy and dose. In this work, an empirical model was established to characterize the implantation induced gate oxide lifetime reduction, which was correlated to the effective oxide thickness reduction. Our results showed that a careful implantation scheme needs to be chosen to balance the reliability requirements and the device performance for the scaled 28nm process and beyond.

Impact of Oxidation Conditions and Surface Defects on the Reliability of Large-Area Gate Oxide on the C-Face of 4H-SiC

This paper discusses the issues regarding reliability of large-area (up to 25mm2) gate oxide on the C-face of 4H-SiC. We have shown that the TDDB characteristics of large-area gate oxide improved by separating gate oxidation processes into oxide growth by dry-oxidation and successive interface control by anneal in N2O ambient or that by wet-oxidation followed by anneal in H2 ambient. In particular, dry-oxidation followed by anneal in N2O ambient for interface treatment (dry+N2O process) is effective for the suppression of the random failure in TDDB characteristics. The estimated lifetime of gate oxide of less than 9mm2 by the dry+N2O process is six-digits larger than 30 years. In the case of the TDDB characteristics of 25mm2 gate oxide grown by the dry+N2O process, the initial and random failure in TDDB characteristics is dominant. However, even in this case, we have confirmed that the evaluated lifetime of 25mm2 gate oxide is more than 30 years. In order to clarify the mechanism of the degradation of the TDDB characteristics of large-area gate oxide, we examined the effect of the surface defect on the TDDB characteristics by observing the surface of each broken MOS capacitor after the TDDB test. We have found following results. (1) The initial failures in TDDB characteristics are mainly due to surface defects such as “down fall”, “comet”, and “triangular defect”. (2) The footprints of random failure do not correspond to the positions of smaller surface defects such as “bump”. Finally, we have found that the quality of the epitaxial layer affects random failure rate in the TDDB characteristics of large area gate oxide; the random failure in the TDDB characteristics of 25mm2 gate oxide on epitaxial layer grown by a certain epitaxial vendor is almost suppressed. However, the cause of the difference in TDDB characteristics is not identified.

NMOSFET의 제조를 위한 습식산화막과 질화산화막 특성에 관한 연구

본 논문에서는 핫 케리어 효과, 항복전압 전하, 트랜지스터 Id Vg 특성곡선, 전하 트래핑, SILC와 같은 특성들을 비교하기 위하여 HP 4145 디바이스 테스터를 사용하여 습식 산화막과 질화 산화막으로된 <TEX>$0.2{\mu}m$</TEX> NMOSFET를 만들어 측정하였다. 그 결과 질화 산화막으로 만들어진 디바이스가 핫 케리어 수명(질화 산화막은 30년 이상인 반면에 습식 산화막 소자는 0.1년임), Vg의 변화, 항복전압, 전계 시뮬레이션, 전하 트래핑면에서도 습식 산화막 소자보다 우수한 결과를 얻을 수 있었다. In this paper we fabricated and measured the <TEX>$0.26{\mu}m$</TEX> NMOSFET with wet gate oxide and nitride oxide gate to compare that the charateristics of hot carrier effect, charge to breakdown, transistor Id_Vg curve, charge trapping, and SILC(Stress Induced Leakage Current) using the HP4145 device tester. As a result we find that the characteristics of nitride oxide gate device better than wet gate oxide device, especially hot carrier lifetime(nitride oxide gate device satisfied 30 years, but the lifetime of wet gate oxide was only 0.1 year), variation of Vg, charge to breakdown, electric field simulation and charge trapping etc.

Strained Si/SiGe MOS technology: Improving gate dielectric integrity

Strained Si is recognised as a necessary technology booster for the nanoelectronics regime. This work shows that high levels of stress attainable from globally strained Si/SiGe platforms can benefit gate leakage and reliability in addition to MOSFET channel mobility. Device self-heating due to the low thermal conductivity of SiGe is shown to be the dominating factor behind compromised performance gains in short channel strained Si/SiGe MOSFETs. Novel thin virtual substrates aimed at reducing self-heating effects are investigated. In addition to reducing self-heating effects, the thin virtual substrates provide further improvements to gate oxide integrity, reliability and lifetime compared with conventional thick virtual substrates. This is attributed to the lower surface roughness of the thin virtual substrates which arises due to the reduced interactions of strain-relieving misfit dislocations during thin virtual substrate growth. Good agreement between experimental data and physical models is demonstrated, enabling gate leakage mechanisms to be identified. The advantages and challenges of using globally strained Si/SiGe to advance MOS technology are discussed.

Monte Carlo Based Weibull Lifetime Uncertainty Calculations and Statistical Comparison of Semiconductor Manufacturing Process Module Changes for Lifetime Improvement

Weibull statistics are used in generation of gate oxide lifetimes from time dependent dielectric breakdown (TDDB) data. However, error bounds for the Weibull generated predicted lifetimes are not usually presented. Statistical methods to judge the impact of process improvements on Weibull lifetimes are also presented. Each of three electric fields was used to generate 1000 points point sets with probability of occurrence determined from a fixed, known underlying distribution. This distribution represents a population of points with a Weibull distribution. From the 1000 points, a sample of 10 to 25 points was randomly selected for each of the three applied electric fields. The subset of points were placed in rank order, and analyzed using the Maximum Likelihood procedure. These steps were repeated to obtain Monte Carlo based statistical information about the impact of sample size on our knowledge of the population. Additionally, similar methods were used to determine the experimental design required to statistically valid information regarding the impact of process changes on gate oxide lifetime.

Ultrathin Gate-Oxide Breakdown—Reversibility at Low Voltage

Solid-insulator breakdown always leads to a permanent conduction path that is irreversible. This is a built-in assumption in all gate-oxide breakdown reliability measurement and lifetime projection. This assumption is not valid when the gate-oxide thickness is less than 2 nm and the operation voltage is 1 V or less. The authors examine the impact of reversible breakdown using breakdown data from 12 000 devices stressed by plasma charging damage. The data support the notion that when the surge current is limited at breakdown, the breakdown event may not leave any mark such as a permanent conduction path. The implication is that the commonly used accelerated-stress test, such as time dependent dielectric breakdown (TDDB), may be underestimating the actual gate-oxide lifetime by as much as a million folds.

Gate oxide reliability in an integrated metal-oxide-semiconductor field-effect transistor-microelectromechanical system technology

We have demonstrated a simple technique for building n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and complex micromechanical systems simultaneously instead of serially, allowing a more straightforward integration of complete systems. The fabrication sequence uses few additional process steps and only one additional masking layer compared with a microelectromechanical system (MEMS)-only technology, but exposes the MOSFET gate oxide to the extreme temperatures of MEMS processing. We find that the high-temperature MEMS anneals can greatly change the current-voltage characteristics of the SiO2 gate oxide film. Defects are introduced by the high-temperature processing which result in considerable positive-charge trapping at short times that leads to increased currents using high bias fields and short bias times. At longer times, the current across the oxide decays as 1/time suggesting electron traps that are uniformly distributed in the bulk of the oxide. A traditional reliability evaluation of the thick oxides using time-dependent dielectric breakdown is greatly hampered by excessive impact ionization that occurs at high gate voltages. This makes a rigorous evaluation of gate oxide lifetime at use fields difficult. We do note that while the current below breakdown is altered by the positive-charge trapping, the voltages at breakdown seen in ramps are not severely impacted by the high-temperature annealing. Breakdown voltages of films annealed at the highest of the temperatures studied here are about the same as those of unannealed films. The breakdown fields of these stressed oxides are 10–11MV∕cm, suggesting that reliable SUMMiT™ field-effect transistor process gate oxides can be fabricated as long as the use voltage is well below the onset for impact ionization.

Hydrogen-related influence of the metallization stack on characteristics and reliability of a trench gate oxide

We discuss influences of the metallization / passivation stack on the 30 nm thick gate oxide of a trench DMOS. A variation in the metallization stack directly influences the gate oxide lifetime, but also the transfer characteristics of the device and the interface trap density revealed by charge-pumping measurements. Surprisingly, a better anneal of the Si-SiO2 interface and the bulk-oxide, resulting in a smaller measured interface-trap density on virgin wafers, implies a reduced GOX reliability. These effects are attributed to the release of reactive hydrogen from PECVD deposited silicon-nitride layers.

Hot-carrier degradation characteristics and explanation in 0.25 μm PMOSFETs

The hot-carrier effect (HCE) of deep-submicron PMOSFETs has been investigated. It is found that the HCE includes both generation of interface states and formation of positive fixed charges in the gate oxide. We present experimental evidences showing that two degradation mechanisms are important in the case of deep-submicron PMOSFETs. Firstly, the generation of positive fixed oxide charges is significant in the case of deep-submicron PMOSFETs, which degrades the threshold voltage and even limits the transistor lifetime. For advanced analogy and mixed signal applications, process and device reliability limits need to be set up based also on threshold voltage shift, in addition to traditional methods of the transconductance degradation or gate oxide lifetime. Secondly, the generation of interface states by holes influences the device characteristics. Some speculation on the HCE formation process is included.

Effect of boron on gate oxide degradation and reliability in PMOS devices

Modern CMOS technology widely utilizes dual poly gate technology to create surface channel PMOS devices with low threshold voltage. The paper presents analysis of degradation and gate oxide reliability in 50 Å oxide p+-poly PMOS transistors. The post boron implant anneal temperature is used to vary amount of boron penetration into the oxide. Results indicate significant role of boron in reduction of the gate oxide lifetime of PMOS devices and enhanced electron trapping in the oxide. The degradation correlates with the threshold voltage variation due to channel doping change. No effect of the boron penetration on stress-induced leakage current was observed. The results are discussed in terms of boron-related oxide defects and deteriorated interface of boron-doped polysilicon.

The gate oxide lifetime limited by `B-mode' stress induced leakagecurrent and the scaling limit of silicon dioxides in the direct tunnellingregime

The scaling limit of the silicon dioxides as gate dielectrics isdiscussed from the viewpoint of the oxide lifetime. First, the definition ofthe `oxide lifetime' in the direct tunnelling regime has been studied, eventhough various studies report that soft breakdown (SBD) induces devicefailure. It is revealed that the previous studies overestimated the leakagecurrent after the SBD, i.e. the `B-mode' stress induced leakage current(B-mode SILC), and that the SBD stressed under typical device-operatingconditions never prevents the transistors from working well. Although hardbreakdown is expected to limit the oxide lifetime consequently, a new conceptof oxide lifetime limited by the chip-level off-leakage current, i.e. thestatistical effect of the B-mode SILC, has been proposed. The study on thestress voltage dependence of oxide lifetimes limited by these two factorsdemonstrates that the oxide lifetime under typical device-operating conditionsis limited by the B-mode SILC. Based on this concept, it has been clarifiedthat the oxide lifetime as a reliability issue does not limit the scaling downof silicon dioxides as the gate dielectrics in future devices.