Gate-overlapped Lightly Doped Drain Research Articles

A novel thin-film transistor with step gate-overlapped lightly doped drain and raised source/drain design

In this paper, a novel step gate-overlapped lightly doped drain (GOLDD) with raised source/drain (RSD) structure (SGORSD) is proposed for TFT electronic device application. The new SGORSD structure could obtain a low electric field at channel near the drain side owing to a step GOLDD design. Compared to the conventional device, the SGORSD TFT exhibits a better kink effect and higher breakdown performance due to the reduced drain electric field (D-EF). In addition, the leakage current also can be suppressed. Moreover, the device stability, such as the threshold voltage shift and drain current degradation under a high gate bias, is improved by the design of SGORSD structure. Therefore, this novel step GOLDD structure can be a promising design to be used in active-matrix flat panel electronics.

A Novel Four-Mask Low-Temperature Polycrystalline Silicon PMOS Thin-Film Transistor With Advanced Terrace Structure for AMOLED Application

We propose a novel four-mask low-temperature polycrystalline-silicon PMOS structure. In this letter, we obtain the utmost simplified thin-film transistor (TFT) structure by eliminating the storage doping, passivation, and anode photomask steps. The proposed four-mask structure has a self-aligned terrace structure whose lightly doped drain (LDD) and gate-overlapped LDD are formed with only one photomask step. The on current of the four-mask PMOS TFT with an advanced terrace structure is similar to that of the conventional seven-mask TFT, while the off current of the new structure is lower than that of the conventional seven-mask TFT.

Effects of Fabrication Parameters on the Electrical Stability of Gate Overlapped Lightly Doped Drain Polysilicon Thin-Film Transistors

We analysed the electrical characteristics and the stability of gate overlapped lightly doped drain (GOLDD) thin-film transistors (TFTs) with different channel length, n- region doping concentration and lateral doping profile at the junctions. A reduction of kink effect and an increase of device stability have been observed with the increase of the lateral doping profile. These results are explained by numerical simulation of electrical characteristics and hot carrier induced degradation. We found that different doping profiles produce, after bias stress, different interface state distributions across the channel/n- and n-/n+ junctions.

Gate Overlapped Lightly Doped Drain Poly-Si TFTs Employing 45° Tilt Implant and OI-ELA Activation for S/D

A gate overlapped lightly doped drain (GOLDD) poly-Si thin film transistor (TFT) employing the 45° tilt implant for source and drain (S/D) regions, is proposed. In order to activate both n + S/D and n - lightly doped drain (LDD) regions, and to eliminate junction defects, oblique-incident excimer laser annealing activation (OI-ELA) was performed. At certain conditions, such as when V DS = 3.3 V, V GS = -20 V, the proposed poly-Si TFT with W/L = 10 μm/3 μm exhibited a lower anomalous leakage current of 4.7 X 10 -11 A/μm, than conventional TFTs, with an anomalous leakage current of 1.7 × 10 -9 A/μm. In addition, the proposed device held 89% of maximum transconductance against hot-carrier stress, compared to the conventional one, which holds 46%.

Novel Method of Intrinsic Characteristic Extraction in Lightly Doped Drain Metal Oxide Semiconductor Field Effect Transistors for Accurate Device Modeling

A lightly doped drain (LDD) region, particularly a gate-overlapped LDD (GOLD) region, is subjected to a gate electric field and its gate-controlled resistance affects the device characteristics. We developed a new extraction method for determining the intrinsic characteristics of LDD MOSFETs using a simple series resistance model, in which the GOLD region is assumed to be a depletion MOSFET with a negative threshold voltage derived from C–V measurement. Polycrystalline-silicon (poly-Si) TFTs with a channel length of 4–100 µm were used for the test LDD samples, particularly GOLD MOSFETs. It was demonstrated that the new proposed method precisely extracts the intrinsic characteristics of poly-Si GOLD TFTs by comparing them with the intrinsic characteristics of poly-Si Self-Aligned (SA) TFTs extracted by the conventional method.

Gate Overlapped Lightly Doped Drain Poly-Si TFTs Employing 45° Tilt Implant For Source and Drain

ABSTRACTWe propose a short channel gate overlapped lightly doped drain (GOLDD) poly-Si TFT employing 45° tilt implant for source and drain (S/D) regions without any additional ion doping or mask. Oblique-incident ELA activation is performed to activate both n+ S/D and n- LDD regions as well as cure junction defects. The proposed poly-Si TFT can suppress the anomalous leakage current, and exhibit the better reliability against the hot-carrier stress.

Analysis of electrical characteristics of gate overlapped lightly doped drain (GOLDD) polysilicon thin-film transistors with different LDD doping concentration

Different drain field architectures have been recently investigated to reduce field-enhanced effects in conventional self-aligned polysilicon thin-film transistor (TFT) architecture, induced by the intense electric fields at the drain junction. Among these, gate overlapped lightly doped drain (GOLDD) architecture has been shown to be effective in reducing the drain field in both on and off states of the TFT, without introducing appreciable series resistance effects. In this paper, we investigate the electrical characteristics, both in the on- and in the off-regime, of GOLDD polysilicon TFTs, made with different LDD doses, by combining experimental data with two-dimensional (2-D) numerical analysis. We also demonstrate that both the on-state and off-state features of the GOLDD structure can be readily understood in terms of a simple, new model, based upon two TFTs series. This is consistent both with the experimental data and the results of full 2-D simulations. This paper not only clarifies the dependence of kink effect, leakage current, and series resistance upon the LDD-doping, but also provides the guidelines to optimize physical parameters of GOLDD TFTs.

Analysis of Hot Carrier Effect in Low-Temperature Poly-Si Gate-Overlapped Lightly Doped Drain Thin Film Transistors

Low-temperature poly-Si thin film transistor (TFT) is widely expected as the most promising technology for realizing system on panels. We fabricated the poly-Si TFT with a gate-overlapped Lightly Doped Drain (GOLD) structure. Reliability was evaluated using electrical stress comparing conventional lightly doped drain (LDD) and single drain structures. We have confirmed that the degradation of ON current and the field effect mobility was very small compared to the case of conventional LDD or non-LDD structures. We have analyzed the reliability of the GOLD TFT using a two-dimensional device simulator and emission microscope. We found that more hot electrons are generated in GOLD TFT, however, a vertical negative field plays a dominant role for improving the reliability of the GOLD TFT. Based on the experimental and theoretical results, we proposed a new reliability model. Impact ionization occurs far from the interface between the oxide and polysilicon by the vertical negative field. Therefore, the damaged region in poly-Si does not affect such electrical performance as drain current.

A new self-consistent model for the analysis of hot-carrier induced degradation in lightly doped drain (LDD) and gate overlapped LDD polysilicon TFTs

Hot-carrier induced degradation is a main issue in the electrical stability of polysilicon TFTs and drain field relief architectures have been introduced, such as lightly doped drain (LDD) and gate overlapped LDD (GOLDD), to improve the stability. Bias-stress experiments were performed on both LDD and GOLDD structures, biasing the devices above pinch-off at constant V g and different V ds. While the LDD structure presented considerable hot-carrier induced degradation, GOLDD devices were characterised by a very high electrical stability. To explain such a difference in electrical stability, we first analysed the spatial distributions of the electric fields, which are lower in GOLDD structures. In addition, we developed a new model to describe the hot-carrier induced degradation, based on the correlation between hot carrier injection currents and interface state generation. Indeed, hot carrier injection is known to produce interface states and oxide trapped charge, and, depending upon their spatial distribution, can strongly influence the local electric fields as well as the current. The proposed model nicely reproduces the degraded characteristics, thus providing indications on the spatial distribution of the generated interface states.

A p-channel SMC poly-Si thin film-transistor with a GOLDD structure

Abstract We have developed a silicide-mediated crystallization (SMC) polycrystalline silicon (poly-Si) thin film transistor (TFT) with a gate overlapped lightly doped drain (GOLDD) structure. Applying a GOLDD structure to the SMC poly-Si TFT, the off-state leakage current of coplanar TFT is reduced, while the reduction of the on-state current is relatively small. The p-channel poly-Si TFT with a GOLDD structure exhibited a field effect mobility of 50 cm 2 /V s and an off-state leakage current of 3.8×10 −11 A/μm at the drain voltage of −5 V and the gate voltage of 10 V.

Improved lifetime of poly-Si TFTs with a self-aligned gate-overlapped LDD structure

We investigated the lifetimes for various poly-Si thin film transistor (TFT) structures. A gate-overlapped lightly doped drain (GOLDD) structure was self-aligned by the side etching of Al-Nd in an Al-Nd/Mo gate electrode. The dopant activation process in the LDD regions of GOLDD TFTs was performed by using a H/sub 2/ ion-doping technique. We also observed the effect of lifetime on the source/drain activation process. The thermal annealing of the source/drain region was found to extend the lifetime. The predicted lifetime of our GOLDD poly-Si TFT is superior to those of non-lightly doped drain (non-LDD) and lightly-doped drain (LDD) poly-Si TFTs. The trapped-electron density at the drain junction after bias-stressing was also investigated using a two-dimensional (2-D) simulation.

A W-spacer GOLD TFT with high performance and high reliability

In this paper, we successfully fabricated Gate-Overlapped Lightly-doped Drain (GOLD) polycrystalline silicon thin-film transistors (poly-Si TFTs) with selectively deposited spacers. Under appropriate deposition conditions, tungsten (W) films can be selectively deposited on poly-Si gate electrodes to form spacers without any additional etching process. Compared to the conventional poly-Si TFTs without LDD structures, our devices effectively suppress the kink effect and the punch-through phenomenon in short-channel devices. The hot-carrier reliability of our devices is also improved due to the reduced electric field on the drain side. In addition, the transconductance of our devices is compatible to that of conventional devices. This is because the W-spacer acts as a part of gate electrode to induce channel when the device is operated under ON state.

Hot carrier-induced degradation of gate overlapped lightly doped drain (GOLDD) polysilicon TFTs

Hot-carrier injection is known to produce interface states and oxide trapped charge, which, depending upon their spatial distribution, can strongly influence the local electric fields as well as the current flow. In this work, we analyze the hot carrier-induced degradation of gate overlapped lightly doped drain (GOLDD) polysilicon thin film transistors (TFTs) and a new model, which correlates the interface state generation with the hot carrier injection current, is proposed. The defect generation rate has been assumed to depend upon the product of hot electron and hole currents J/sub eh/, and the resulting interface state distribution has been evaluated self-consistently with the current density and carrier concentration distributions. By successive iterations, a complete spatial and time evolution of the interface state distribution has been determined, and the electrical characteristics, calculated with these interface state distributions are in good agreement with the experimental data.

Low-frequency excess noise induced by hot-carrier injection in polysilicon thin-film transistors

Low-frequency noise has been investigated in self-aligned (SA) and gate overlapped lightly doped drain (GOLDD) polysilicon thin-film transistors (TFTs). We found that, at low Vds, both device structures are characterised by 1/f noise, originating from carrier number fluctuations. However, when the SA devices were operated in the kink regime, an excess noise was observed, in contrast to GOLDD TFTs. This has been explained by attributing the excess noise to supplemental oxide charge fluctuations induced by hot-carrier injection into the gate oxide. By using two-dimensional numerical simulations, we show that the hot-electron emission current in SA polysilicon TFTs is much higher than in the GOLDD structure.

Low-frequency noise in gate overlapped lightly doped drain polycrystalline silicon thin-film transistors

Low-frequency noise has been investigated in gate overlapped lightly doped drain (GOLDD) polysilicon thin-film transistors (TFTs). We found that as in self-aligned polycrystalline silicon (polysilicon) TFTs, the low-frequency noise GOLDD polysilicon TFTs originates from carrier number fluctuations. In addition, no excess noise was observed when measuring GOLDD TFTs in the kink regime, in contrast to what was observed in self-aligned polysilicon TFTs. This has been explained by attributing the excess noise to supplemental oxide charge fluctuations induced by hot-carrier injection into the gate oxide and showing, by using two-dimensional numerical simulations, that the hot-electron emission current in GOLDD polysilicon TFTs can be much lower than in conventional drain contact configurations.

Numerical Analysis of the Electrical Characteristics of Gate Overlapped Lightly Doped Drain Polysilicon Thin Film Transistors

Polycrystalline silicon (polysilicon) thin film transistor (TFT) technology is emerging as a key technology for active matix liquid crystal displays, allowing the integration of both active matrix and driving circuitry on the same substrate. However, conventional self-aligned polysilicon TFTs present several undesired effects in the electrical characteristics, including large off-currents, kink effect and hot carrier instabilities. These effects are related to the presence of high electric fields at the drain junction and drain field relief is essential. Among the different structures proposed to reduce the drain field, the gate overlapped lightly doped drain (GOLDD) structure appears to have a number of advantages. In this work we investigate the electrical characteristics of GOLDD polysilicon TFTs by using 2-dimensional (2D) numerical analysis. From a close analysis of the output characteristics, we have distinguished two saturation regimes: the first related to the conventional formation of the pinch-off region near the LDD, the second one, occurring at higher source-drain voltages, related to the depletion of the LDD region. Impact ionization effects have been also analysed and kink effect in GOLDD structure has been found to be associated with the parasitic bipolar transistor action, similarly to silicon-on-insulator (SOI) devices. At very high source-drain voltages, avalanche breakdown occurs, due to impact ionization occurring at both channel/LD-region and LD-region/n+ region junctions.

Gate-overlapped lightly doped drain poly-Si thin-film transistors for large area-AMLCD

We have fabricated a gate-overlapped lightly doped drain (GO-LDD) polycrystalline silicon thin-film transistor (poly-Si TFT) applicable for large area AMLCD by employing the uniform and low-temperature doping techniques, such as ion shower doping and in situ doping. Experimental results show that the leakage current of the proposed TFT's is reduced by more than the magnitude of two orders, compared with that of conventional nonoffset TFT, while the ON current is scarcely decreased. It is verified by the device simulator that the electron concentration in the LDD region is increased under the ON state and decreased under the OFF state due to the field plate with gate potential over the LDD region. Furthermore, the vertical peak electric field in the LDD region is decreased significantly by the extended field plate potential during the OFF state. It is observed that the gate bias stress degrades significantly the subthreshold slope of the ion shower doped GO-LDD TFT's at the low drain bias but does not degrade the device characteristics of those with in situ doping due to the high-quality TEOS SiO/sub 2/ interlayer.

Analysis of Drain Field and Hot Carrier Stability of Poly-Si Thin Film Transistors

Hot carrier instabilities in poly-Si thin film transistors (TFTs) are caused by high electric fields at the drain. These high fields are determined mainly by the abruptness of the lateral n+ doping profile in the drain and the two-dimensional (2D) coupling of the x and y components of the electric field between the gate and drain. The density of trapping states in the poly-Si film, however, has a much less significant impact on the field. Further, it is shown that improving the properties of the poly-Si film tends to have an adverse affect on hot carrier stability. Consequently, it is concluded that drain field relief is essential for hot carrier stability of n-channel poly-Si TFTs. It is shown that gate overlapped lightly doped drain (GOLDD) architectures can be used to relieve the drain field without introducing series resistance. Stable TFTs have been fabricated with GOLDD, consistent with circuit operation up to drain biases of 20 V. GOLDD is also effective in reducing the field enhanced leakage current in the off-state.

Gate-Overlapped Lightly Doped Drain Poly-Si Thin Film Transistors by Employing Low-Temperature Doping Techniques

We have fabricated a gate-overlapped lightly doped drain (GO-LDD) polycrystalline silicon thin film transistor (poly-Si TFT) applicable for large area AMLCD by employing the large area- and low-temperature-doping techniques, such as ion shower doping and in-situ doping. Experimental results show that the leakage current of the proposed TFTs is reduced by more than the magnitude of two orders, compared with that of conventional non-offset TFT, while the ON current is scarcely decreased. The degradation phenomena after gate bias stress in GO-LDD TFTs with in-situ doping has not been found because the electron trapping into the overlayer may be suppressed effectively by the high quality TEOS interlayer.

A Novel LDD-Structured Poly-Si Thin Film Transistors with High ON/OFF Ratio

We have fabricated a new polycrystalline silicon thin film transistor (poly-Si TFT), entitled a gate-overlapped lightly doped drain (GO-LDD) TFT, which may reduce the leakage current without sacrificing the ON current. Both the source/drain and LDD region of GO-LDD TFT are formed simultaneously by employing the buffer oxide without any additional LDD doping. Experimental results show that the leakage current of the proposed TFTs is decreased by the magnitude of two orders without sacrificing the ON current. The low-temperature ion shower doping is also employed to fabricate both the source/drain and LDD in the GO-LDD TFTs without a troublesome ion implantation.