Gate MOSFET Research Articles

A Simple Proposal to Reduce Self-heating Effect in SOI MOSFETs

In this work, we aim to design a silicon on insulator MOSFET in which the self-heating effect is fully removed. Within the proposed scheme, a T-shaped 4H-SiC region is embedded in the buried oxide layer, extended from the silicon drift region towards the substrate providing a heating pathway to improve the low thermal conductivity of the oxide. This T-shaped 4H-SiC part can absorb heat from the active region and transfer it to the substrate area. Therefore, heat dissipation rising from the high gate and drain bias in MOSFETs are reduced. Simulations show that in addition to the maximum lattice temperature that is brought from ~ 694 K to ~ 366 K, DC and AC characteristics of the device have also improved drastically. The proposed transistor demonstrates lower negative differential resistance, more carrier mobility, higher saturation current, higher DC Transconductance, less delay time, and higher cut-off frequency compared to conventional silicon on insulator MOSFET. These promising properties and competitive advantages propose the designed device as a reliable alternative for conventional MOSFETs in high power and RF applications.

Drain Current Modelling of Asymmetric Junctionless Dual Material Double Gate MOSFET with High K Gate Stack for Analog and RF Performance

This paper presents the continuous 2D analytical modelling of electrostatic potential, threshold voltage (Vth), subthreshold swing, drain induced barrier lowering (DIBL) and drain current of asymmetric junctionless dual material double gate MOSFET with high K gate stack (AJDMDG Stack MOSFET). The electrostatic potential is achieved by solving Poisson’s equation with the help of the parabolic approximation method. Analytical results are verified by using ATLAS TCAD Device simulator. A comparative study of short channel effects (SCEs) of AJDMDG Stack MOSFET and asymmetric junctionless dual material double gate MOSFET with high K gate stack (SJDMDG Stack MOSFET) has been observed in order to show the efficacy of asymmetry condition such as gate oxide asymmetry, gate work function asymmetry etc. for suppressing SCEs. Further, analog/RF performance parameters such as transconductance (gm), output resistance (rout), intrinsic gain, transconductance generation factor (TGF), cut-off frequency (fT), maximum frequency (fmax), gain bandwidth product (GBW) etc. of AJDMDG Stack MOSFET are observed and compared the results with SJDMDG Stack MOSFET structure. Results reveal that AJDMDG Stack MOSFET has better efficacy for RF applications.

Analysis of black phosphorus double gate MOSFET using hybrid method for analogue/RF application

In this work, the authors study the performance of black phosphorus double gate MOSFET (BP-DGMOSFET) within the ballistic limit. A hybrid simulation technique involving both atomistic and technology computer-aided design (TCAD) tool has been used for the first time to simulate the device characteristics. First, the density functional theory has been used to simulate the electrical characteristics of single and fewlayer (five layers) phosphorene (including armchair and zigzag directions). The parameters such as bandgap and effective mass obtained using an atomistic simulator tool are exported into Sentaurus TCAD to simulate the BP-DGMOSFET characteristics. They have used the kinetic velocity model and quantum model to account for the ballistic mobility and quantum effects in the device. The current drain characteristics are calibrated with non-equilibrium Greens function (NEGF) simulation and radio frequency (RF) characteristics with compact model values and found that their results agree with them. Secondly, the other RF figure of merits, such as maximum frequency of oscillation, transconductance, output conductance and stability has also been simulated. It is found that their proposed method shows results comparable to NEGF with reduced computation time and complexity.

Simulation of the Nanoscale Joint Surrounding Gate SOI MOSFET Characteristics

In order to solve the current problem of increasing the efficiency of modern electronic circuits, the applicability of a nanoscale joint surrounding gate MOSFET with oval work area is discussed. The design and principle of its operation are considered. This concept involves of jointing the working areas of n-channel and p-channel MOSFETs. In fact, the JSMOSFET consists of two "glued" along the halves of MOSFETs: one - nchannel and the other - p-channel, but with one common gate. We analyze the applicability of the design of an oval-shaped protected area. In our case, the contact of two heterogeneously doped regions occurs in the plane passing through the small axis of the oval. The main channels are formed in zones associated with the large axis of the oval. This achieves the main goalincreasing the number of charge carriers. At the same time, the efficiency of short-channel effect suppression is maintained and a high current level of the transistor is provided in the strong inversion mode. By the developed TCAD model of a nanoscale joint surrounding gate MOSFET with an oval work area the electrophysical characteristics of several prototypes with different transverse dimensions were numerically calculated at a supply voltage of 0.5 V. From the simulation results, it follows that all prototypes are low-voltage devices that can function at voltages below 0.5 V in the gigahertz frequency range with a high gain. The proposed devices perform the function of inverting the input signal without distortion. From the comparison of modeling data, the scope scaling capabilities are determined. The obtained results create prerequisites for the development of the proposed transistor architecture, since electronic chips created on their basis will differ in low power supply voltage, high performance, and minimal occupied area, which meets modern requirements for transistors for analog and digital applications.

True Origin of Gate Ringing in Superjunction MOSFETs: Device View

As superjunction devices are scaled down to smaller dimensions, the gate ringing becomes more prominent in dynamic switching. The exact origin of superjunction MOSFET's gate ringing has not been so far identified as the conventional three-terminal measurement method cannot capture the dynamic behavior of the device, in particular the redistribution of charge between the different internal capacitive components in the superjunction structure. In this article, it is found that the gate ringing is highly related to the input capacitance. Specifically, by employing a TCAD model with a split gate method, the gate-to-source (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ) and gate-to-drain (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> ) current are investigated during the dynamic transitions. The gate ringing is highly dependent on sum of the input capacitances (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> + C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> ) for the turn-on. In the case of the turn-off, however, the gate ringing is affected by the ratio of the input capacitances (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> /C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ) and a lower CGS is desirable for a low gate oscillation.

Effect of size quantization and quantum capacitance on the threshold voltage of a 2D nanoscale dual gate MOSFET

The size quantization effect in the channel of a 2D nanoscale MOSFET is studied using a self-consistent quantum method. Under this, Schrodinger-Poisson equations are solved for determining the electron density for 2D device channels from 3 nm × 3 nm to 100 nm × 100 nm. The lower dimension channels show a peak of the electron density at the middle whereas higher dimension channels show the accumulation of the electrons at the oxide/semiconductor interface. Also, the role of quantum capacitance on the threshold voltages of these nanoscale devices is investigated as a function of channel dimensions and electron effective masses. It is observed that not only the size but the electron effective masses dominate the conductivity of the channel for such nanoscale devices. Here, the channel electron densities are obtained using density matrix formalism. A block diagonal Hamiltonian Matrix [H] is constructed for this oxide/channel/oxide 2D structure and the channel is discretized by using the finite-difference method. This analysis is important for understanding the physics of the size quantization and its effect on the threshold voltage.

Analytical Modeling of D.C. Parameters of Double Gate Junctionless MOSFET in Near and Subthreshold Regime for RF Circuit Application

Aims:: In this work, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. Background:: D.C. performances like power, delay and voltage swing of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short-channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Objective:: Impact of supply voltage, temperature, High-k gate oxide, TOX, TSI on the power, delay and voltage swing of the Inverter circuits have been detailed here. Methods: Extensive simulations using SILVACO ATLAS have been done to validate the proposed logic based digital circuits. Besides, the optimum supply voltage has been modelled and verified through simulation for low voltage operations. In depth analysis of voltage swing is added to measure the noise immunity of the proposed logic based circuits in Sub &amp; Near-threshold operations. For ultra-low power operation, JLDG MOSFET can be an alternative compared to conventional planar MOSFET. Result:: Hence, the analytical model of delay, power dissipation and voltage swing have been proposed of the proposed logic based circuits. Besides, the ultra-low power JLDG CMOS inverter can be an alternative in saving energy, reduction of power consumption for RFID circuit design where the frequency range is a dominant factor. Conclusion:: The power consumption can be lowered in case of UHF, HF etc. RF circuits using the Double Gate Junction-less MOSFET as a device for circuit design.

МОДЕЛИРОВАНИЕ ПАРАЗИТНЫХ ТУННЕЛЬНЫХ ТОКОВ В ЭЛЕМЕНТАХ ФЛЕШ-ПАМЯТИ НА ОСНОВЕ КОРОТКОКАНАЛЬНЫХ МОП-ТРАНЗИСТОРОВ

Simulation of parasitic currents in Flash-memory cells based on short-channel MOSFET. In present paper the distributions of parasitic tunneling current as well as mean electron energy and mobility along the channel are calculated for short-channel MOSFETs by using Monte Carlo simulation of electron drift in such devices. The effect of drain bias in Flash-memory cells on these distributions is investigated for reading information regime. It is shown that the value of parasitic current is very small at considered conditions. But long storage can be change the charge in a floating gate of short-channel MOSFETs.

Analytical modeling of subthreshold current and swing of strained‐Si graded channel dual material double gate MOSFET with interface charges and analysis of circuit performance

AbstractIn this paper, a two‐dimensional (2‐D) center channel potential based subthreshold current (SC) and subthreshold swing (SS) are developed analytically for strained‐Si (s‐Si) graded‐channel dual‐material double gate (GC‐DMDG) MOSFET with interface charges. The proposed analytical model is extracted by solving 2‐D Poisson equation in s‐Si graded‐channel using appropriate boundary conditions. The analytical 2‐D model includes effects of various MOSFET parameters such as s‐Si channel length, strain in the silicon substrate, and oxide interface charge density with damaged length by extensively analyzing channel potential, SC, and SS. Also, the subthreshold characteristics of the proposed s‐Si GC‐DMDG MOSFET demonstrate superior performance over s‐Si graded channel double gate MOSFET. The numerical results obtained using TCAD of the proposed DG MOSFET are validated with the results attained from proposed analytical model. Moreover, the performance of CMOS inverter using s‐Si GC‐DMDG MOSFET is evaluated for different device parameters. It is investigated that the proposed s‐Si GC‐DMDG MOSFET has better noise margin than s‐Si GC‐DG MOSFET.

Investigation of Single Event Transient Effects in Junctionless Accumulation Mode MOSFET

The Junctionless Accumulation Mode Double Gate MOSFET (JAM DG MOSFET) is a promising novel architecture for future nano-scaled devices because of its outstanding electrical characteristics, e.g., lower subthreshold swing, lower drain induced barrier lowering, i.e., lower short channel effects and higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio. In this paper, a comprehensive analysis of the effects of single-event transient on JAM DG MOSFET has been performed using the sentaurus TCAD simulator. The result shows that the transient drain current peak obtained after the heavy-ion strike for JAM DG MOSFET is small at lower value linear energy transfer (LET) and high for the larger value of LET. Collected charge at different LET values has also been investigated. Moreover, the sensitive region of the device, e.g., source to channel junction, channel, and channel to drain junction has been studied. It has been found that the drain to channel junction is more sensitive to the linear energy than the channel and source to channel junction. The electrical characteristics have also been compared with JL DG MOSFET.

A 2D Analytical Modeling and Simulation of Double Halo Triple Material Surrounding Gate (DH-TMSG) MOSFET

In the nanoscale regime, scaling is the driving force for the miniaturized device applications. Many devices are scaled in size and performance analyses are measured. The scaling of MOSFET leads to the introduction of short channel effects. As the devices are scaled, the magnitude of these short channel effects hinders the performance of the device. In order to minimize these effects, gate engineering and channel engineering are performed. The modification in the gate material is pronounced as gate engineering and the changes in the doping concentration lead to channel engineering. In this paper, a combination of gate and channel engineering is utilized to reduce the short channel effects. A device called double halo triple material surrounding gate(DH-TMSG) MOSFET is introduced for the first time and its 2D analytical model is derived. The performance of the device is analyzed using TCAD ATLAS simulation tool. It has been found from the simulation results that DH-TMSG structure of MOSFET produce the ION current of 10−3A/μm and IOFF current of 10−12A/μm which proves to reduce the leakage current.

Palladium-based trench gate MOSFET for highly sensitive hydrogen gas sensor

This paper presents, Palladium-based Trench Gate MOSFET (TG-MOSFET) for the detection of hydrogen gas. The sensing mechanism occurs with the dissociation of hydrogen molecules into hydrogen atom and then diffuses into the palladium gate. Thereafter, owing to the polarization of the hydrogen atom, the dipole layer is formed at the palladium-oxide (SiO2) interface. From the perspective of a highly sensitive gas sensor, it is observed that the proposed device has very high sensitivity (105 A/A) for different gas pressure applying onto the device. Further, the gate bias dependent sensitivity of the device has been analyzed in terms of change in threshold voltage (ΔVth), surface potential, energy band, and transconductance for the entire range of gas pressure. Furthermore, the device stability is presented and the impact of temperature has also been investigated on the sensing performance of the device. Result reveals that the proposed device is highly sensitive for the detection of hydrogen gas.

MOSFETs’ Electrical Performance in the 160-nm BCD Technology Process With the Diamond Layout Shape

This article introduces an innovative approach that describes the drain–source current improvements of MOS transistors. It is based on the geometrical modification of MOSFET’s channel from a rectangular layout shape (RLS) into a diamond layout shape (DLS). In this way, the drain–source current enhancement is increased up to 11% for the DLS MOS transistors with an effective aspect ratio ( ${W}/\textit {L)}_{\mathrm {eff}}$ equal to 2.0 and an angle $\alpha $ set to 80°. Moreover, we present the comparison of 3-D TCAD simulations data, analytical model data based on Schwarz–Christoffel transformation (SCT), and measurement data given by measurement of the MOS transistors fabricated in the Bipolar-CMOS-DMOS (BCD) 160-nm technology process. For this purpose, there have been fabricated 1124 samples, which were proportionally divided into RLS MOSFETs and DLS MOSFETs with the angles $\alpha $ equal to 120°, 100°, and 80°. For all studied aspect ratios, the presented model has an excellent analytic description in comparison with the 3-D TCAD simulation results with an error lower than 3%. So, it proves the quality of the analytical model based on the SCT approach and it is the recommended approach to use also for modeling other MOSFET gate layout shapes.

A Cap-less Voltage Spike Detection and Correction Circuit for Low Dropout Regulator

A cap-less voltage spike detection and correction circuit for flipped voltage follower (FVF)-based low dropout regulator (LDO) is proposed in this paper. The transients in the output voltage are controlled by the pull-up currents [Formula: see text] and [Formula: see text] and pull-down currents [Formula: see text] and [Formula: see text]. These currents are dynamic current sources which are activated only during transient period and noise contributed by these current sources at steady state is zero. These currents increase/decrease based on the intermediate FVF node voltage [Formula: see text]. The proposed circuit detects the output voltage via [Formula: see text] and controls the power MOSFET gate and output capacitances by changing the pull-up and pull-down currents whenever the load changes. The proposed circuit consumes small additional bias current in the steady state and achieves less settling time and output spike voltage. This LDO is simulated using 180[Formula: see text]nm technology and the simulation result shows that the LDO has good load transient response with 190[Formula: see text]ns settling time and 170[Formula: see text]mV voltage spike over 1[Formula: see text]mA to 100[Formula: see text]mA load current range.

Online Detection of MOSFET Gate Oxide Degradation in a Three-Phase Inverter-Drive Application

Failure in electrical machines or their drives can be catastrophic in safety-critical applications. Both silicon and silicon-carbide MOSFETs experience gate oxide degradation that leads to device failure. It is ideal to detect gate oxide degradation early using noninvasive, online techniques. In this article, an online gate oxide degradation detection method is proposed to reduce the reliability concern of using MOSFET switching devices. Gate oxide degradation causes a delay in phase current rise. Although the delay is short, it affects the voltage commands calculated in the controller. It is shown through analysis, simulation, and experiment that space vector pulsewidth modulation (SVPWM) duty cycle commands reflect the delay in phase current rise caused by gate oxide degradation.

Modeling source/drain lateral Gaussian doping profile of DG-MOSFET using Green’s function approach

Present work has used Green’s function approach to derive a two-dimensional analytical model of the double gate (DG) MOSFET at the subthreshold regime of operation that considers the effect of inevitable source/drain (S/D) lateral Gaussian doping profile. The non-integrable Gaussian term has been converted into an integrable function for accurate Fourier coefficient calculation which is then used to determine the potential equations of all three regions. These equations are then utilized to formulate channel current (Isub), the threshold voltage (Vt) roll off and subthreshold slope (SS) of the device. The effects of lateral Gaussian profile at different gate length (L), and for devices with different combinations of oxide thickness (tox) and channel thickness (tsi) have been investigated. The results show that the S/D Gaussian doping profile has severe effects at scaled gate lengths, where gate electrostatic control is of paramount importance.

Effect of Gate Engineering and Channel Length Variation in Surrounding Gate MOSFETs

In this paper, the digital and analog performance for Double Material Gate Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (DM SG MOSFET) has been analyzed. A detailed study of DM SG MOSFET is performed for different channel length ratio's. The comparison analysis on surface potential, electric field, transfer characteristics, output characteristics, transconductance and output conductance is carried with respect to the silicon dioxide and hafnium dioxide based device. It has been found from the simulation results that HfO2 dielectric used DM SG TFET provides better performance than SiO2 dielectric used DM SG TFET. Also it has been observed from the presented results that the transconductance is 45.32 at 1:3 channel length ratio for DG SG MOSFET.

Oxide Edge Trap Density Extraction in Silicon Nanowire MOSFET From Tunnel Current Noise Measurement in Gated Diode Like Arrangement

Edge traps in the gate oxide of silicon nanowire MOSFETs have been extracted from tunnel current noise measurement in a gated diode like arrangement. We have found that, low frequency noise in tunnel current results from collective response of the edge traps available within the gate oxide surrounding band-to-band generation (BTBG) region of silicon nanowire, and when the BTBG region is accessed by favorable terminal biases. From detail modeling of the phenomenon, we derived a closed form expression of the tunneling current noise power spectral density (PSD) employing which oxide edge trap density in nanowire MOSFET had been extracted through its fit with the experimental noise PSD data. We furthermore validated our model for different BTBG biases, and contrasted our result with the bulk oxide trap density in identical MOSFET, while the latter was separately estimated from the gate current noise PSD measurement. Mismatch between the oxide bulk trap and edge trap concentrations has been found, whereby actual edge trap density remains otherwise hidden from the widely employed gate current noise measurement technique. It is because, the present scheme improves the resolution of the extracted oxide edge trap concentration in surrounded gate MOSFET owing to constricted tunnel current flow near the corner of the gate which imposes selectivity on the oxide edge traps

Analysis of gate engineered asymmetric junctionless double gate MOSFET for varying operating conditions

In this paperan asymmetrical junctionless double-gate MOSFET(AJDG-MOSFET) has been analyzed using different gate oxide material like SiO2 and HfO2 and different gate contact material like aluminium, copper and polysilicon. To check the sensitivity of AJDG-MOSFET, a temperature analysis has been performed at a different temperature ranging 250-400K. The performance of AJDG-MOSFET is analyzed with transfer and output characteristics using 2D/3D simulation on Cogenda TCAD. The device performs better using HfO2 as gate oxide and polysilicon as gate contact. The ideal subthreshold performance (DIBL=65mV/V, SS=68 mV/decade) is observed with a high value of Ion/Ioff(∼1012) for 300K temperature. The analysis for temperature shows a very small variation in OFF current and found suitable for low power applications.

A review on performance comparison of advanced MOSFET structures below 45 nm technology node

CMOS technology is one of the most frequently used technologies in the semiconductor industry as it can be successfully integrated with ICs. Every two years the number of MOS transistors doubles because the size of the MOSFET is reduced. Reducing the size of the MOSFET reduces the size of the channel length which causes short channel effects and it increases the leakage current. To reduce the short channel effects new designs and technologies are implemented. Double gate MOSFET design has shown improvement in performance as amplifiers over a single MOSFET. Silicon-based MOSFET design can be used in a harsh environment. It has been used in various applications such as in detecting biomolecules. The increase in number of gates increases the current drive capability of transistors. GAA MOSFET is an example of a quadruple gate around the four sides of channel that increases gate control over the channel region. It also increases effective channel width that improves drain current and reduces leakage current keeping short channel effects under limit. Junctionless MOSFET operates faster and uses less power with increase in ON-state current leading to a good value of ION/IOFF ratio. In this paper, several gate and channel engineered MOSFET structures are analyzed and compared for sub 45 nm technology node. A comparison among different MOSFET structures has been made for subthreshold performance parameters in terms of IOFF, subthreshold slope and DIBL values. The analog/RF performance is analyzed for transconductance, effective transistor capacitances, stability factor and critical frequency. The paper also covers different applications of advance MOSFET structures in analog/digital or IoT/ biomedical applications.