Gate Metal Workfunction Engineering Research Articles

Design and analysis of dopingless 1T DRAM using work function engineered tunnel field effect transistors

In this paper, a dopingless DRAM based on work function engineered Tunnel field effect transistor is proposed. Gate metal workfunction engineering is done to enhance ON/OFF current ratio of drain current, thereby improving the sense margin and retention time. Drain electrode is made up of dual metal, so as to suppress ambipolar current. The analysis of dual material gate dual drain electrode DRAM (DMG DDE DRAM) and triple material gate dual drain electrode DRAM (TMG DDE DRAM) is done in terms of retention time and sense margin. The performance parameters with different device dimensions and bias conditions are analyzed. It is observed that the proposed DRAMs work well even when the dimensions are scaled down. In addition, the proposed DRAMs have comparable performance with the conventional DRAMs and provide better performance when compared with other dopingless DRAM. Retention times of 430 ms and 370 ms, sense margins of 130 nA and 101 nA are achieved with TMG DDE DRAM and DMG DDE DRAM respectively.

Design and simulation of triple metal double-gate germanium on insulator vertical tunnel field effect transistor

In this paper, a novel Triple metal double gate germanium on insulator vertical TFET is proposed and investigated by using SILVACO ATLAS TCAD tool. Gate metal work-function engineering is used to overcome the problem of low ON-current, high OFF-current, high average subthreshold swing and low ION/IOFF ratio which are present in single material double gate TFET. By modulating the values of metal gate work-functions, the performance of the device is improved. The low band-gap material and vertical tunneling concept also increase the steepness of subthreshold slope as well as ON-current of the device. Further the effects of channel length and gate to source overlap thickness on the device are also analysed to get optimum device dimensions for obtaining the improved performance results. The vertical stacking of source, channel and drain also consumes less space as compared to the conventional TFETs. So, the considerable good performance of this proposed device makes it suitable as an attractive choice for ultra-low power applications.

Performance analysis of double-metal-gate dual-cavity dielectrically modulated-TFET as a label free biosensor

In this paper, a double metal gate dual cavity dielectrically modulated tunnel field effect transistor (DMG-DC-DMTFET) biosensor is proposed. The On and ambipolar currents of the device are used for detection of various biomolecules. The cavities, where biomolecules get immobilized are considered at both source-channel and drain-channel junctions of TFET in order to utilize ambipolar nature of TFET to detect the presence of biomolecules in an efficient way. Sensitivity improvement and reduction in Off current at higher dielectric constant of biomolecules are done by considering the gate metal work function engineering. The effect of charged and neutral biomolecules on band energy, transfer characteristics and electric field has been analyzed.

Design and Analysis of IGZO Based Junctionless Thin Film Transistor Using SOI Technology

In this paper, IGZO based Junctionless Thin Film Transistor (IGZO JLTFT) using SOI technology is proposed with a channel length of 20 nm. The article also demonstrates a comparative analysis of amorphous Silicon-based JLTFT and artificial material IGZO based JLTFT using the Silvaco Atlas tool. Based upon the Junctionless properties, the compound, and high bandgap material, Indium Gallium Zinc Oxide (IGZO) is used to overcome the Short Channel Effects (SCEs) caused due to continuous miniaturization of the channel size. Optimization of the proposed SOI based IGZO JLTFT device has been carried out, by varying the Buried oxide and gate oxide materials and their thicknesses, and HFO2 has been demonstrated to give the best Ion/Ioff ratio. Further, gate metal work-function engineering is employed to enhance the performance of the proposed device in terms of increasing on-state current, and reducing off-state current. Through rigorous simulations with variations in different device parameters, it is demonstrated that the 20 nm IGZO JLTFT with HfO2 as Buried and Gate oxides, and work functions of 4.8 eV each for both metal gates, provides the best performance such as: Ioff of 9.97*10−12 A, threshold voltage of 0.38 V, overall gate capacitances of 1.13*10−15 F, and Subthreshold Slope (SS) of 93 mV/dec.

Performance investigation of heterogeneous gate dielectric-gate metal engineered–gate all around-tunnel FET for RF applications

In this work, the effect of gate metal work function engineering (GME), gate bias and drain bias on the bias dependent parasitic capacitances has been studied. Further, RF Figure of merits (FOMs) such as power gains, cut-off frequency (fT), maximum oscillation frequency (fMax) and intrinsic delay of hetero-dielectric gate-metal-engineered gate-all-around tunnel FET (HD-GME-GAA-TFET) are studied and compared with HD-GAA-TFET. Simulation results show an appreciable improvement in RF FOMs with the application of GME architecture on GAA TFET. Further, it has been observed that GME exhibits 3.76 times enhancement and 0.017 times reduction in cut-off frequency and intrinsic delay respectively as we increase the work function difference, which makes it a promising candidate for low power switching applications. Moreover, the small signal Y-parameters have also been studied which indicates that HD-GME-GAA-TFET is a promising candidate for RF/microwave applications. All the simulations have been done using ATLAS device simulator.

Optimization of high-k and gate metal workfunction for improved analog and intermodulation performance of Gate Stack (GS)-GEWE-SiNW MOSFET

This work optimizes the gate engineering scheme (both gate stack and gate metal workfunction engineering) of Stacked Gate (SG) Gate Electrode Workfunction Engineered (GEWE)-Silicon Nanowire MOSFET at 300 K for improved analog and intermodulation performance. This has been done by evaluating and analyzing the metrics such as Switching Ratio, Subthreshold Swing (SS), Device Efficiency, channel and output resistance, VIP3, IIP3, 1-dB Compression Point, IMD3, HD2 and HD3. Simulation results exhibit that HfO2 as a gate stack exhibit high linearity at a comparatively low gate bias of 0.56 V with higher IIP3 (6.21 dBm) and low IMD3 (9.6 dBm). Further, the characteristics/performance is modulated by adjusting the workfunction difference of metal gate. This study demonstrates that SiNW MOSFET modeled with HfO2 as a gate stack over SiO2 interfacial layer, and gate metal workfunction difference (ΔW) of 4.4 eV can be considered as a promising potential for low power switching component in ICs and Linear RF amplifiers.

Influence of gate metal engineering on small-signal and noise behaviour of silicon nanowire MOSFET for low-noise amplifiers

In this paper, we have investigated the small-signal behaviour and RF noise performance of gate electrode workfunction engineered (GEWE) silicon nanowire (SiNW) MOSFET, and the results so obtained are simultaneously compared with SiNW and conventional MOSFET at THz frequency range. This work examines reflection and transmission coefficients, noise conductance, minimum noise figure and cross-correlation factor. Results reveal significant reduction in input/output reflection coefficient and an increase in forward/reverse transmission coefficient owing to improved transconductance in GEWE-SiNW in comparison with conventional counterparts. It is also observed that minimum noise figure and noise conductance of GEWE-SiNW is reduced by 17.4 and 31.2 %, respectively, in comparison with SiNW, thus fortifying its potential application for low-noise amplifiers (LNAs) at radio frequencies. Moreover, the efficacy of gate metal workfunction engineering is also studied and the results validate that tuning of workfunction difference results further improvement in device small-signal behaviour and noise performance.

Ballistic Performance Study of Nanowire FET: Effect of Channel Materials and Phonon Scattering

The ballistic performance of Si and Ge nanowire (NW) is compared in this study. Current–voltage characteristic is obtained by self-consistently solving the nonequilibrium Green’s function (NEGF) transport equation with Poisson’s equation. The result is obtained at [Formula: see text] channel orientation. Simulation result shows Ge NW gives higher ON-state current than Si NW, when OFF-state current is made equal by gate metal work function engineering. However, at subthreshold region, performance of NW FET for both material is almost identical. The intravalley and intervalley electron–phonon scattering effect is also calculated using the deformation potential theory and the self-consistent Born approximation. It is found that electron–phonon scattering effect is more pronounced at ON-state of Si NW FET. The ballistic current decreases with the decrease in diameter of the Si NW FET due to electron–phonon scattering.

Impact of device parameter variation on RF performance of gate electrode workfunction engineered (GEWE)-silicon nanowire (SiNW) MOSFET

In this paper, we explore the quantitative investigation of the high-frequency performance of gate electrode workfunction engineered (GEWE) silicon nanowire (SiNW) MOSFET and compared with silicon nanowire MOSFET(SiNW MOSFET) using device simulators: ATLAS and DEVEDIT 3D. Simulation results demonstrate the improved RF performance exhibited by GEWE-SiNW MOSFET over SiNW MOSFET in terms of transconductance $$(\hbox {g}_{\mathrm{m}})$$(gm), cut-off frequency $$(f_{\mathrm{T}})$$(fT), maximum oscillator frequency $$(f_{\mathrm{MAX}})$$(fMAX), power gains (Gma, G$${_\mathrm{MT}}$$MT) parasitic capacitances, stern's stability factor and intrinsic delay. Further, using three-dimensional device simulations, we have also examined the efficacy of parameter variations in terms of oxide thickness, radius of silicon nanowire, channel length and gate metal workfunction engineering on RF/microwave figure of merits of GEWE-SiNW MOSFET. Simulation result reveals significant enhancement in $$f_{\mathrm{T}}$$fT and $$f_{\mathrm{MAX}}$$fMAX; and a reduction in switching time in GEWE-SiNW MOSFET due to alleviated short channel effects, improved drain current and smaller parasitic capacitance, thus providing detailed knowledge about the device's RF performance at such aggressively scaled dimensions.

Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET

This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k=7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (gm), the gain per unit current (gm/Ids), the intrinsic gain (gmRo), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RF performance analysis. Analysis suggested that the average intrinsic gain, gm/Id and gm are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET.

Dual Material Double-Layer Gate Stack SON MOSFET: A Novel Architecture for Enhanced Analog Performance—Part I: Impact of Gate Metal Workfunction Engineering

In this paper, we present a simulation study, using ATLAS-2D, of analog circuit performance metrics for the dual-material gate (DMG) MOSFETs in Part I. Part II focuses on the impact of double-layer gate stack architecture on the analog performance and fT-gain relationship of the silicon-on-nothing MOSFETs with and without DMG. The simulation results in Part I demonstrate that, out of the several combinations in DMG MOSFET design studied, the DMG device with an LM1/L ratio of frac12 amalgamates the advantages of using a high metal workfunction gate M1 and a low metal workfunction gate M2 in the most efficient manner. An increase in early voltage and a reduced output conductance from the DMG MOSFET design are the driving forces for the observed performance improvement.