Gate Metal Oxide Semiconductor Field Effect Transistor Research Articles

Exploring Intertwined quantum and cryogenic behaviour in ultra-scaled 10 nm MOSFET: a NEGF quantum ballistic simulation

Silicon-based spin qubits have emerged as promising candidates for scalable quantum information processing. This study first time investigates the behaviour of ultra-scaled 10 nm gate length and 3 nm channel thickness nanoscale double gate metal-oxide semiconductor field-effect transistors (MOSFETs) over a broad temperature range, from deep cryogenic (4 K) to room temperature (300 K). Employing the Non-Equilibrium Green’s Function (NEGF) method, the research explores the intertwined quantum and cryogenic behaviours of the various quantum phenomena, including eigen energies, eigen-functions, electron concentration, current characteristics, and more. This comprehensive analysis sheds light on the intricate interplay of quantum effects in nanoscale transistors under deep cryogenic conditions, offering valuable insights into the development of cryo-CMOS circuits for quantum computing.

Design and Performance Analysis of Logic Circuits using FinFET Technology

As the dimensions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) decreases, the short channel effect (SCE) becomes a dominating concern in VLSI. The Short channel effect causes an exponential increase in the leakage current. To reduce the SCE and hence leakage current, a new technology has been developed in recent years. In this recent technology a 3D multiple gate MOSFETs like FinFET (Fin Field Effect Transistor) has been developed which possess numerous advantages over conventional MOSFETs and has attracted many engineers and designers. FinFET is the new growing technology that works in the nm range to minimize short channel effects. Many companies (like Intel) have started using FinFET technology. This document is a review paper of current research on FinFET technology and discusses how it can be used in future to design new logic devices (like Adder, Comparator, MUX and De-MUX etc.) and memory devices. Various parameters of FinFET like reduced short channel effects, less leakage current, low power consumption, less propagation delay and less time delay are discussed. Various mathematical models and software (HSpice) were used to simulate power, delay, power delay product, average power dissipation and energy delay product. Thus, FinFET technology was designed to eliminate the problem of SCE by permitting transistors to be scaled down into sub 20nm range.

Influence of electron beam irradiation induced charging-effect on nanoprobing localization of a crystal defect in MOSFET

The paper demonstrates that the electron beam (e-beam) irradiation induced charging-effect has remarkable impact on nanoprobing localization of a crystal defect hidden in metal-oxide-semiconductor field-effect transistor (MOSFET). We present a practical example showing that device characterization at the contact layer (CT) is susceptible to the charging-effect since scanning electron microscopy (SEM) based nanoprobe system running is inevitablely acompanied by e-beam irradiation towards device under test (DUT). The mechanisms is seldomly reported in the past. In our case, the p-n junction at a nMOSFET drain end showed the ohmic current-voltage (I-V) characteristic at the beginning. However, by utilizing the atomic force microscopy (AFM) based nanoprobe system without e-beam, the measurement found previous resistive characteristic of the p-n junctions disappeared. Instead, it exhibited good rectifying characteristic. I-V characteristic discrepancy coming from two analytical methods was attributed to the charging-effect influence. It was experimentally proven that the charging-effect impact at MOSFET gate CT had strong dependance on the e-beam irradiation magnitude corresponding to the SEM scan speed. Charging effect produced distinct consequences at distinct scan speeds. The positive charging-effect occurred under the fast scan while the negative charging-effect occurred under the slow scan. The former mechanism made the potential at gate CT high enough to turn on nMOSFET. Therefore, the nMOSFET channel current merged with the p-n junction current in a closed-loop. In contrast, the slow scan induced negative charging-effect made the gate potential lower than the nMOSFET threshold voltage (VT), so that the nMOSFET stayed off-state. Consequently, the p-n junction resumed its intrinsic rectifying I-V characteristic. Different from the nMOSFET, the charging-effect affected the pMOSFET in the opposite manner. As a result, the initial conclusion of the MOSFET junction leakage was not valid. Next, we ran a optimal flow to narrow down a fault by eliminating the charging-effect impact. Eventually, a crystal defect (pipeline) was isolated in a suspcted nMOSFET relying on nanoprobe and TEM analysis. The article explains the evident influence of charging-effect on the nanoprobe analysis and puts forward an effective way to minimize the side effect of the e-beam irradiation. The work may draw more attention to the analytical methodologies regarding MOSFET reliability improvement.

Monitoring ammonia slip from large-scale selective catalytic reduction (SCR) systems in combined heat and power generation applications with field effect gas sensors

Abstract. Following tightened regulations, selective catalytic reduction (SCR) of nitrogen oxides (NOx) by ammonia (NH3) has over the last couple of decades found wider adoption as a means of reducing NOx emissions from e.g. power production and district heating plants. As in the SCR process NH3 injected into the flue gas reacts with and reduces NOx to nitrogen (N2) and water (H2O) on the surface of a specific catalyst, the NH3 injection has to be dynamically adjusted to match both instant and long-term variations in flue gas nitrogen oxide concentration in order to minimize NOx and NH3 emissions. One possibility of realizing such NH3 dosing control would be the real-time monitoring and feedback of downstream flue gas NOx and NH3 concentrations to the NH3 injection control unit. In this study the sensing characteristics and performance of SiC-based Metal Oxide Semiconductor Field Effect Transistor (MOSFET) sensors with a structurally tailored gas-sensitive gate contact of iridium (Ir) for in situ NH3 monitoring downstream from the SCR catalyst in a combined heat and power (CHP) plant have therefore been investigated and evaluated. The sensor's NH3 sensitivity and selectivity as well as the cross-sensitivity to common flue gas components – oxygen (O2), water vapour (H2O), nitric oxide (NO), nitrogen dioxide (NO2), carbon monoxide (CO), and a model hydrocarbon, ethene (C2H4) – were thereby investigated for relevant concentration ranges under controlled conditions in the laboratory. While, at the prescribed sensor operation temperature of 300 ∘C, the influence of H2O, CO, and C2H4 on the sensor's NH3 concentration reading could be regarded as practically insignificant, a moderate cross-sensitivity was observed between NH3 and NO2 and, to a lesser extent, between NH3 / NO and NH3 / O2. As the NOx concentration downstream from the SCR catalyst under normal SCR and power plant operation is expected to be considerably smaller than the NH3 concentration whenever any appreciable ammonia slip occurs, the observed NH3 / NOx cross-sensitivities may, however, be of less practical significance for ammonia monitoring in real flue gases downstream from the SCR catalyst. Furthermore, if required, the small influence of O2 concentration variations on the sensor reading may also be compensated for by utilizing the signal from a commercially available oxygen sensor. Judging from in situ measurements performed in a combined heat and power plant, the structurally tailored Ir gate field effect sensors also exhibit good NH3 sensitivity over the relevant 0–40 ppm range when directly exposed to real flue gases, offering an accuracy of ±3 ppm as well as low sensor signal drift, the latter most likely to further improve with regular zero-point calibration and thereby make the Ir gate MOSFET ammonia sensor a promising alternative for cost-efficient real-time ammonia slip monitoring or SCR system control in heat and/or power production plants.

Low Inductive Characterization of Fast-Switching SiC MOSFETs and Active Gate Driver Units

Accurate switching device characterization is necessary for effectively utilizing the technological ad-vantages of Silicon Carbide (SiC) Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) over their Silicon (Si) Insulated-Gate Bipolar Transistor (IGBT) counterparts. With switching times of few nanoseconds, the unprecedented switching speed of SiC semiconductor devices challenges today's converter and characterization setup designs in regard to parasitic layout inductances for optimal conversion and reliable characterization data. Fur-thermore, active gate driving is a key to unlock the potential of SiC MOSFETs, but requires performance assessment prior to integration. This paper presents a low-inductive test platform for flexible and high-accuracy characterization of fast-switching SiC MOSFETs and active gate drivers evalu-ation. The test circuit delivers high quality characterization data that is comparable with a commercial dynamic power device characterizer. In addition to the conventional hard-switching double-pulse tests with a two-level voltage source gate driver, the test circuit offers soft-switching and gate driver evaluation capability in addition. This test platform is a valuable tool for obtaining reliable characterization data to develop more accurate SiC MOSFET simulation models, and evaluate the combination of gate driver and MOSFET prior to the prototyping phase of a converter.

Investigation of 4H-SiC UMOSFET Architectures for High Voltage and High Speed Power Switching Applications

A comparative TCAD (Technology Computer Aided Design) simulation study of various 4H-SiC trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (or U-shaped trench gate MOSFET abbreviated for UMOSFET) architectures for high voltage and high-speed switching applications is reported. The DC (Direct Current) and AC (Alternating Current) characteristics of the different trench gate structures are investigated. Particularly, compared to conventional 4H-SiC UMOSFETs, the breakdown voltage of the UMOSFET having a p-type implanted bottom shield is increased by 44%. However, due to the extra JFET (Junction Field Effect Transistor) region, the specific on resistance also increases by 6%. Furthermore, under 1000 V drain bias, the peak electric field at the bottom oxide of the shielded trench gate is below 0.3 MV/cm. In contrast, the peak electric field of conventional UMOSFETs can be as high as 8 MV/cm, which might cause reliability issues. On the other hand, when the bottom oxide thickness of the trench gate is increased, the UMOSFET exhibits 22% less total gate charge, leading to 76% and 71% shorter switching delay time, compared to conventional UMOSFETs and bottom shield UMOSFETs, respectively. As revealed by the simulation results, the UMOSFETs with the p-type implanted bottom shield or thick bottom oxide are advantageous for high voltage and high-speed power switching applications.

Dependence of reverse leakage on the edge termination process in vertical GaN power device

The trench gate metal oxide semiconductor field effect transistor (MOSFET) represents a prominent device architecture among the Gallium Nitride (GaN) based vertical devices currently investigated for the next generation of power electronics. A low leakage current level in off-state under high drain bias is of great importance for vertical transistors since it is a crucial feature for high breakdown voltage and device reliability. The off-state drain leakage originates from different sources in the vertical trench gate MOSFET. Besides the trench gate module, the leakage paths at the dry-etched sidewall of the lateral edge termination can also significantly contribute to the off-state drain-current. In this report, the influence of each relevant process step on the drain leakage current in off-state that is related to the lateral edge termination is investigated utilizing specific test structures on high-quality GaN epitaxial material which mimic the lateral edge termination of the MOSFET. Electrical characterization reveals the sensitivity of the leakage current to plasma-related processes. A termination technology is presented that results in low leakage current while including thick dielectric layers from plasma-assisted deposition as intended for fabrication of a field plate structure over the edge termination.

A 4H-SiC semi-super-junction shielded trench MOSFET: p-pillar is grounded to optimize the electric field characteristics

A 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor (UMOSFET) with semi-super-junction shielded structure (SS-UMOS) is proposed and compared with conventional trench MOSFET (CT-UMOS) in this work. The advantage of the proposed structure is given by comprehensive study of the mechanism of the local semi-super-junction structure at the bottom of the trench MOSFET. In particular, the influence of the bias condition of the p-pillar at the bottom of the trench on the static and dynamic performances of the device is compared and revealed. The on-resistance of SS-UMOS with grounded (G) and ungrounded (NG) p-pillar is reduced by 52% (G) and 71% (NG) compared to CT-UMOS, respectively. Additionally, gate oxide in the GSS-UMOS is fully protected by the p-shield layer as well as semi-super-junction structure under the trench and p-base regions. Thus, a reduced electric-field of 2 MV/cm can be achieved at the corner of the p-shield layer. However, the quasi-intrinsic protective layer cannot be formed in NGSS-UMOS due to the charge storage effect in the floating p-pillar, resulting in a large electric field of 2.7 MV/cm at the gate oxide layer. Moreover, the total switching loss of GSS-UMOS is 1.95 mJ/cm2 and is reduced by 18% compared with CT-UMOS. On the contrary, the NGSS-UMOS has the slowest overall switching speed due to the weakened shielding effect of the p-pillar and the largest gate-to-drain capacitance among the three. The proposed GSS-UMOS plays an important role in high-voltage and high-frequency applications, and will provide a valuable idea for device design and circuit applications.

Ultrasensitive Perovskite Photodetector Achieved When Configured with a Si Metal Oxide Semiconductor Field‐Effect Transistor

A novel photodetecting device architecture that combines the optoelectronic property advantages of a perovskite and the amplification properties of a Si metal–oxide–semiconductor field‐effect transistor (MOSFET) to innovate a photodetecting system with ultrahigh sensitivity, especially in low‐light intensity, is demonstrated. This perovskite‐based MOSFET photodetector (PM‐PD) can respond as low as 116 nW cm−2 with extremely high responsivity 4200 A W−1. The perovskite is part of the gate dielectric to modulate the MOSFET drain current when the light intensity is changed. A direct bandgap, organic–inorganic hybrid halide perovskite with a large optical absorption coefficient, can enhance photodetector performance. However, perovskite materials are not good conductors for transporting photogenerated electrons and holes compared with single‐crystal silicon. Therefore, the perovskite was utilized as a dielectric where the capacitance is used instead. In the proposed PM‐PD architecture, changing the width‐to‐length (W/L) ratio of perovskite capacitor electrodes, can modulate the dark current from picoamperes to microamperes providing a tunable parameter for optimizing photodetecting performance. Furthermore, the capacitance of the perovskite can be modulated by frequency, which facilitates matching the capacitance of perovskite and MOSFET gate oxide—another important requirement for optimal photodetecting performance. Finally, our novel PM‐PD is commensurate with potential 3D monolithic integration.

High performance SiC trench-type MOSFET with an integrated MOS-channel diode

A novel SiC double-trench metal-oxide-semiconductor field effect transistor (MOSFET) with integrated MOS-channel diode is proposed and investigated by Sentaurus TCAD simulation. The new SiC MOSFET has a trench gate and a stepped-trench source, and features an integrated MOS-channel diode on the top sidewall of the source trench (MT MOS). In the reverse conduction state, the MOS-channel diode turns on firstly to prevent the internal parasitic body diode being activated, and thus reduces the turn-on voltage V F and suppresses the bipolar degradation phenomena. The V F of 1.70 V (@I ds = –100 A/cm2) for the SiC MT MOS is 38.2% lower than that of SiC double-trench MOSFET (DT MOS). Meanwhile, the reverse recovery charge Q rr of the MT MOS is 58.7% lower than that of the DT MOS at I load = 700 A/cm2, and thus the reverse recovery loss is reduced. Furthermore, owing to the modulation effect induced by the double trenches, the MT MOS preserves the same superior forward conduction and blocking performance as those of DT MOS, with 22.9% and 18.2% improvement on breakdown voltage and R ON,sp compared to the trench gate MOSFET with planar integrated SBD (ST MOS).

Low-voltage bulk-driven flipped voltage follower-based transconductance amplifier

A low voltage high performance design of operational transconductance amplifier is proposed in this paper. The proposed architecture is based on bulk driven quasi-floating gate metal oxide semiconductor field effect transistor (MOSFET) which supports low voltage operation and improves the gain of the amplifier. Besides to this the tail current source requirement of operational transconductance amplifier (OTA) is removed by using the flipped voltage follower structure at the input pair along with bulk driven quasi-floating gate MOSFET. The proposed operational transconductance amplifier shows a five-fold increase in direct current (DC) gain and 3-fold increase in unity gain bandwidth when compared with its conventional bulk driven architecture. The metal oxide semiconductor (MOS) model used for amplifier design is of 0.18 um complementary metal oxide semiconductor (CMOS) technology at supply of 0.5 V.

Asymmetric Split-Gate 4H-SiC MOSFET with Embedded Schottky Barrier Diode for High-Frequency Applications

4H-SiC Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) with embedded Schottky barrier diodes are widely known to improve switching energy loss by reducing reverse recovery characteristics. However, it weakens the static characteristics such as specific on-resistance and breakdown voltage. To solve this problem, in this paper, an Asymmetric 4H-SiC Split Gate MOSFET with embedded Schottky barrier diode (ASG-MOSFET) is proposed and analyzed by conducting a numerical TCAD simulation. Due to the asymmetric structure of ASG-MOSFET, it has a relatively narrow junction field-effect transistor width. Therefore, despite using the split gate structure, it effectively protects the gate oxide by dispersing the high drain voltage. The Schottky barrier diode (SBD) is also embedded next to the gate and above the Junction Field Effect transistor (JFET) region. Accordingly, since the SBD and the MOSFET share a current path, the embedded SBD does not increase in RON,SP of MOSFET. Therefore, ASG-MOSFET improves both static and switching characteristics at the same time. As a result, compared to the conventional 4H-SiC MOSFET with embedded SBD, Baliga′s Figure of Merit is improved by 17%, and the total energy loss is reduced by 30.5%, respectively.

Improvements in FOMs and Thermal Effects of a III-V Compound Material Based Short-Channel Thin Film Junctionless Double Gate MOSFETs

Better figure of merits (FOMs) have been achieved by using III-V compound material based junctionless double gate metal-oxide semiconductor field-effect transistors (JL DG-MOSFETs), and a thorough analysis of the device’s performance over temperature has been performed using a highly N-doped GaAs-based JL DG-MOSFET using III-V compound material GaSb. GaSb, a compound material, is employed as the source material, which is well known for its greater mobility and injection velocity property with GaAs as the channel and drain materials, to obtain more output current and less leakage current due to the development of hetero structure (GaSb-GaAs) at the source-channel interface. The dielectric material HfO2 with a high k value is utilized to reduce the gate tunneling effects of electrons and enhance the control of the gate at the 20 nm channel length. Primary and auxiliary gates are taken to include ipact ionization on drain side for reducing the Subthreshold-swing. Numerous characteristics of a DG JLMOSFET, such as Id, SS, gm, TGF, Ion/Ioff, Cgs, and fT, GFP, TFP, GTFP are explored and compared with a silicon based material. The proposed structure shows an improved results comparing to the earlier model with Id of 117 mA, SS of 15.08 mV decade−1, gm of 0.62 A V−1, TGF of 38.8 V−1, Ion/Ioff ratio of 1.89 × 10 13, Cgs of 5.86 × 10 −16 F, fT of 2.05 × 10 15 Hz, GTFP of 1.81 × 10 17 Hz/V for the improvement of FOM in RF and DC analysis.

MOSFET Gate Driver Circuit Design for High Repetitive (200 kHz) High Voltage (10 kV) Solid-State Pulsed-Power Modulator

Solid-state pulsed-power modulators can effectively generate high repetition rate pulses, which are required in applications where the process rate depends on the repetition rate, e.g., plasma source ion implantation and deposition, plasma immersion ion milling, and diamond-like carbon coating. In this article, a solid-state pulsed-power modulator for generating high repetitive pulses is developed. Active pull-down circuits and designed metal-oxide-semiconductor field-effect transistor (MOSFET) gate drivers are applied to the modulator without increasing its size. The drivers enable a fast rise, fall time, and minimize pulsewidth, which are effective for high-repetition-rate pulse applications. The developed modulator exhibits a maximum output pulse voltage of ±10 kV, maximum output pulse current of 50 A, pulsewidth between 200 ns and 10 us, maximum pulse repetition rate of 200 kHz, and average output power of 10 kW. The operation principle of the designed MOSFET gate driver is analyzed in detail. Experimental results show that the modulator operates stably at a high repetition rate of 10 kV and 200 kHz and the feasibility of this proposed circuit for high repetition rate operation are verified.

Thickness Modeling of Short-Channel Cylindrical Surrounding Double- Gate MOSFET at Strong Inversion Using Depletion Depth Analysis

Aims: The semiconductor technology has a great impact on consistent growth in the Very-Large- Scale Integrated (VLSI) devices. The transistor size has been scaled down from micron to submicron and towards the nanometer regime in the past 30 years due to technological advancements. The most reliable solid-state device is Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) but this rapid decrease in the device dimensions with the advent of Moore's law follows several problems, such as Short Channel Effects (SCE's) and Hot Carrier Effects. The channel becomes too small at short channel effects that necessitate the analysis of the optimum device designs, in particular in the operating conditions. The charge-sheet model that can quickly analyze a long-channel device, currently in the subthreshold to saturation regime without any discontinuity, turns out to be inappropriate at reduced channel size. Objectives: At the nano-scaling of the device, since the accumulation layer thickness is comparable to the device, the assumption of the channel as a thin sheet of charge vanishes. Though the depletion layers or zone are the regions of the absentia of charges mostly, the existence affects the device behavior and the channel thickness. Therefore, channel thickness modeling becomes essential at various bias conditions to define the specifics of device operation and the channel dependence of the structural parameters. In this work, the objective is to develop an analytical model and numerical analysis of the Cylindrical Surrounding Double-Gate (CSDG) MOSFET, including the thickness, derived based on the formation of depletion depth to analyze the device performance at reducing dimensions. Methods: The analysis is built upon the device's physical and electrical parameters, such as capacitance, electric field, thickness, threshold voltage, effective channel dimensions, drain current, are considered in this research. The depletion region in a MOSFET structure accounts for the inclusion of the source and drain depletion regions, divided primarily into three separate sub-regions as a junction between the diffused source/drain and the substrate depletion under the channel and by region induced by lateral source and drain diffusion. The condition of a planar MOSFET in channel formation, i.e., for strong inversion, and when VGS > VTH has been considered for this mathematical analysis. Results: The computed results of device thickness and depending parameters for a planar MOSFET and the CSDG MOSFET have been obtained. Based on this analysis, the silicon thickness of the typical CSDG MOSFET computed is 180 nm, 281 nm, and 327 nm at VDS 0.2 V, 0.8 V, and 1.2 V, respectively. The achieved results, through the thickness modeling proposed in this work, show that nanoscale CSDG MOSFET can be deployed for the improvements in the device performance and novel design modifications. Conclusion: The analysis presented in this work significantly contributes to understanding the dependence of semiconductor thickness in CSDG MOSFET and serves as a guide for future modifications in the structure for the device compactness.

An Overview on MOSFET Drivers and Converter Applications

—The metal oxide semiconductor field effect transistor (MOSFET) drivers are among the main components for most power electronic applications. Increasing the switching frequency from kHz to MHz levels, MOSFETs' current, power and efficiency expectations are increasing. So it needs to find new solutions to design fast drivers. Some of the outcomes and new applications are now silicon carbide MOSFET applications. The focus of this paper is the power MOSFET gate drive requirements in various switch-mode power conversion applications. So a detailed literature review about MOSFET drivers investigates in this study firstly. There are several different MOSFET structures, but the authors focused on the planar-gate counterparts. Primary system and the switching principle of MOSFET's given in this study. The MOSFET gate driver design principles are presented in more detail in this study. Different proposals and applications for power converters are provided with examples. The drivers evaluated and concluded in all ways.

Improved 4H-SiC UMOSFET with super-junction shield region* *Project supported by the National Natural Science Foundation of China (Grant Nos. 61774052 and 61904045), the Youth Foundation of the Education Department of Jiangxi Province, China (Grant No. GJJ191154), and the Youth Foundation of Ping Xiang University, China (Grant No. 2018D0230).

This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor (MOSFET) (UMOSFET) fitted with a super-junction (SJ) shielded region. The modified structure is composed of two n-type conductive pillars, three p-type conductive pillars, an oxide trench under the gate, and a light n-type current spreading layer (NCSL) under the p-body. The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer, thus improving the specific on-resistance (R on,sp). There are three p-type pillars in the modified structure, with the p-type pillars on both sides playing the same role. The p-type conductive pillars relieve the electric field (E-field) in the corner of the trench bottom. Two-dimensional simulation (silvaco TCAD) indicates that R on,sp of the modified structure, and breakdown voltage (V BR) are improved by 22.2% and 21.1% respectively, while the maximum figure of merit () is improved by 79.0%. Furthermore, the improved structure achieves a light smaller low gate-to-drain charge (Q gd) and when compared with the conventional UMOSFET (conventional-UMOS), it displays great advantages for reducing the switching energy loss. These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance, which also enables the charge carriers to be extracted quickly. In the end, under the condition of the same total charge quantity, the simulation comparison of gate charge and OFF-state characteristics between Gauss-doped structure and uniform-doped structure shows that Gauss-doped structure increases the V BR of the device without degradation of dynamic performance.

Active tunable THz metamaterial array implemented in CMOS technology

Terahertz (THz) modulators offer multifaceted capabilities for various practical applications such as THz imaging, wireless communications, sensing, etc. However, compared to the modulation devices used for other electromagnetic bands, the ubiquitous proliferation of THz applications is severely impeded by the tremendous lack of complementary metal-oxide-semiconductor (CMOS)-compatible technology. Here we demonstrated a CMOS-based active tunable THz metamaterial array (C-ATTMA) with split-ring resonators (SRRs). The THz metamaterial can be externally controlled with an electrically controlled dynamic. The C-ATTMA fabricated by the 180 nm CMOS technology featuring a resonant frequency of 0.30 THz was connected to the source and drain of a bottom metal-oxide-semiconductor field-effect transistor (MOSFET) through the vias. By delicately controlling the MOSFET gate voltage, the equivalent circuit response of the C-ATTMA was actively engineered, enabling tailoring THz resonance frequencies. Under a gate voltage of 1.8 V, we successfully realized a resonant frequency shift of ∼35 GHz and 3° phase shift. The equivalent circuit successfully explained the principle of the change. Inductor–capacitor (LC) resonance and electric dipole resonance of single-layer and double-layer SRRs have also been studied. The exhibited CMOS-compatible electrically regulated THz metamaterials provided a potential method for voltage regulation of THz, which may contribute to THz wireless communications, information encryption, THz compressed sensing and imaging, etc.

Numerical simulation and parametric assessment of GaN buffered trench gate MOSFET for low power applications

This study presents numerical simulation of a novel gallium nitride buffered trench gate (GaN-BTG) metal oxide semiconductor field effect transistor (MOSFET) for high-speed and low-power applications. The electrical characteristics of GaN-BTG-MOSFET are compared with BTG MOSFET and conventional trench gate MOSFET. A comparative study of different performance factors such as electric field, electron velocity, threshold voltage (V th), electron mobility, and sub-threshold swing (SS) of these devices has been performed. Results reveal a 43.85% improvement in SS and 9.83% decrement in V th for GaN-BTG-MOSFET. Furthermore, the frequency analysis has been performed in terms of scattering (S) parameters, cut-off frequency (f T) and maximum oscillator frequency (f MAX) to show how the device is also suitable for radio frequency applications. Furthermore, the study of parametric variation of GaN-BTG-MOSFET with the change in channel length, oxide thickness (t ox), and doping concentration has also been presented. Results show that GaN-BTG-MOSFET can act as a promising structure for further scaling down of the trenched MOSFET and assures better performance for sub-20 nm trenched MOSFET.

Design and Analysis of Heavily Doped n+ Pocket Asymmetrical Junction-Less Double Gate MOSFET for Biomedical Applications

The Complementary Metal-Oxide Semiconductor (CMOS) technology has evolved to a great extent and is being used for different applications like environmental, biomedical, radiofrequency and switching, etc. Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) based biosensors are used for detecting various enzymes, molecules, pathogens and antigens efficiently with a less time-consuming process involved in comparison to other options. Early-stage detection of disease is easily possible using Field-Effect Transistor (FET) based biosensors. In this paper, a steep subthreshold heavily doped n+ pocket asymmetrical junctionless MOSFET is designed for biomedical applications by introducing a nanogap cavity region at the gate-oxide interface. The nanogap cavity region is introduced in such a manner that it is sensitive to variation in biomolecules present in the cavity region. The analysis is based on dielectric modulation or changes due to variation in the bio-molecules present in the environment or the human body. The analysis of proposed asymmetrical junctionless MOSFET with nanogap cavity region is carried out with different dielectric materials and variations in cavity length and height inside the gate–oxide interface. Further, this device also showed significant variation for changes in different introduced charged particles or region materials, as simulated through a 2D visual Technology Computer-Aided Design (TCAD) device simulator.