Gate Matrix Layout Research Articles

Adaptive large neighborhood search applied to the design of electronic circuits

In this paper, a new algorithm is proposed for solving the Gate Matrix Layout Problem (GMLP). This combinatorial problem is NP-Hard and aims to determine the physical layout of the components of an electronic circuit in order to minimize the number of tracks required to connect its nets. By reducing the circuit area, it is possible to reduce manufacturing costs and also improve circuit performance. Computer-aided design of such layouts has direct practical applications in engineering and industry, including information technology, industrial processes automation, and consumer goods production. We propose new local search procedures combined in an Adaptive Large Neighborhood Search (ALNS) metaheuristic to generate solutions for the GMLP. To assess the quality of the proposed method, we have considered 1455 real-world and artificial instances from the literature and compared the proposed ALNS with the state-of-the-art method for the GMLP solution. The ALNS performance is robust as it matches 89% of known optimal solutions and also improves the best known results in some instances.

A heuristic and an exact method for the gate matrix connection cost minimization problem

AbstractIn many applications, a sequencing of patterns (electronic circuit nodes, cutting patterns, product orders, etc.) has to be found in order to optimize some given objective function, giving rise to the so‐called open stack problems. We focus on a problem related to the optimization of gate matrix layouts: electronic circuits are obtained by connecting gates and one seeks a gate layout permutation that minimizes connection costs under restrictions on the circuit area. In the literature, the connection costs and circuit area are also known as time of open stacks and maximum number of open stacks, respectively. We propose a genetic algorithm providing heuristic solutions and a branch‐and‐cut algorithm based on a new linear integer programming formulation that represents, to the best of our knowledge, the first exact method proposed in the literature. The algorithms have been tested on real instances and on data sets from the literature. The computational results give evidence that the proposed methods provide solutions that improve the ones found by the approaches presented in the literature.

A multiple-population evolutionary approach to gate matrix layout

This paper deals with a Very-Large-Scale Integrated systems design problem that belongs to the NP(Nondeterministic Polynomial)-hard class. The Gate Matrix Layout problem has numerous applications in the chip-manufacturing industry and in other industrial settings. A memetic algorithm is employed to solve a set of benchmark instances, and numerical comparisons with a highly competitive method—a microcanonical optimization approach—are performed. Beyond the effectiveness of the method, shown by the results obtained for these instances, an additional goal of this work is to study how the performance of the algorithm is affected by the use of multiple populations and of different individual-migration policies between such populations. The results signal a strong performance improvement of multiple populations over single population approaches. Finally, the proposed algorithm presents several refinements, like structured populations and a specially tailored local search.

A constructive genetic algorithm for gate matrix layout problems

This paper describes an application of a Constructive Genetic Algorithm (CGA) to the gate matrix layout problem (GMLP). The GMLP happens in very large scale integration design and can be described as a problem of assigning a set of circuit nodes (gates) in an optimal sequence, such that the layout area is minimized, as a consequence of optimizing the number of tracks necessary to cover the gates interconnection. The CGA has a number of new features compared to a traditional genetic algorithm. These include a population of dynamic size composed of schemata and structures and the possibility of using heuristics in structure representation and in the fitness function definitions. The application of CGA to GMLP uses a 2-Opt-like heuristic to define the fitness functions and the mutation operator. Computational tests are presented using available instances taken from the literature.

On a solution of a randomized three tracks variant of the Gate Matrix Layout problem

We are concerned with the k-Gate Matrix Layout ( k-GML) problem in a very large scale integration design. The problem asks if k tracks are enough to lay out a given circuit. The k-GML problem may be stated equivalently in terms of random Boolean matrices. In the paper, we find thresholds for the appearance of matrices which are ‘yes’ instances for a randomized 3-GML problem.

On the Power of Logic Resynthesis

A linear arrangement problem, called the minmax mincut problem, emerging from circuit design is investigated. Its input is a series-parallel directed hypergraph (SPDH), and the output is a linear arrangement (and a layout). The primary objective is to minimize the longest path, and the secondary objective is to minimize the cutwidth. It is shown that cutwidth D, subject to longest path minimization, is affected by two terms: pattern number k and balancing number m. Also, k and m are both lower bounds on the cutwidth. An algorithm, running in linear time, produces layouts with cutwidths $D \leq 2(k+m)$. There exist examples with $k=\Omega (N)$, where N is the number of vertices; however, m is always O(log N). We show that every SPDH, after $local\ logic\ resynthesis$ (specifically, after reordering the serial paths), can be linearly placed with cutwidth D=O(log N). Simultaneously, its dual SPDH can be linearly placed with the same vertex order and with cutwidth D=O(log N). Therefore, after local resynthesis the area can be reduced by a factor of N/log N. Application to gate-matrix layout style is demonstrated.

Synthesizing a predatory search strategy for VLSI layouts

When searching for prey, many predator species exhibit a remarkable behavior: after prey capture, the predators promptly engage in "area-restricted search", probing for consecutive captures nearby. Biologists have been surprised with the efficiency and adaptability of this search strategy to a great number of habitats and prey distributions. We propose to synthesize a similar search strategy for the massively multimodal problems of combinatorial optimization. The predatory search strategy restricts the search to a small area after each new improving solution is found. Subsequent improvements are often found during area-restricted search. Results of this approach to gate matrix layout, an important problem arising in very large scale integrated (VLSI) architectures, are presented. Compared to established methods over a set of benchmark circuits, predatory search is able to either match or outperform the best-known layouts. Additional remarks address the relation of predatory search to the "big-valley" hypothesis and to the field of artificial life.

Linear gate assignment: a fast statistical mechanics approach

This paper deals with the problem of linear gate assignment in two layout styles: one-dimensional logic array and gate matrix layout. The goal is to find the optimal sequencing of gates in order to minimize the required number of tracks, and thus to reduce the overall circuit layout area. This is known to be an NP-hard optimization problem, for which no absolute approximation algorithm exists. Here we report the use of a new optimization heuristic derived from statistical mechanics-the microcanonical optimization algorithm, /spl mu/0-to solve the linear gate assignment problem. Our numerical results show that /spl mu/0 compares favorably with at least five previously employed heuristics: simulated annealing, the unidirectional and the bidirectional Hong construction methods, and the artificial intelligence heuristics GM Plan and GM Learn. We also show how the algorithm is able to outperform microcanonical annealing. Moreover, in a massive set of experiments with circuits whose optimal layout is not known, our algorithm has been able to match and even to improve, by as much as seven tracks, the best solutions known so far.

Minimal Oriented Graphs of Diameter 2

Gate matrix layout is an NP-complete combinatorial problem. The related fixed-parameter decision problem has been thoroughly studied for small values of k in recent years. We chose to investigate a more difficult circular version of the fixed-parameter decision problem. We have identified a major group of obstructions to the circular 3-track layout problem. These obstructions all contain a bridge which separates sufficiently large subgraphs; they are called the bridge obstructions. The complete set of circular-3-GML bridge obstructions contains 336 graphs.

A neural network approach to gate matrix layout

Gate matrix layout problem plays an important role in integrated circuit design, but its optimization is NP-hard. In this paper, typical gate layout problem is analysed and adapted to neural network representation, furthermore the simulated results are given.

Improved self-reduction algorithms for graphs with bounded treewidth

Recent results of Robertson and Seymour show that every class that is closed under taking of minors can be recognized in O ( n 3) time. If there is a fixed upper bound on the treewidth of the graphs in the class, i.e., if there is a planar graph not in the class, then the class can be recognized in O ( n 2) time. However, this result is nonconstructive in two ways: the algorithm only decides on membership, but does not construct “a solution”, e.g., a linear ordering, decomposition or embedding; and no method is given to find the algorithms. In many cases, both nonconstructive elements can be avoided, using techniques of Brown (1989) and Fellows and Langston (1989), based on self-reduction. In this paper we introduce two techniques that help to reduce the running time of self-reduction algorithms. With the help of these techniques we show that there exist O ( n 2) algorithms that decide on membership and construct solutions for treewidth, pathwidth, search number, vertex search number, node search number, cutwidth, modified cutwidth, vertex separation number, gate matrix layout, and progressive black–white pebbling, where in each case the parameter k is a fixed constant.

Obstruction set isolation for the gate matrix layout problem

Gate matrix layout is a well-known NP -complete problem that arises at the heart of a number of VLSI layout styles. Despite its apparent general intractability, it has recently been shown that it can be solved in O( n 2) time whenever the number of tracks is fixed. Curiously, the proof of this is nonconstructive, based on finite but unknown obstruction sets. What then are such sets, and what is their underlying structure? The main result we report in this paper is a proof that the obstruction set for three tracks contains exactly 110 elements. We also describe a number of methods for obstruction identification that extend to any number of tracks.

The Vertex Separation and Search Number of a Graph

We relate two concepts in graph theory and algorithmic complexity, namely the search number and the vertex separation of a graph. Let s(G) denote the search number and vs(G) denote the vertex separation of a connected, undirected graph G. We show that vs(G) ≤ s(G) ≤ vs(G) + 2 and we give a simple transformation from G to G′ such that vs(G′) = s(G). We characterize those trees having a given vertex separation and describe the smallest such trees. We also note that there exist trees for which the difference between search number and vertex separation is indeed 2. We give algorithms that, for any tree T, compute vs(T) in linear time and compute an optimal layout with respect to vertex separation in time O(n log n). Vertex separation has previously been related to progressive black/white pebble demand and has been shown to be identical to a variant of search number, node search number, and to path width, which has been related to gate matrix layout cost. All these properties are known to be computationally intractable. For fixed k, an O(n log2n) algorithm is known which decides whether a graph has path width at most k.

An Efficient Polynomial-Time Algorithm for Three-track Gate Matrix Layout

Gate Matrix Layout (GML) is a combinatorial optimization problem that arises in several VLSI layout styles. It is known to be equivalent to other important problems in combinatorial graph theory including vertex separation and pathwidth. While the general problem is N P-complete, when the relevant parameter is fixed, the decision problem can be solved in polynomial time. While solutions with time-complexities O(n) and O(n2) are known, all of those presented so far are impractical due to the presence of extremely large coefficients. Herein we present an efficient O(n3) algorithm for the three-track GML decision problem. The approach we use lays out connected subgraphs in each step thereby constructing a solution when one exists. The algorithm has performed efficiently when used on graphs with over 200 edges.

Genetic beam search for gate matrix layout

The paper presents a novel implementation of the genetic algorithm in combination with beam search for gate matrix layout. This is a permutation problem, for which the traditional genetic crossover operator results in repetition of gates, and therefore the GA is not applicable without modification. However, the GA is a very efficient stochastic optimisation technique, and is easily parallelisable. To adapt it to the gate matrix layout problem, the principles of beam search have been used. The gates are ranked according to their connectivity with each other, and the ranks of the gates to be placed next to each other are picked by the GA. A beam value is used to restrict the ranks of the gates placed next to each other to a low value. This reduces the search space to be explored, and thus results in a more efficient search. The algorithm produces better results compared to a graph-theoretic approach on published netlists.

The Pathwidth and Treewidth of Cographs

It is shown that the pathwidth of a cograph equals its treewidth, and a linear time algorithm to determine the pathwidth of a cograph and build a corresponding path-decomposition is given.

SEGMA: A Simulated Evolution Gate‐Matrix LayoutAlgorithm

In this paper, we present a Simulated Evolution Gate Matrix layout Algorithm (SEGMA) for synthesizing CMOS random logic modules. The gate‐matrix layout problem is solved as a one‐dimensional transistor gates placement problem. Given a placement of all the transistor gates, simulated evolution offers a systematic method to improve the quality of the layout that is measured by the number of tracks needed for the given netlist. This is accomplished by identifying a subset of gates whose relative placements are deemed “poor quality” according to a heuristic criterion. By rearranging the placement of these identified subsets of gates, it is hoped that a gate placement with better quality, meaning fewer tracks, may emerge. Since this method enables the current “generation” of gate placement to evolve into a more advanced one in a way similar to the biological evolution process, this method is called simulated evolution. To apply simulated evolution to solve the gate‐matrix layout problem, we propose a novel heuristic criterion, called randomized quality factor, which facilitates the judicious selection of the subset of poor quality gates. Several carefully devised and tested strategies are also implemented. Extensive simulation results indicate that SEGMA is producing very compact gate‐matrix layouts.

Achieving optimality for gate matrix layout and PLA folding: a graph theoretic approach

We present O( n 3) heuristic algorithms for multiple/ simple PLA folding, which also apply to the matrix layout problem. Our heuristic is based on a new approach, where both problems are shown to be composed by a permutation step followed by a compaction step. Therefore we are able to show that the exponential complexity of the problem stems from the permutation step—where a good configuration is searched—, since the compaction step—where the actual folding takes place—is optimally solved in polynomial time. We discuss bounds on the distance of the obtained solution to the optimal and give sufficient conditions for the solution to be optimal. Verification of the sufficient conditions constitutes part of the proposed algorithms, and is in fact used to construct the heuristic solution. An example showing the multiple folding of a 58 × 19 PLA produced by the proposed algorithm is presented.

The vertex separation number of a graph equals its path-width

We show that the problems of finding a graph's vertex separation number and path-width are the same. The equivalence of these problems with the gate matrix layout and the node search number problems then follows immediately from the results of Fellows and Langston and Kirousis and Papadimitriou, respectively. The fixed parameter variants of problems are known to possess O( n 2) decision algorithms based on finite but unknown obstruction sets. We show how all tree obstructions in these sets may be constructively obtained.

A metal—metal matrix cell generator for multi-level metal MOS technology

This paper describes an automatic cell generator that generates cells in metal—metal matrix (M 3) layout. To minimize the layout area, an ordering of the diffusion columns is determined by minimizing the net-density across the columns, as opposed to between the columns of the layout as is done in gate-matrix layout minimization. In addition, our algorithm considers the interaction between the PMOS region and the NMOS region of CMOS circuits. This method in conjuction with the switching network logic (SNL) approach can be used for design automation of VLSI circuits in double-metal technology as demonstrated through examples.