Gate Matrix Layout Research Articles

Optimal gate-matrix layout of CMOS functional cells

An optimal algorithm for layout of CMOS functional cells, in the gate-matrix style, is proposed. A novel simultaneous graph partitioning technique, which facilitates concurrent partitioning of the p-part and n-part of a CMOS cell, is introduced. The proposed algorithm lays out a given cell with n gates in O(log n) rows, and runs in O( n log n) time. Optimality of this bound is established by proving that there are instances of the problem that require ω(log n) rows. The algorithm has been implemented and experimental results are included.

GM-learn: an iterative learning algorithm for CMOS gate matrix layout

In the paper, an iterative CMOS gate matrix layout algorithm utilising artificial intelligence (A.I.) learning techniques is proposed. This algorithm, called GM-Learn, features a rudimentary learning mechanism which enables iterative improvements of the quality of a gate matrix layout. This is accomplished through the repetitive applications of a one-pass gate matrix layout algorithm, called GM-Plan, to realise a given circuit specification. The function of GM-Learn, is then to ‘learn’ to modify the heuristics used in GM-Plan based on the previous trials. Two AI learning paradigms, known as rote learning and learning by parameter adjustment, are employed. These learning techniques enable GM-Learn to modify its heuristic search parameters based on information obtained from previous iterations. Benchmark test results indicate that this novel algorithm is able to produce a high quality gate matrix layout in only a few iterations. The significance of this new method is that it may be applicable to other combinatorial VLSI physical design problems where heuristic guided search is required.

GM Plan: a gate matrix layout algorithm based on artificial intelligence planning techniques

The CMOS gate matrix layout problem is formulated and solved as an artificial intelligence planning problem in which a plan (the solution algorithm) is to be generated to achieve a goal (the gate matrix layout). The overall goal consists of many subgoals, each of which corresponds to the placement of a gate to a slot, and to the routing of associated nets connecting to that gate. As different nets compete for track (resource) usage, these subgoals interact (interfere) with each other, rendering suboptimal solutions. Here, such interaction among subgoals is managed with two artificial intelligence planning techniques: hierarchical subgoal organization and domain-independent search control policies. The subgoal hierarchy facilitates an object classification of the subgoals into priority classes according to a proposed distance measure of connectivity. Two search control policies (general problem-solving heuristics)-most-constraint (MC) and least impact (LI)-are used to guide the search process. A planning-based gate matrix layout algorithm, called GM Plan, which combines the gate placement and net routing into a single, incremental, problem-solving loop has been developed using these techniques. Encouraging results have been observed in a number of test examples. >

Improved gate matrix layout

A two-stage approach to gate matrix layout is described. The approach consists of: the determination of an optimal gate sequence and an assignment of nets to rows such that the nets are realizable. The gate sequence algorithm is based on T. Asano's approximate search (1981). Modifications are made to it to take into account constraints of transistor sizing, serial subcircuit conflicts, input/output (I/O) gates, and I/O nets. The zone-net assignment algorithm assigns nets to a minimum number of rows determined by the gate sequence and provides a means to resolve vertical conflicts in the layout. Power connections are implemented using the power nets and possible added power rows. Results of examples show that the approach can achieve a considerable improvement compared to earlier algorithms, while satisfying additional constraints.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Improved net merging method for gate matrix layout

A net-merging method is proposed for gate-matrix layout. The method is based on a density function to calculate the minimum number of tracks necessary for the net assignment. Examples that demonstrate how this method leads to a denser gate matrix layout are included. The pitch of the gate columns is determined by the design rules, in particular, the space required to accommodate a diffused region with an internal contact window between two poly columns. In gate matrix layout, when the space between a pair of gate columns is not sufficient, the spacing between them can be increased locally to two pitches to avoid design rule violation as long as such a local change does not cause column matching problems. >

An Efficient Approach to Gate Matrix Layout

This paper proposes a new representation of nets for gate matrix layout, called dynamic-net-lists. The dynamic-net-list representation is better suited for layout optimization than the traditional fixed-net-list since with it net-bindings can be delayed until the gate-ordering has been constructed. Based on dynamic-net-lists, an efficient modified min-net-cut algorithm has been developed to solve the gate ordering problem for gate matrix layout. This new approach is shown through theoretical analysis and experimental results to reduce the number of horizontal tracks and hence the area significantly. The time complexity of the algorithm is O(N log N), where N is the total number of transistors and gate-net contacts. It is also shown that an ideal min-net-cut algorithm for optimal gate matrix layout with n gate signals is at worst a log-n approximation algorithm and is conjectured to be a relative approximation algorithm.

Domino-CMOS barrel switch for 32-bit VLSI processors

A description is given of a full-fledged CMOS 32-bit barrel switch and its physical design. With an extensive use of domino-CMOS circuits with undecoded control signals, a high-speed, area-efficient barrel switch was designed to shift or rotate 32-bit data to the left or right by any number of bit positions between 0 and 31. Operating principles, timing requirements, gate matrix layout, and simulation and test results are discussed.

Exact and Approximate Solutions for the Gate Matrix Layout Problem

We consider the gate matrix layout problem for VLSI circuits, which is known to be NP-complete. We present an efficient algorithm for determining whether two tracks suffice. For the general problem of minimizing the number of tracks (and, hence, the area) needed, we design an attractive dynamic programming formulation to guarantee optimality. We also investigate the performance of fast heuristic algorithms published in the literature and demonstrate that there exist families of problem instances for which the ratio of the number of tracks required by these heuristics to the optimal value is unbounded. Moreover, we show that this result holds for any on-line layout algorithm. We additionally prove that, unless P = NP, no polynomial-time layout algorithm can ensure that the number of tracks it requires never exceeds k plus the optimum, for any constant k.

Gate Matrix Layout

A graph-theoretic description of the problem of layout of CMOS circuits in the style of gate matrix in minimum area is presented. The problem is formulated as one of finding two assignment functions f and h such that the layout L(f, h) requires the minimum number of rows of the gate matrix. The function f maps the distinct gates of the transistors to the columns of the gate matrix and the function h maps the nets of the circuit to the rows such that all of the vertical diffusion runs which connect nets on different rows are realizable. A two-stage approach to the problem is described which first obtains a layout without regard to the vertical constraints and then rows are permuted to satisfy the constraints. Detailed algorithms and examples are given. The gate matrix layout of a 118-transistor circuit was obtained in 9 s on a mainframe computer.

Noise associated with distributed resistance of MOSFET gate structures in integrated circuits

The effect of thermal voltage fluctuations in a resistive gate matrix perpendicular to the direction of channel current, in a MOSFET, are treated in detail. A general formula is derived to arrive at channel current fluctuations for an arbitrary gate matrix layout. This formulation is an extension of the analysis done by Thornber and is valid for frequencies at which the distributed RC time constants associated with the gate matrix are not important. The results of this analysis can be used to design low-noise resistive gate structures.

NMOS dense gate matrix VLSI design

New optimized rules for a fast dense gate matrix layout in single-metal polysilicon-gate depletion-load NMOS technology are presented and applied to a cell design suitable for a VLSI custom cell library.

Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design

BELLMAC-32A is a single-chip fully 32-bit high-end microprocessor designed in 2.5-?m twin-tub CMOS technology. This paper describes the gate matrix layout of random control logic in BELLMAC-32A with top-down hierarchical design methodology. The gate matrix layout provided (1) parallel team layout efforts, (2) adaptability to evolving logic design with short turnaround time, (3) high packing density competitive with hand layout, (4) compatibility with computer-aided layout and verification tools, (5) capability to fine-tune circuits, and (6) technology updatability. It took 6.5 engineer-years to complete the layout of random control logic with 7000 transistors although the logic design was continuously evolving during the layout period. The average packing density of gate matrix layout was 1500 ?m2 per transistor in random logic and 840 ?m2 per transistor in data path. BELLMAC-32A had more-than-three times performance improvement over its 3.5 ?m technology prototype chip BELLMAC-32, in which random control logic was implemented with polycells.

A dense gate matrix layout method for MOS VLSI

A rapid and systematic method for performing chip layout of VLSI circuits is described. This method utilizes the configuration of a matrix composed of intersecting rows and columns to provide transistor placement and interconnections. This structure, which is orderly and regular, gives high device-packing density and allows ease of checking for layout errors. Resulting layouts may be updated to new design rules automatically. This method has been used in the layout of a 20 000-transistor section of a VLSI circuit.