Reduction Of Gate Length Research Articles

Enabling medium thick gate oxide devices in 22FDX® technology for switch and high-performance amplifier application

In this paper two processes with different source and drain out diffusion into the channel of medium thick gate oxide devices in 22FDX® are compared in terms of HCI reliability (electrical field) and DC/RF performance. The margin to pass HCI reliability of the under-drive device allows a steeper source/drain doping profile which enables further gate length reduction. The steeper doping profile reduces Ron significantly while improving the electrostatic behavior due to the longer effective channel. Gate length scaling allows a better trade-off between electrostatic behavior, DC/RF performance, breakdown voltage and reliability. For switch applications the Coff*Ron,AC/Vmax figure of merit can be reduced while ft and fmax is increased for power amplifier applications.

High-Performance Monolayer BeN2 Transistors With Ultrahigh On-State Current: A DFT Coupled With NEGF Study

Conventional field-effect transistors (FETs) based on silicon downscaling are approaching physical limits, and thus, it is urgent to explore additional novel solutions to address this issue. The 2-D semiconductors have unique advantages as the channel material and provide a promising prospect for high-performance FETs in the post-Moore era. In this work, a new 2-D semiconductor, monolayer BeN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , is studied for the FET performance limits through first-principle quantum-transport simulations. Monolayer BeN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> exhibits a graphene-like planar structure with a direct bandgap of 1.3 eV. Transfer characteristics of sub-10-nm BeN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs are thoroughly assessed through scaling gate length. In particular, 2-D BeN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs with 10-nm gate present the ultrahigh ON-state current above <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4500\,\, \mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> for high-performance applications. Also, we realize the significant reduction of gate length (only 2.5 nm) against the International Technology Roadmap for Semiconductors (ITRS) requirements through introducing underlap structures. In addition, the performance of single devices based on monolayer BeN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> is evaluated and compared with some of the recently proposed 2-D devices.

DC Modeling of 4H-SiC nJFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460°C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6 μm (recently fabricated Gen. 11 ICs) limits mission-relevant circuit capabilities. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies (shallow n−and extended n+) to reduce the SiC JFET channel length while maintaining the turn-off behavior needed to realize 500°C circuit operation. COMSOL Multiphysics was used to simulate the transfer characteristics and maximum potential below the gate of a 4H-SiC nJFET at 500°C, and a 1 μm gate length nJFET with turn-off performance comparable to the state-of-the-art is suggested.

Investigation on Variability of Ferroelectric-Gate Field-Effect Transistor Memory by Random Spatial Distribution of Interface Trap

We investigated the variability of memory window (MW) in ferroelectric-gate field-effect transistor (FeFET) by considering the spatial distribution of the trap density at the ferroelectric layer/interfacial layer (FE/IL) interface. Through technology computer-aided design (TCAD) simulations including calibrated ferroelectric parameters, the variability of ultrathin body (UTB) structured FeFETs by the scaling of IL and channel area was confirmed. It was revealed that the reduction of IL thickness (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IL</sub> ) not only increases mean of MW (μMW) but also decreases standard deviation of MW (σMW). Additionally, by identifying the σMW/μMW sensitivity for the reduction of gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) and channel width (W), it was indicated that W causes the more serious σMW degradation because short channel effects by L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> scaling mitigate the σMW degradation.

(Invited) History of Micro-/Nano-Electronics Development; Breakthroughs and Innovations

Introduction Although the first MOSFET-like device ideas were proposed about 90 years ago by J. E. Lilienfeld [1], it took 30 years for the first operational MOSFET to have been successfully fabricated by selecting Al/SiO2/Si as the MOS materials by D. Kahng and M. Attalla [2]. Then, another 10 years were necessary until it had evolved to Large Scale Integrated circuits (LSIs). Indeed ‘microelectronics’ started in early 1970’s with microprocessors fabricated on the LSI chips. At that time, the technology was 10 μm PMOS LSIs. Now, it has evolved to 10 nm-range CMOS LSIs. In the past 50 years, we have experienced 23 generations (each about 2.5 years) of the shrinkage, and the MOSFETs size has decreased by 1,000 times, resulting in an increase in integration density with 1 million times. The continuous increase with the constant rate is the Moore’s law [3], but no one including me could imagine its continuation of over 50 years. The downsizing of MOSFETs has been accomplished based on the scaling scheme proposed by R. Dennard [4], but we have encountered very serious problems at every new generation. Fortunately, however, we have so far succeeded in finding the solutions. This presentation explains some of the history of micro-/nano-electronics technology developments in the past 50 years based on my experience and memory. Technology development for the past 50 years In order to shrink the size, removing the misalignment space margin between the layers is effective, and 2 self-align techniques, Si-gate (between gate and source/drain) and LOCOS (between filed diffusion and oxide) were developed at the end of 1960’s. Then, at the beginning of 1970’s, the fabrication process was simple, with 5 masks for the lithography; field isolation, gate electrode, contact hole, Al interconnects, and bonding pad, with options of a few more masks; channel ion-implantation, or direct-contact between poly-Si lines and source/drain layers, etc.Another factor to reduce the size is to minimize the side-etching and side-diffusion, and anisotropic technologies (or 'dry-process'), such as reactive ion etching and heavy source/drain implantation, were developed at the beginning of 1980’s for the VLSI era. At the same time, stepper (step-and-repeat reduction-projection system) was introduced for higher-resolution lithography. The resolution of the lithography has been improved continuously by introducing a shorter optical wavelength and also by developing various resolution enhancement technologies. Recent introduction of the EUV is a big leap for the wavelength.Since the early 1970’s, short-channel effects (threshold voltage decrease and off-leakage current increase) have been the hurdle for the gate length reduction. The solution was to decrease source/drain junction depth and gate oxide thickness. In order to realize shallow source/drain diffused layers with low resistance, the diffusion element changed from P to As, and new technologies such as low-energy implantation, rapid thermal annealing, and silicided-source/drain were developed. For the thin gate oxide, rapid thermal oxidation, oxynitride gate insulator and finally high-k metal gate technologies were developed. In the early stage of the LSI in 1970s, the semiconductor chips were composed of only 3 major elements, i.e., Si, O, Al with 3 other ones, P, B and H, as additives, but now so many new elements are used for the gate, source, and drain of the MOSFETs, memory cells, and interconnects.Other problems were the degradations of yield and reliability. The mechanisms of the degradations were investigated and many new process/structure/material technologies have been developed as the solutions.In order to suppress the short-channel effects and also to increase the integration density, the structures of the MOSFETs and DRAM/flash memory cells have changed from flat to 3D. Conclusions So huge resources have been invested for the development of micro/nano-electronics in the past 50 years because of its impact to and demands from our modern society, and unbelievably huge progress in engineering and science has been achieved. Indeed, the scales of investment and impact were much bigger than those of the Apollo moon project. The dedication of so many people during the past 50 years has opened up a new smart society in the 21st century with AI, big data, internet and so on. Past 50 years have been really an exciting period. However, the next 50 years will be a more exciting period with a great leap on the base of the micro/nano-electronics.[1] J. Lilienfeld, US1900018A, filed March 28, 1928[2] M. Atalla, and D. Kahng, IRE-AIEE Solid State Device Research Conference, 1960[3] G. Moore, Electronics, Vol. 38, No. 8, April 19, 1965[4] R. Dennard et al., IEEE JSSC, Vol.SC-9, No.5, October, 1974

Linear Characterization and Modeling of GaN-on-Si HEMT Technologies with 100 nm and 60 nm Gate Lengths

Motivated by the growing interest towards low-cost, restriction-free MMIC processes suitable for multi-function, possibly space-qualified applications, this contribution reports the extraction of reliable linear models for two advanced GaN-on-Si HEMT technologies, namely OMMIC’s D01GH (100 nm gate length) and D006GH (60 nm gate length). This objective is pursued by means of both classical and more novel approaches. In particular, the latter include a nondestructive method for determining the extrinsic resistances and an optimizaion-based approach to extracting the remaining parasitic elements: these support standard DC and RF measurements in order to obtain a scalable, bias-dependent equivalent-circuit model capturing the small-signal behavior of the two processes. As to the noise model, this is extracted by applying the well known noise-temperature approach to noise figure measurements performed in two different frequency ranges: a lower band, where a standard Y-factor test bench is used, and an upper band, where a custom cold-source test bench is set up and described in great detail. At 5 V drain-source voltage, minimum noise figures as low as 1.5 dB and 1.1 dB at 40 GHz have been extracted for the considered 100 nm and 60 nm HEMTs, respectively: this testifies the maturity of both processes and the effectiveness of the gate length reduction. The characterization and modeling campaign, here presented for the first time, has been repeatedly validated by published designs, a couple of which are reviewed for the Reader’s convenience.

Study on the Charge Collection Mechanism of Single Event Transient Effect for Nano N-Channel Metal Oxide Semiconductor Field Effect Transistor

Based on the mechanism of charge collection, drift and diffusion, the influence of incident position, drain bias and incident particle LET (Linear Energy Transfer) value on the charge collection of NMOS devices is analyzed. It is found that the strongest electric field in drain depletion region is at 70 nm, and the maximum transient current is 3.43 mA. Drain bias affects the electric field in drain region. The higher drain bias is, the greater the electric field is, and the transient current is the larger of the peak value is, and the change of drain bias does not affect the diffusion current part; the larger the LET is, the larger the set current is, and the transient current peak value and collection charge increase linearly with the increase of LET. In addition, for a single transistor, the influence of the reduction of gate length on the bipolar amplification is analyzed, which is discovered that the reduction of gate length results in the aggravation of the single event effect. Therefore, the simulation results provide valuable reference for research on irradiation reliability and application of strained integrated circuit of Si Nano-scale NMOSFET.

Smaller antenna-gate gap for higher sensitivity of GaN/AlGaN HEMT terahertz detectors

We report an attempt to improve the sensitivity of terahertz detection based on self-mixing in antenna-coupled field-effect transistors by enhancing the field-effect factor and the antenna factor with a reduced gate length and a reduced antenna-gate gap, respectively. An optical noise equivalent power (NEP) of 3.7 pW/Hz at 0.65 THz was achieved in a GaN/AlGaN high-electron-mobility transistor (HEMT) with a gate length of 300 nm and an antenna-gate gap of 200 nm at room temperature. It was found that the antenna factor was inversely proportional to the antenna-gate gap, and the responses upon coherent/incoherent terahertz irradiation were well described by the self-mixing model. To fill the NEP gap of 0.1−1 pW/Hz between room-temperature and cryogenic detectors by HEMT-based detectors at room temperature, impedance match needs to be carefully considered.

Low leakage GaN HEMTs with sub-100 nm T-shape gates fabricated by a low-damage etching process

This paper demonstrates a new fabrication process for gallium nitride high-electron mobility transistors (HEMTs) free of plasma damages in the sub-100 nm T-shape gate area. The common peeling-off problems of electron beam resists during gate metal deposition process were solved by introducing a fluorine plasma treatment process before gate metal deposition. By combining dry and wet etching processes appropriately, an on/off ratio of 107 at a drain-to-source voltage of 1 V was achieved. This work also investigated the short channel effect in devices with gate lengths from 70 to 440 nm. Reducing gate length results in decrease of threshold voltage due to the drain-induced barrier-lowering effect. Current gain cut-off frequency fT and maximum oscillation frequency fmax increase while gate length reduces till 250 nm. However, below 250 nm, fT and fmax no longer increase while gate length reduces till sub-100 nm, which reflect the short channel effect.

Nanoscale dual-gate InAlAs/InGaAs HEMT with improved characteristics

ABSTRACT This paper deals with the DC and Radio Frequency (RF) characteristics of InAlAs/InGaAs-based dual-gate high-electron-mobility transistor (DG-HEMT) for a 50 nm gate length. In single-gate HEMT (SG-HEMT), the gate length having less than 100 nm shows poor transconductance (g m ) which reduces the voltage gain (A v ) and maximum oscillation frequency (f max). To overcome this problem, a dual-gate structure is designed keeping the device dimensions unchanged and a numerical model is developed to study the effect of the dual gate. A comparative study of SG-HEMT and DG-HEMT is presented. For a DG-HEMT, a maximum drain current (Ids ) of 310 mA/mm at Vds = 0.1 V, a peak transconductance (g m_max) of 2294 mS/mm, a cut-off frequency (fT ) of 100 GHz and a maximum oscillation frequency (f max) of 270 GHz have been achieved. For reduced gate length, the DG-HEMT performs better due to the presence of dual gate and double heterojunction.

Oxygen desorption kinetics of ZnO nanorod–gated AlGaN/GaN HEMT-based UV photodetectors

In this study, we investigated the effect of gate length and surface area of the ZnO ultraviolet (UV) absorbing structure on the transient characteristics of AlGaN/GaN HEMT based UV photodetectors. The gate-areas (2, 6 and 18 μm lengths with same width of 100 μm) of AlGaN/GaN HEMTs are covered with ZnO thin film and nanorods (NR) separately. The fabricated devices show enhancement in response speed with the reduction of gate length or the increase of ZnO surface area. The best response speed of ∼10 ms response time and ∼190 ms recovery time is measured from the NR-gated device with a gate length of 2 μm. A model for the oxygen desorption kinetics is proposed for the first time which theoretically shows that the response speed is dependent on two key parameters; light absorbing surface area and gate length. From our model analysis, it is shown that predicted response time is a strong function of these two device parameters, and the calculations show a good agreement with the experimental measurements.

Quadruple Gate-Embedded T Structured GaN-Based Metal–Oxide–Semiconductor High-Electron Mobility Transistors

In this paper, high performance quadruple gate-embedded T structured GaN-based metal–oxide–semiconductor high-electron mobility transistors (MOSHEMTs) were fabricated using laser interference photolithography method and photoelectrochemical oxidation method, in which polymethylmethacrylate was used as sacrificial layer. The associated drain-source saturation current was improved to 175 mA/mm and the gate leakage current at the gate-source voltage of −80 V was improved to $0.81~\mu \text{A}$ compared with the 125 mA/mm and $7.6~\mu \text{A}$ of the conventional single gate GaN-based MOSHEMTs, respectively. Moreover, the associated maximum extrinsic transconductance of the quadruple gate-embedded T structured GaN-based MOSHEMTs was enhanced from 97.3 mS/mm to 118.4 mS/mm. Besides, the associated unit gain cutoff frequency and the associated maximum oscillation frequency were improved from 7.6 GHz to 10.8 GHz and from 11.4 GHz to 27.4 GHz, respectively. The improved performances of the quadruple gate-embedded T structure GaN-based MOSHEMTs were attributed to the function of the gate length reduction and the gate resistance decrease.

Velocity overshoot degradation in short-channel AlGaAs/GaAs HEMTs due to the minimum electron acceleration lengths

Short-channel AlGaAs/GaAs High Electron Mobility Transistors (HEMTs) with gate lengths ranging up to 10 nm were fabricated using electron-beam lithography process. Transconductance starts to rise rapidly as the gate length becomes on the order of the inelastic mean free path of electrons in case of our devices below 80 nm. After reaching a maximum at around 40 nm, it is observed that both the measured transconductance and the subsequently extracted effective electron velocity drop rapidly with further reduction in gate length. We investigated this behavior with a transient transport model based on the retarded Langevin equation (RLE), which indicates the existence of a minimum acceleration length needed for the carriers to reach the overshoot velocity. Also, it clearly shows a degradation of the overshoot. This approach confirms the overshoot is limited by having a minimum acceleration length to reach the peak value of the overshoot due to a source resistance.

Comparative analysis of full-gate and short-gate dielectric modulated electrically doped Tunnel-FET based biosensors

In this work, we have done a comprehensive study between full-gate and short-gate dielectrically modulated (DM) electrically doped tunnel field-effect transistor (SGDM-EDTFET) based biosensors of equivalent dimensions. However, in both the structures, dielectric constant and charge density are considered as a sensing parameter for sensing the charged and non-charged biomolecules in the given solution. In SGDM-EDTFET architecture, the reduction in gate length results a significant improvement in the tunneling current due to occurrence of strong coupling between gate and channel region which ensures higher drain current sensitivity for detection of the biomolecules. Moreover, the sensitivity of dual metal SGDM-EDTFET is compared with the single metal SGDM-EDTFET to analyze the better sensing capability of both the devices for the biosensor application. Further, the effect of sensing parameter i.e., ON-current (ION), and ION/IOFF ratio is analysed for dual metal SGDM-EDTFET in comparison with dual metal SGDM-EDFET. From the comparison, it is found that dual metal SGDM-EDTFET based biosensor attains relatively better sensitivity and can be utilized as a suitable candidate for biosensing applications.

(Dielectric Science and Technology Division Thomas D. Callinan Award Address) Dielectrics for MOS Integrated Circuits

Introduction Insulator films are one of the fundamental elements of the semiconductor integrated circuits together with semiconductor substrate/films and metal/silicide interconnects. Functions of the insulator films in ICs (Integrated Circuits) are roughly classified into the following 6 categories; a) isolation between active devices, b) gate insulator of MOSFETs/MOS capacitors/MIM (Metal Insulator Metal) capacitors, c) sidewall insulation films for gate electrode, d) interlayer isolation films for interconnects, e) passivation films above the interconnects to cover and protect the IC chip surface, and f) insulator film between surface Si layer and Si substrate in SOI (Silicon On Insulator) wafer. In this paper, author’s past works related to the insulator films used ICs are reviewed. Introduction of BPSG reflow technique into NMOS LSI technology One of the severe problems for ICs until the middle of 1970’s was the disconnection of the aluminum interconnects at the steps of insulation film over the edges of poly Si lines and field SiO2 regions. The author applied BPSG (BoroPhospho Silicate Glass) reflow technique for the first time in the world to his developed NMOS LSI technologies in Toshiba, making the steps completely smooth, verifying the yield, and long term reliability in the 1k bit SRAM products in 1975. Finding of plasma induced damage to the gate oxide during ion-implantation and reactive ion etching The author developed a 64k bit DRAM technology from late 1970’s to the beginning of 1980’s. The introduction of source/drain heavy ion-implantation and RIE (Reactive Ion Etching) techniques of poly Si gate electrodes (2nd poly Si) were necessary to fabricate the designed small cell size. The accumulated ionic charge to the capacitor poly electrodes (1st poly Si) during the ion-implantation and reactive ion etching broke the 3 nm gate oxide of the 1st poly Si capacitor, causing bit errors of DRAM. This phenomena were published at the late news of ECS for the first time in the world in 1982 (1). Introduction of RTN gate oxide to prevent the boron penetration In early 1990’s CMOS technology changed from that of single n+-poly Si gate to dual poly Si gate (n+-poly Si for NMOSFETs and p+-poly Si for PMOSFETs) technology, in order to suppress the short-channel effect of PMOSFETs. Because the boron diffusion through the gate SiO2 during the high temperature thermal process is very large, the high-concentration boron penetration from the p+-poly Si to the PMOSFET channel through the gate SiO2 became a big problem. This was known to be solved by introduction of nitrogen to the SiO2. The author and his colleagues demonstrated that the RTN (Rapid Thermally Nitrided) SiO2 gate film completely suppress the boron penetration even the nitrogen concentration in SiO2 is only several percent, for the first time in 1990 (2). Introduction of direct-tunneling gate oxide for CMOS logic device It has been assumed that the gate oxide thinning limit would be 3 nm, because of the significant increase of the gate leakage current by direct-tunneling mechanism. However, the author and his colleagues demonstrated that MOSFETs with 1.5 nm thick direct-tunneling gate oxide operate quite normally, even though there is the direct-tunneling leakage, when decreasing the gate length less than 0.1 um, because the ratio between the gate leakage current and the drain current deceases in proportion to the square of the gate length reduction rate (3). Demonstration of the 0.4 nm EOT La-silicate gate oxide MOSFETs In order to decrease the gate length of MOSFETs to 5 nm, EOT (Equivalent Oxide Thickness) of the gate oxide should be 0.4 nm. The author and his colleagues developed La-silicate high-k metal gate technology and demonstrated the excellent operation of 0.4 nm EOT MOSFETs (4). Reference S. Sawada, S. Maeda, Y. Matsumoto, H. Iwai, H. Nihira, and O. Ozawa, “Degradation of thin gate oxide under process induced electrical stress”, 162nd ECS Fall Meeting, Recent Newspapers, Detroit, USA, October, (1982).T. Morimoto, H. S. Momose, K. Yamabe, and H. Iwai, “Prevention of boron penetration from p+ poly gate by RTP produced thin gate oxide”, ESSDERC 90, Nottingham, England, September, (1990), 73.H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, H. Iwai, “Tunneling gate oxide approach to ultra-high current drive in small-geometry MOSFETs”, in IEDM Tech. Dig., December, (1994), 593H. Iwai, T. Yasuda et al., “Research and development for second generation of ultra-thin gate insulator material”, NEDO Forum 2012 on energy saving technology, Tokyo, November, (2012): in Japanese

Characteristics of a field plate connected to T-shaped gate in AlGaN/GaN HEMTs

An AlGaN/GaN high electron mobility transistor (HEMT) with a T-shaped gate employing a gate-foot-connected field plate is presented. Similar to other devices with gate connected field plates the device described in this paper is a variation of the Γ-shaped gate with the “head” of the Tshaped gate attached at the top. The proposed device has a higher breakdown voltage and a lower leakage current due to the attached field plate while maintaining the advantages of the T-shaped gate structure, which are a low gate resistance and a low noise level. In addition, the field plate deposition step during the fabrication process involves a partial covering of the “foot” of the gate which showed a possibility for a gate length reduction.

Invited: Scaling Mosfets with Self-Aligned Super-Steep-Retrograde-Well

With aggressively reducing of MOSFET area or IC manufacturing costs, the design space to satisfy both device performance and power consumption requirements becomes very limited. Although strain engineering and high-k/metal gate (HKMG) technique were successfully used to scale planar bulk device down to 28nm technology node, further reduction of gate length requires use of fully depleted channel (FDC) to control short channel effect (SCE). FinFET [1] and UTBB SOI [2] are two typical device structures using FDC. However, significant structural and process changes are involved for both FinFET and UTBB SOI implementations. Super steep retrograde well (SSRW) [3] can be used to reduce depleted depth in the channel of bulk MOSFETs with minor process changes. Two major drawbacks for the devices with SSRW are 1) large band-to-band tunneling (BTBT) or leakage between SSRW and source/drain/extension caused by high doping level and 2) difficult to keep abruptness of SSRW due to large thermal budget used in fabrication process, especially source/drain annealing. To fully take the advantage of state-of-the-art integration flow of all gate last HKMG [4], we propose a new method, called self-aligned SSRW, which forms a SSRW self-aligned to the gate of a bulk MOSFET in replacement gate process. The formation of self-aligned SSRWs can avoid source/drain annealing step and reduce the overlap between SSRW and source/drain/extension. A steep retrograde well can be achieved by a relatively low temperature spike annealing or laser annealing.Self-aligned SSRW CMOS devices have been fabricated on 200mm Si wafers in our lab. In this paper, we will review and report the first self-aligned SSRW nMOSFETs and pMOSFETs with all-last HKMG process. To investigate the SCE control and BTBT effect by SSRW, an asymmetrical device structure, replaced metal spacer gate (RMSG) MOSFET with an asymmetrical SSRW doping is also introduced. The MOSFETs with self-aligned SSRWs show good SCE control and low off current at a gate length of 25 nm. Dramatically improved DIBL and Ion/Ioff characteristics have been achieved when SSRW doping is used to replace the conventional halo doping. It turns out that with self-aligned SSRW drain-to-body leakage is reduced by upto two decades due to reduction of BTBT leakage current between channel and SD/extension. We have demonstrated that the self-aligned SSRW process is simple and fully compatible with state-of-the-art all gate last CMOS technology, promising for device performance improvement and mass production towards scaling of MOSFETs. Simulations and further improvements for bulk and SOI MOSFETs with self-aligned SSRWs are also discussed.[1] C. H. Jan et al., IEDM Tech. Dig., pp. 44-47 (2012)[2] L. Grenouillet et al., IEDM Tech. Dig., pp. 64-67 (2012).[3] Z. Ren et al., IEDM Tech. Dig., pp. 733 – 736 (2005).[4] P. Packan et al., IEDM Tech. Dig., pp. 2841-2844 (2009)

Sub-10 nm Gate Length Graphene Transistors: Operating at Terahertz Frequencies with Current Saturation

Radio-frequency application of graphene transistors is attracting much recent attention due to the high carrier mobility of graphene. The measured intrinsic cut-off frequency (fT) of graphene transistor generally increases with the reduced gate length (Lgate) till Lgate = 40 nm, and the maximum measured fT has reached 300 GHz. Using ab initio quantum transport simulation, we reveal for the first time that fT of a graphene transistor still increases with the reduced Lgate when Lgate scales down to a few nm and reaches astonishing a few tens of THz. We observe a clear drain current saturation when a band gap is opened in graphene, with the maximum intrinsic voltage gain increased by a factor of 20. Our simulation strongly suggests it is possible to design a graphene transistor with an extraordinary high fT and drain current saturation by continuously shortening Lgate and opening a band gap.

Thermally reflowed ZEP 520A for gate length reduction and profile rounding in T-gate fabrication

The characteristics of thermally reflowed ZEP 520A-7 (ZEP), a resist commonly used in electron beam lithography, are presented for use as a gate stem resist layer in T-gate process development. As-developed ZEP lines possess a resist sidewall profile that displays varying amounts of undercut, which are determined by the conditions used to expose the line. The authors find that after thermal reflow, the top of the ZEP profile becomes substantially rounded in shape, mitigating “metal cathedraling” problems, a yield-affecting issue that becomes more pronounced as the gate length is reduced. In addition to profile rounding, a linewidth reduction of over 100 nm is observed, and this process has been used to produce gate lengths in the 30–40 nm range. The changes in feature size and the final profile shape depend on the as-developed sidewall angle. Additionally, the ZEP reflow process saturates after a certain amount of time, so reproducibility is not hindered by a lack of precise control in timing. As larger lines can be used to produce smaller features via reflow, the potential for faster throughput exists due to the use of a higher beam current, which would normally limit the attainable minimum feature size.

50-nm Asymmetrically Recessed Metamorphic High-Electron Mobility Transistors With Reduced Source–Drain Spacing: Performance Enhancement and Tradeoffs

Whereas gate-length reduction has served as the major driving force to enhance the performance of GaAs- and InP-based high-electron mobility transistors (HEMTs) over the past three decades, the limitation of this approach begins to emerge. In this paper, we present a systematic evaluation of the impact of greatly reduced source-drain spacing on the performance of 50-nm asymmetrically recessed metamorphic HEMTs (MHEMTs). Extremely high extrinsic transconductance has been achieved over a wide drain bias range starting from as low as 0.1 V by reducing source-drain spacing to 0.5 μm with a self-aligned (SAL) ohmic process. The measured maximum extrinsic transconductance of 3 S/mm is a new record for all HEMT devices on a GaAs substrate and is equal to the best results reported for InP-based HEMTs. With the use of an asymmetric recess, SAL MHEMTs also demonstrate remarkable improvement in other major figures of merit, including off-state breakdown, on-state breakdown, subthreshold characteristics, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio, and the voltage gain over the other SAL HEMTs reported so far. However, they still, in a few respects, under perform the conventional devices typically with 2-μm source-drain spacing. In particular, the on-state breakdown of the SAL devices has been capped at approximately 2 V, even with a very wide asymmetric recess. It appears that the uniqueness of the SAL technology would best fit applications that require low voltage and/or low DC power consumption, which can be fully tapped only when the parasitic capacitance is also properly controlled with, e.g., a high stem gate process.