Gate-length GaAs MESFET Research Articles

Depletion Layer Modeling for Short Gate Length Non-Uniformly Doped GaAs MESFET Under Dark and Illuminated Condition

This paper presents an analytical expression for the depletion region height of short gate length GaAs MESFET with non-uniform doping profile in the channel region. Both, dark as well as illuminated conditions have been considered for model formulation. Depletion region height sensitivities on the doping parameters have also been demonstrated.

Influence of the Edge Effects on the MESFET Transistor Characteristics

A two-dimensional numerical analysis is presented to investigate the field effect transistor characteristics, Our main aim in these sheet related on the one hand to the optimization of a two dimensional (2D) analytical model for the static characteristics of short gate-length GaAs MESFET‟s, this model takes into account the different physical specific phenomena of the device, and on the other hand to study the influence of the effect edge on the variation of some intrinsic elements (...)

A seven-parameter nonlinear I– V characteristics model for sub-μm range GaAs MESFETs

A seven-parameter nonlinear current–voltage ( I– V) characteristics model for sub-micrometre range GaAs MESFETs has been developed. In this regard, Ahmed et al. model [IEEE Trans. Electron Devices 44 (1997) 360] for sub-micron GaAs MESFETs has been modified. In this modification, the effects of both drain-to-source voltage, V DS, and gate-to-source voltage, V GS, on the output conductance, g d, have been incorporated. The developed model has been compared with Ahmed et al. model. For this comparison, an improved mean square error (MSE) technique has been employed instead of root mean square (RMS) error technique. An algorithm has also been developed for the optimization of empirical constants of the model. Sub-μm range MESFETs of different aspect ratios have been modeled with greater accuracy by the modified model. The modified model should be a useful tool for the designing of future integrated circuits with sub-micron gate length GaAs MESFETs.

The Effects of Plasma Induced Damage on The Channel Layers of Ion Implanted GaAs MESFETs during Reactive Ion Etching(RIE) and Plasma Ashing Processes

AbstractThe gate length of GaAs MESFETs is required to be shorter for higher microwave frequency applications. The side-wall process using silicon nitride is one of the effective processes to fabricate short gate length GaAs MESFETs. The side-wall process consists of deposition and anisotropic etching of silicon nitride and delivers plasma induced damages on the channel layers of the devices. In this study, the effects of plasma induced damage on the channel layers of ion implanted GaAs MESFETs during reactive ion etching and plasma ashing processes have been investigated. The plasma induced damage was characterized by sheet resistance measurement, Xray photoelectron spectroscopy(XPS) and auger electron spectroscopy(AES) of different etched surfaces, compared with a chemically wet-etched reference surface. Also the effect of the plasma induced damage on the device performance was investigated. As a result, plasma ashing can deteriorate the plasma-induced damage by RIE.

3-V MSM-TIA for Gigabit Ethernet

The paper describes a 3-V monolithically integrated metal-semiconductor-metal photodetector (MSM-PD) and transimpedance amplifier (TIA) chip that is fully compliant with the Gigabit Ethernet receiver specification for the short-reach application (IEEE 802.3z 1000BASE-SX). Key typical performance specifications are -22 dBm sensitivity, 1200 MHz 3-dB bandwidth, 1300-V/W differential responsivity, and 120-mW power dissipation at 3 V. The chip is fabricated in a production 0.5-/spl mu/m gate length GaAs MESFET technology and is packaged in a TO-46 header with a flat window and a ball-lens cap option.

Differential precoder IC modules for 20-and 40-Gbit/s optical duobinary transmission systems

This paper reports on 20- and 40-Gbit/s differential precoder modules for optical duobinary transmission systems. These precoder modules overcome the speed limit of a conventional precoder by parallel processing. The proposed precoders handle two or four parallel signals before multiplexing with data rates of one-half or one-quarter the transmission bit rate, and the final preceded signal is obtained by multiplexing the precoder output bit by bit, production-level 0.2-/spl mu/m gate-length GaAs MESFET's were used to fabricate the precoders. The precoders are mounted in an RF package. They successfully performed 20- and 40-Gbit/s precoding for the first time, and the 20-Gbit/s precoder achieved a maximum precoding rate of 22 Gbit/s, which is 76% faster than that of the conventional circuit using the same MESFETs. The 40-Gbit/s precoder performs 40-Gbit/s precoding when combined with a 40-Gbit/s multiplexer unit. Twenty-Gbit/s optical duobinary transmitter and receiver circuits using the 20-Gbit/s precoder module successfully generate fully encoded optical duobinary signal at this rate for the first time. These circuits show a receiver sensitivity of -28.6 dBm for a bit error rate of 1/spl times/10/sup -9/.

GaAs MESFET distributed baseband amplifier IC withallpass filter network

A distributed baseband amplifier integrated circuit (IC) which uses an allpass-filter configuration and three-dimensional transmission lines is described. An IC fabricated using 0.1 µm gatelength GaAs MESFETS has a 0 to > 62.5 GHz bandwidth with a flat gain of 10 dB. Its group delay variation in the 0-50 GHz band is only 12.4 ps. This is ~17 ps smaller than that of a conventional distributed baseband amplifier IC.

20-40-Gbit/s-CLASS GaAs MESFET DIGITAL ICs FOR FUTURE OPTICAL FIBER COMMUNICATIONS SYSTEMS

This paper describes recent advances in high-speed digital IC design technologies based on GaAs MESFETs for future high-speed optical communications systems. We devised new types of a data selector and flip-flops, which are key elements in performing high-speed digital functions (signal multiplexing, decision, demultiplexing, and frequency conversion) in front-end transmitter/receiver systems. Incorporating these circuit design technologies with state-of-the-art 0.12 μm gate-length GaAs MESFET process, we developed a DC-to-44-Gbit/s 2:1 data multiplexer IC, a DC-to 22-Gbit/s static decision IC, and a 20-to-40-Gbit/s dynamic decision IC. The fabricated ICs demonstrated record speed performances for GaAs MESFETs. Although further operating speed margin is still required, the GaAs MESFET is a potential candidate for 20- to 40-Gbit/s class applications.

( n)GaAs/Ti/Pt/Au Schottky contacts and their effect on MESFET's dc parameters

Rf sputtered Ti/Pt/Au Schottky contacts with varying titanium thickness have been made on ( n)GaAs by the lift-off process under actual device processing conditions. The ideality factor of the Schottky barrier is dose to unity (∼ 1.07) with a barrier height of 0.80 ± 0.02 eV. The contacts with Ti films as thin as 100 Å remain thermally stable with annealing up to 400°C. These contacts have been next used to fabricate submicron gate length GaAs MESFETs. The MESFET's g m increases with improved gate diode ideality but is not a strong function of it. The effect of Schottky gate annealing on the MESFET's dc characteristics shows that I DSS, g m, V p and V R(GS) remain stable with annealing upto 350°C and degrade with 400° anneal.

32 Gbit/s super-dynamic decision IC using 0.13 µmGaAs MESFETs with multilayer-interconnection structure

The authors report on a super-dynamic decision IC using 0.13 /spl mu/m gate-length GaAs MESFETs. Using a combination of high-speed circuit and device technologies together with a multilayer interconnection structure, 32 Gbit/s decision operation was achieved.

An analytical delay expression for source-coupled FET logic (SCFL) inverters

An analytical delay expression for SCFL inverters is proposed based on a transfer function method. Good agreement is obtained between the measured and calculated propagation delays for an SCFL inverter with 0.2-/spl mu/m gate-length GaAs MESFETs. >

Delay time analysis for short gate-length GaAs MESFETs

GaAs MESFETs with gate lengths from 55 to 150 nm have been fabricated and characterized. By using selective etching for the gate recess, the channel thickness as well as the aspect ratio of the devices of each gate length are known accurately. A cutoff frequency as high as 112 GHz was obtained for a 100 nm × 150 μm device. To study the intrinsic characteristics of these devices, the effects of the pad and the substrate parasitics were first measured and corrected for. Two independent methods adopted to perform this correction have been compared with both resulting in the same intrinsic delay times. Delay time analysis was used to determine the transit time of the electrons in the channel, the channel charging delay, and the drain delay, all as functions of gate length. The results show that the high speed performance of devices with ultra-small gate lengths is limited by the pad parasitics and the intrinsic channel charging and drain delay.

Numerical algorithms for modelling microwave semiconductor devices

AbstractThis paper presents an analysis of the numerical algorithms used to model microwave semiconductor devices. A comparison is made of the relative merits and features of the more popular finite difference schemes. A new generalized Scharfetter–Gummel formulation is presented which is compatible with drift diffusion and energy‐transport formulations, and is suitable for implementing in two‐dimensional simulations on personal computers. The treatment allows for fully degenerate semiconductors, but implementation for the nondegenerate situation is easily obtained as a special case. The convergence and stability properties of the generalized scheme are discussed. The simulation of a planar submicrometre gate length GaAs MESFET is used to illustrate the application of these algorithms.

Effective V-F characteristics in submicrometre GaAsMESFETsevaluated by ensemble Monte Carlo simulation

The effective velocity-field characteristics in a 0.5 µm gate-length GaAs MESFET are evaluated by ensemble Monte Carlo simulation. It is shown that their double-valued properties are caused by hot electron and inertia effects.

2.5 Gb/s laser-driver GaAS IC

A laser-diode driver GaAs IC incorporating an optional NRZ/RZ (non-return-to-zero/return-to-zero) conversion facility, having ECL (emitter-coupled logic) and SCFL (source-coupled FET logic)-compatible inputs and providing a 0-60-mA adjustable output current into a 50- Omega /5-V termination at bit rates up to 2 Gb/s NRZ and maintaining a clear eye opening of 50 mA at 2.5 Gb/s NRZ bit rate has been designed, using a commercial 1- mu m gate-length (F/sub tau /=12 GHz) GaAs MESFET foundry service. The high maximum output current is obtained by implementing the output driver as a cascode differential amplifier. The logic circuitry implemented using a novel, DCAL (diode-clamped active-load) SCFL family, which is based on gate-width scaling rather than on absolute values, so that the on-chip logic voltage swing is less sensitive to process variations than conventional SCFL. A 60% improvement in noise margin is also obtained. To verify laser driving performance a back-to-back optical-fiber transmission experiment was performed, giving good optical eye diagrams at 2.5 Gb/s. The electrooptical interplay between laser-diode driver and laser-diode has been demonstrated using SPICE simulations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

25 Gbit/s selector module using 0.2 μm GaAs MESFET technology

A high-speed selector module has been developed. It is constructed from a selector IC mounted in a ceramic package, a power supply unit, phase shifters, and coaxial cables. The IC was designed using LSCFL and fabricated with 0.2 μm gate length GaAs MESFETs. The selector module operated above 25 Gbit/s. It is expected to be applied to high-speed IC measurements.

Accurate noise characterization of short gate length GaAs mesfets and hemts for use in low‐noise optical receivers

AbstractAccurate noise characterization of MESFETs and HEMTs is required for the design of high‐frequency optical receivers. Here we consider a technique that extracts the intrinsic noise parameters P, R, C from measured noise data. Novel analytic expressions are presented as well as results that prove the validity of the technique. © 1993 John Wiley &amp; sons, Inc.

Modeling submicrometer GaAs MESFETs using PISCES with an apparent gate-length-dependent velocity-field relation

An empirical velocity-field relationship, based on Monte Carlo simulation, is integrated into the PISCES drift-diffusion simulation program in order to analyze short-gate GaAs MESFETs. The current-voltage characteristics are compared with 2D Monte Carlo simulation results on a 0.2 mu m gate length and with measured I-V characteristics of a 0.32 mu m gate-length GaAs MESFET. The comparison and the analysis made support the accuracy of the modified drift-diffusion model and show that it is computationally efficient for simulation of short-gate devices.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High DC and microwave characteristics of subhalf-micrometre gate ion-implanted GaAs MESFETs using trilayer deep UV lithography

Subhalf-micrometre gate length ion-implanted GaAs MESFETs have been fabricated on 3 inch diameter substrates using trilayer deep UV lithography. Implanted MESFETs with 0.3 mu m gate lengths exhibit a maximum extrinsic transconductance of 205 mS/mm at a drain current of 600 mA/mm. From S-parameter measurements, a current gain cutoff frequency f/sub t/ of 56 GHz and a maximum available gain cutoff frequency f/sub max/ greater than 90 GHz are achieved. The gate-to-drain diode characteristics of the devices show a sharp breakdown voltage of 13-15 V. The high drain current-drain voltage and microwave characteristics indicate that ion-implanted technology with trilayer deep UV lithography has potential for the manufacture of power devices and amplifiers for Q-band communication applications. This is the first reported result using trilayer deep UV lithography to demonstrate both f/sub t/ over 56 GHz and 13-15 V gate-to-drain breakdown on 0.3 mu m gate-length ion-implanted GaAs MESFETs. >

Gate width effects on deep level spectra in implanted GaAs MESFETs on LEC substrates

The presence of deep levels in 1 μm gate length GaAs MESFETs has been studied by channel-current deep level transient spectroscopy. Narrow-width devices (10 μm) show only the presence of the EL2 level, while two traps with activation energies of 0.68 eV (hole like) and 0.96 eV, are detected in 40 and 100 μm wide devices. From the above level behavior, it is suggested that the first one reflects electron capture at the GaAs/Si 3N 4 ungated surface, while the second level is a donor center located in, or just below, the same region. In small area devices, the total gate perimeter, rather than the gated to ungated area ratio, appears to be important.