Gate Leakage Current Research Articles

The isolation feature geometry dependence of reverse gate-leakage current of AlGaN/GaN HFETs

Reverse gate-leakage current of AlGaN/GaN heterojunction field-effect transistors (HFETs) realized on array of submicron sized fins and conventional mesa isolation feature geometries is investigated at room temperature and zero drain-source bias. For each of the abovementioned device categories, the significance of leakage from the top surface gate as well as gated etched GaN surfaces, especially sidewalls, is studied for a wide range of gate-source voltages (VGS) (i.e. below and above the threshold voltage). It is proven that in the explored fin-type HFETs, for all values of VGS leakage through the gated GaN surfaces, especially the sidewalls, is more significant than the leakage from the top surface gate. This is while in the mesa category, the sidewall leakage is of importance only at less negative values of VGS, and leakage from the top surface gate substantially takes over at more negative VGS values. The discrepancy in the dominance of the aforementioned leakage paths at more negative VGS values among the explored fin and mesa-type HFETs is demonstrated to be due to the stronger electric field across the barrier in the gated region of the mesa-type HFET for this range of VGS. While in the explored fin-type HFETs Ion/Ioff ratio is as high as 2 × 107, the total amount of reverse gate-leakage at all values of VGS is substantially larger compared to the mesa category sharing an equal value of the overall gate width, which substantiates the significance of leakage through etched GaN surfaces in devices composed of larger number of sidewalls, incorporating larger area of gate-overlapping etched GaN surface.

Adaptive Level-Shift Gate Driver With Indirect Gate Oxide Health Monitoring for Suppressing Crosstalk of SiC MOSFETs

An adaptive level-shift gate driver with indirect gate oxide health monitoring for suppressing crosstalk of bridge-leg configured SiC MOSFETs is proposed. This paper firstly presents a holistic assessment of the changes in major intrinsic parameters before and after aging SiC MOSFETs with repetitive short-circuit tests. Gate leakage is found to be an appropriate precursor to reflect gate oxide degradation. Then, the structure, operation, and design of the proposed gate driver are given. The working principle is based on using a digitally controlled variable resistor in a resistor-capacitor-based voltage divider network to adjust the off-state gate-source voltage. Then, the peak off-state gate-source voltage caused by the spurious voltage is regulated at a level that can avoid shoot-through and reduce off-state voltage stress on the gate. Besides suppressing crosstalk, an optimal off-state gate-source voltage can also improve the life expectancy of SiC MOSFET. By utilizing the loading effect of gate leakage current on the proposed gate driver output, the gate oxide degradation is indirectly monitored by observing the change in the value of the variable resistor. The proposed gate driver has been evaluated on a 1kW inverter prototype under various intrinsic parameter variations. Performance comparisons between proposed and traditional gate drivers are given.

Design and Comparative Analysis of Silicon and GaAs MOSFET for Low Power Applications

The demand for low power consumption in modern electronic devices has led to the development of various technologies, including usage of different materials such as Si and GaAs. In this paper, we present a design and comparative analysis of Si and GaAs MOSFETs for low power applications. The analysis includes the electrical characteristics, performance parameters, and power consumption of both devices. The Si MOSFET and GaAs MOSFET are simulated and analyzed using TCAD tools, and the results are compared. The simulation results show that the GaAs MOSFET has a higher transconductance (gm) compared to the Si MOSFET. However, the Si MOSFET has a lower gate leakage current (Ig) and lower power consumption at low operating frequencies. We also investigate the effect of scaling on the performance and power consumption of both MOSFETs. The results show that scaling improves the performance of both devices, but the power consumption increases as the device dimensions are reduced. The comparative analysis of Si and GaAs MOSFETs for low power applications provides useful insights into the selection of suitable MOSFET technology for specific applications. The results show that both Si and GaAs MOSFETs have their advantages and disadvantages, and the choice depends on the application requirements.

Voltage-margin limiting mechanisms of AlScN-based HEMTs

In this work, the off-state characteristics of AlScN/GaN high electron mobility transistors (HEMTs) grown by metalorganic chemical vapor deposition (MOCVD) were studied and directly compared to an AlGaN- and an AlN-HEMT grown in the same MOCVD. Pinch-off instability and leaky capacitive measurements were observed for AlScN-based HEMTs, which was correlated with a higher ideality factor and lower effective potential barrier height than the AlGaN and AlN-HEMTs. However, the reverse bias characteristics exhibited a sudden drain-current increase without a significant increase in gate-leakage current. The drain-leakage current is assumed to be related to a parasitic channel across the AlScN-barrier as a result of trap-assisted carrier transport with a Poole–Frenkel characteristic. The demonstrated pinch-off instability led to significant gain expansion in load-pull measurements and early soft-breakdown, which, in turn, limits the achievable voltage-margin. The results demonstrate a key issue to reveal the full potential of AlScN-based HEMTs for mm-wave applications.

Efficacy of back barrier engineered Π-gate InAlN/GaN high electron mobility transistors for high-power applications

This work investigates thin-barrier InAlN/GaN high electron mobility transistors (HEMTs) for high-power applications through technology computer-aided design (TCAD) simulations. To begin with, the TCAD simulations were first calibrated with an in-house fabricated InAlN HEMT sample for both DC and pulsed characteristics. The thin-barrier InAlN/GaN HEMTs showed a large leakage current through the gate electrode due to high gate injection, which severely degrades the breakdown characteristics of the device and thus acts as a bottleneck for high-power applications. To improve the two-dimensional electron gas confinement, and consequently reduce the bulk leakage, a back-barrier technique was used. The resistive GaN buffer was replaced with an AlGaN back-barrier that improved the breakdown characteristics at the cost of output power density. Thus, to scale up the output power density and further optimize the breakdown characteristics a Π-shaped gate was introduced to limit the gate leakage current through the InAlN barrier by virtue of its improved hot electron reliability. Coupled with the AlGaN back-barrier, the Π-gate significantly improved the breakdown characteristics to achieve high output power densities, albeit with minor trade-offs to the device gain. To elucidate the compatibility with high-power applications, all the device architectures were dynamically characterized by pulsed I–V simulations and the trap-related dispersive effects were investigated. The Π-shaped gate coupled with an AlGaN back-barrier outperforms conventional architectures by exercising superior electrostatic control over the channel and exhibiting a high linearity for high-power millimeter-wave applications.

Fabrication of non-volatile memory transistor by charge compensation of interfacial ionic polarization of a ferroelectric gate dielectric

Lithium niobate (LiNbO3) is a popular lead free perovskite ferroelectric materials, but its implementation as a gate dielectric for developing a ferroelectric thin film transistor (FeTFT) has not been investigated much due to its low band gap. Low band gap introduces high gate leakage current that results in very low retention time of the device. In this report a solution processed Li5AlO4/LiNbO3/Li5AlO4 stacked layer has been used as a gate dielectric of a metal oxide thin film transistor which reduces gate leakage current by four orders of magnitude with respect to the single layer LiNbO3 gate dielectric device. Besides, due to the ionic polarization of Li5AlO4 thin film that originated from the mobile Li+, charge compensation of the depolarization field has been nearly removed. By reducing these factors, it becomes possible to fabricate metal oxide based FeTFT that has retention time of 7 h which is ∼200 times higher with respect to the LiNbO3 only FeTFT. The ratio of On and Off state of FeTFT is ∼103 which retains ∼ 95% after 7 h of operation. The carrier mobility, ON/OFF ratio and subthreshold swing (SS) of this FeTFT are 2.9 cm2 V − 1 s − 1,7.2 × 104 and 328 mV.decade−1 respectively.

Improved breakdown voltage mechanism in AlGaN/GaN HEMT for RF/Microwave applications: Design and physical insights of dual field plate

This work investigated and proposed the source–gate dual field plate (SG-FP) AlGaN/GaN HEMT for different gate-to-drain drift distances with a fixed gate length of 0.25 μm using ATLAS-TCAD. The increment in the GaN buffer thickness and gate-to-drain drift distance with the variation in the field plate length improves the device performance and breakdown voltages by maintaining the impact ionization mechanism. The breakdown voltage behavior, physical insights of electric field contour, impact generation rate, and potential profile intricacies of source field plate (S-FP), gate field plate (G-FP), and dual field plate (SG-FP) are illustrated. The proposed source–gate dual field plate (SG-FP) with the SiN passivation interfacial layer, SiO2, thicker GaN buffer, and extended gate-to-source drift region is best suited for optimal performance in high breakdown voltage, with optimum cut-off frequency and low gate-leakage current. The proposed dual field plate AlGaN/GaN device with the source field plate (LS-FP = 4 μm), gate field plate (LG-FP = 2 μm), the AlGaN buffer thickness of 3.697 μm, and gate-to-drain drift distance of 8 μm show the highest breakdown voltage of 562 V with the optimum frequency of 8.861 GHz. Finally, the AC/DC characteristics of the optimized dual field plate (SG-FP) are demonstrated. We observed that the source–gate dual field plate (SG-FP) device shows a 6.70% and 4.09% improvement in breakdown voltage compared to individual source field plate (S-FP) and gate field plate (G-FP) designs, respectively. This work shows that the proposed dual field plate device is used in power switching, high-power, and RF/Microwave applications due to its superior breakdown voltage performance, reduction in parasitic capacitances, and optimal cut-off frequency.

Low-Temperature Deuterium Annealing for the Recovery of Ionizing Radiation-Induced Damage in MOSFETs

Ionizing radiation generates bulk traps (Not) as well as interface traps (Nit) in the gate dielectric. These traps cause unwanted threshold voltage (VTH) shifting, subthreshold swing (SS) and increased gate leakage current (IG). In this study, we used low-deuterium annealing (LTDA) as an alternative to conventional annealing, to minimize the side effects of thermal budget. Deuterium atom absorption was confirmed using secondary ion mass spectrometry (SIMS). DC characterizations are performed to analyze the recovery of the gate dielectric damages. Our results demonstrate that the proposed LTDA enables the curing of the gate dielectric damage caused by not only fabrication processing, but also by ionizing radiation. Operating deuterium annealing under low-temperature conditions can improve device performance, reliability, and device-to-device variability.

Synaptic Transistor Arrays Based on PVA/Lignin Composite Electrolyte Films

With the development of information society, the traditional von Neumann-based computing system is facing significant challenges. The search for an intelligent computing system similar to the biological brain would be a very effective solution to the present-day von Neumann bottleneck. Electrolyte-gated transistors (EGTs) have received much attention because they can simulate biological synaptic behavior very effectively. However, large-scale EGTs arrays are still lacking because most of the existing reported EGTs use organic or liquid electrolytes, which poses a significant challenge to the current production methods for manufacturing integration using photolithography. Although synaptic transistor arrays using solid-state electrolytes have the potential for large-scale fabrication, the power consumption required for individual transistors is relatively high. In this work, an electrolyte transistor array (10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 10) fabricated by the photolithography process was successfully proposed, where the individual transistors in the array used a composite polyvinyl alcohol (PVA)/lignin electrolyte as the gate dielectric layer. The switching ratio of a single transistor can reach 106, and the maximum gate leakage current is 43.96 pA in the voltage range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 3 to 3 V. In addition, the synaptic properties, such as excitatory postsynaptic current (EPSC) and paired-pulse-facilitation (PPF), were successfully achieved. When the pulse duration is 100 ms, the energy consumption of the transistor is 0.63 nJ. The number’s dynamic memory and forgetting functions were also successfully simulated by the artificial synaptic transistor array. This work will provide a useful idea for large-scale array integration of EGTs using organic and liquid electrolytes as gate dielectric layers.

AlGaN/GaN Metal Oxide Semiconductor High-Electron Mobility Transistors with Annealed TiO2 as Passivation and Dielectric Layers.

This paper reports on improved AlGaN/GaN metal oxide semiconductor high-electron mobility transistors (MOS-HEMTs). TiO2 is used to form the dielectric and passivation layers. The TiO2 film is characterized using X-ray photoemission spectroscopy (XPS), Raman spectroscopy, and transmission electron microscopy (TEM). The quality of the gate oxide is improved by annealing at 300 °C in N2. Experimental results indicate that the annealed MOS structure effectively reduces the gate leakage current. The high performance of the annealed MOS-HEMTs and their stable operation at elevated temperatures up to 450 K is demonstrated. Furthermore, annealing improves their output power characteristics.

Solution processed Li-Al2O3/LiNbO3/Li-Al2O3 stacked gate dielectric for a non-volatile ferroelectric thin film transistor

Lithium niobate (LiNbO3) gate dielectric based SnO2 ferroelectric thin film transistor (FETFT) is fabricated by a simple solution processed technique. However, LiNbO3 alone is not a suitable candidate for a gate insulator of a TFT because of its low band gap. Therefore, Li-Al2O3/LiNbO3/Li-Al2O3 stacked gate dielectric has been used that reduces the gate leakage current by an order of magnitude compared to the LiNbO3 only device. Moreover, ionic polarization of Li-Al2O3 thin films that originated from mobile Li+ of Li-Al2O3, compensate for the ferroelectric charge polarization of LiNbO3 film. By reducing gate leakage current and compensating ferroelectric charge polarization, it becomes possible to achieve ferroelectric memory retention up to 7.2× 103 s of time with a difference of ON/OFF state by 3 times whereas the reference LiNbO3 device almost merges to each other very quickly. Besides, these ferroelectric TFTs (FETFT) can operate within 2 V operating voltage due to the strong ionic polarization of the gate dielectric. The carrier mobility of 1.9 cm2. V−1.s−1, current ON/OFF ratio of 1.6⨭104 and subthreshold swing (SS) of 167 mV.decade−1 has been achieved under 2 V operation of this FETFT, whereas memory retention time has been studied at 0 V gate and 1 V drain bias.

Realizing improved performance of metal-insulator-semiconductor diodes with high-k MgO/SiOx stack

With the development of metal-insulator-semiconductor (MIS) field-effect transistors, the thickness of silicon dioxide (SiO2) must be scaled down; however, it causes a large gate leakage current and a low on/off current ratio. Magnesium oxide (MgO) exhibits a dielectric constant as high as 11.2, which is about three times larger than that (3.9) of SiO2; thus the thickness of MgO can be three times greater than that of SiO2 and significantly reduces the gate leakage current. Nevertheless, a large lattice mismatch (22.5%) exists between MgO and Si materials. In the study, the MgO/SiOx stack dielectrics are employed to suppress the large lattice mismatch and improve the performance of MIS diodes. The MgO/SiOx stack largely reduces the oxygen vacancy of MgO from 75% to 52.3%; also the fixed oxide charge and interface trap charge density are drastically decreased from 1.3 × 1012 and 1.8 × 1013 to 8.2 × 1011 cm−2 and 7.8 × 1012 cm−2eV−1, respectively. Compared to the MIS diodes with a single MgO, the MgO/SiOx stack dielectrics suppress the gate leakage current by about two orders in MIS diodes; hence the rectification ratio is enhanced from 114 to 1032 at ±2V. Band-diagram shows that Fowler-Nordheim tunneling occurs at a high reverse-bias voltage, and the barrier height increases from 0.18 to 0.42 eV in the MIS diodes with single MgO and MgO/SiOx stack dielectrics, respectively. Nevertheless, the MIS diodes operate through a direct tunneling at low reverse-bias voltages.

A thorough study on the electrical performance change and trap evolution of AlGaN/GaN MIS-HEMTs under proton irradiation

In this work, the effects of proton-induced trap evolution on the electrical performances of AlGaN/GaN metal–insulator–semiconductor (MIS) high-electron-mobility-transistors (HEMTs) have been investigated in detail. Contrary to observed proton-induced degradation in sheet electron density (ns), carrier mobility (μn), and sheet resistance (RSH), a significant improvement in gate leakage current (IG) and off-state drain–source breakdown voltage (BVDS) is found in irradiated devices. The low-frequency noise (LFN) results show that the density of traps in the AlGaN layer and AlGaN/GaN interface increases after irradiation, which leads to a degradation in ns, μn, and RSH and an improvement in BVDS due to enhanced electron trapping and depletion. Furthermore, the measurement results obtained from the frequency-dependent conductance technique show that irradiated devices exhibit decreased trap density (DT) at the insulator/semiconductor interface with hardly changed trap energy level (ET), which confirms the observed proton-induced decrease in IG. An increase in DT at the AlGaN/GaN interface is also found after irradiation, which is consistent with LFN results. These traps with deeper ET induce a serious Coulomb scattering effect. This work provides valuable information for the systematic understanding of the proton irradiation effect of AlGaN/GaN MIS-HEMTs.

Performance Degradation Modeling and Its Prediction Algorithm of an IGBT Gate Oxide Layer Based on a CNN-LSTM Network.

The problem of health status prediction of insulated-gate bipolar transistors (IGBTs) has gained significant attention in the field of health management of power electronic equipment. The performance degradation of the IGBT gate oxide layer is one of the most important failure modes. In view of failure mechanism analysis and the easy implementation of monitoring circuits, this paper selects the gate leakage current of an IGBT as the precursor parameter of gate oxide degradation, and uses time domain characteristic analysis, gray correlation degree, Mahalanobis distance, Kalman filter, and other methods to carry out feature selection and fusion. Finally, it obtains a health indicator, characterizing the degradation of IGBT gate oxide. The degradation prediction model of the IGBT gate oxide layer is constructed by the Convolutional Neural Network and Long Short-Term Memory (CNN-LSTM) Network, which show the highest fitting accuracy compared with Long Short-Term Memory (LSTM), Convolutional Neural Network (CNN), Support Vector Regression (SVR), Gaussian Process Regression (GPR), and CNN-LSTM models in our experiment. The extraction of the health indicator and the construction and verification of the degradation prediction model are carried out on the dataset released by the NASA-Ames Laboratory, and the average absolute error of performance degradation prediction is as low as 0.0216. These results show the feasibility of the gate leakage current as a precursor parameter of IGBT gate oxide layer failure, as well as the accuracy and reliability of the CNN-LSTM prediction model.

Investigation of gate leakage current in TFET: A semi-numerical approach

Tunneling FET (TFET) has been demonstrated as a favorable candidate to replace conventional MOSFETs in low-power applications. However, there are many challenges that should be overcome to efficiently operate the TFET. One of the most limiting factors that can restrict the TFET performance is the gate leakage current. In this paper, the tunneling leakage current through the gate oxide of double gate TFET has been analyzed. The conduction band energy level for gate-oxide-silicon was employed to calculate the tunneling transmission coefficient by utilizing a numerical method. To obtain the potential barrier between the gate and the channel surface, a modified analytical pseudo-2D method has been applied to deduce the corresponding surface potential taking into account a precise calculation of depletion regions. Furthermore, the inclusion of the image charge barrier lowering effect is incorporated in calculating the transmission probability through the oxide. Including such an effect shows a significant influence on determining the gate tunneling current. The gate leakage current has been calculated for various bias voltages and equivalent oxide thicknesses. The presented semi-numerical technique shows good agreement within a suitable CPU time when validated and compared against full numerical TCAD simulation.

Liquid-Metal-Printed Ultrathin Oxides for Atomically Smooth 2D Material Heterostructures.

Two-dimensional (2D) semiconductors are promising channel materials for continued downscaling of complementary metal-oxide-semiconductor (CMOS) logic circuits. However, their full potential continues to be limited by a lack of scalable high-k dielectrics that can achieve atomically smooth interfaces, small equivalent oxide thicknesses (EOTs), excellent gate control, and low leakage currents. Here, large-area liquid-metal-printed ultrathin Ga2O3 dielectrics for 2D electronics and optoelectronics are reported. The atomically smooth Ga2O3/WS2 interfaces enabled by the conformal nature of liquid metal printing are directly visualized. Atomic layer deposition compatibility with high-k Ga2O3/HfO2 top-gate dielectric stacks on a chemical-vapor-deposition-grown monolayer WS2 is demonstrated, achieving EOTs of ∼1 nm and subthreshold swings down to 84.9 mV/dec. Gate leakage currents are well within requirements for ultrascaled low-power logic circuits. These results show that liquid-metal-printed oxides can bridge a crucial gap in dielectric integration of 2D materials for next-generation nanoelectronics.

Ultra-thin top-gate insulator of atomic-layer-deposited HfOx for amorphous InGaZnO thin-film transistors

In recent years, high-k gate dielectrics have attracted increasing attention in amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), due to the urge for stronger gate controllability in advanced applications of high integration density. In this work, the ultra-thin top-gate insulator of atomic-layer-deposited (ALD) HfOx was developed for the amorphous indium-gallium-zinc oxide (a-IGZO) TFTs. Despite the good electrical characteristics of the 4-nm HfOx-gated a-IGZO transistor, its reliability is considerably poor and ascribed to the abundant interface defects, for example, oxygen vacancies. The interface reaction between HfOx and a-IGZO during the ALD process is clarified to be responsible for such defect generation. To prevent the oxygen-related reaction, the a-IGZO channel is pre-treated using the strong oxidizing plasma, contributing to significantly enhanced electrical stabilities. However, the further thinner HfOx would readily increase the gate leakage current, since the electron can easily tunnel through the ultra-thin HfOx due to the low conduction band offset between HfOx and AOS. The 4-nm ALD HfOx together with the pre-oxidization contributes to the optimal performance and stability of top-gate a-IGZO TFT.

Impact of Lanthanum-Induced Dipoles on the Tunneling and Dielectric Properties of Gate-Stack

Threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V_{t}}$ </tex-math></inline-formula> ) engineering is critical and challenging in the advanced logic devices. Inducing interface dipoles by the incorporation of dopants into the gate dielectrics is an emerging scheme to modulate the threshold voltage. However, the impact of those dipoles on gate-stack performance is of great concern. In this work, we present the first-principles calculations of dielectric constant and tunneling current of high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> gate-stack with lanthanum (La) dopants. It is found that incorporation of La improves the local dielectric constant as well as the equivalent oxide thickness (EOT), but degrades the gate leakage current. The calculated results are consistent with the reported experimental data. Furthermore, by analyzing the transmission coefficients and band alignment across the gate-stack, a theoretical explanation for the change of gate leakage current is provided.

Nonalloyed ohmic contact development with n+ InGaN regrowth method and analysis of its effect on AlGaN/GaN HEMT devices

In this study, the DC performance of AlGaN/GaN based HEMT devices of different geometries (designed to operate in the S, X and Ka-band frequency ranges) with regrown degenerately doped n + In0.12GaN nonalloyed ohmic contacts on different epitaxial structures were investigated. Once the optimal recess etch depth and regrowth thickness for drain and source contacts were determined, the effects of alloyed and nonalloyed ohmic contacts on the maximum drain current (IDS,max), ON‐resistance (Ron), maximum DC transconductance (gm), pinch-off voltage (Vth), drain leakage current (ID,leak), and gate leakage current (IG,leak) were investigated for S, X and Ka-band HEMT devices. The results showed that the use of nonalloyed ohmic contacts resulted in decreasing Rc with a better surface morphology. Additionally, the nonalloyed ohmic contact structure with low contact resistance caused an increase in the IDS,max and gm values by reducing the Ron resistance, and also reducing the ID,leak and IG,leak leakage currents by preventing the surface distortions and trap formations due to the absence of high temperature. Although there was no dramatic change in Vth for S, X and Ka-band HEMT devices, Vth shifts towards positive in S and X-band devices, and towards negative in Ka-band devices.

Normally-Off Metal-Insulator-Semiconductor P-GaN gated AlGaN/GaN high electron mobility transistors with low gate leakage current

In this study, a normally-off AlGaN/GaN metal–insulator-semiconductor high electron mobility transistors (MIS-HEMTs) with p-GaN layer were processed, which possess a high threshold voltage and a low gate leakage current due to metal–insulator-semiconductor (MIS) gate structure. A SiNx layer as the insulator layer was deposited between p-GaN layer and gate electrode. The dependent of device performance on SiNx thickness was investigated. Moreover, the threshold voltage of normally-off MIS-HEMT was emphatically discussed with different insulator layer thickness. It demonstrates that obviously positive shifting for threshold voltage from 1.5 to 6 V was achieved by increasing the SiNx thickness from 0 to 20 nm, while the channel mobility was comparable for all samples. Besides, the introduction of MIS gate structure is also beneficial for suppressing the gate leakage current and improving the maximum gate voltage swing owing to the high breakdown field of approximately 8.3 MV/cm.