Gate Leakage Current Density Research Articles

High-quality molecular-beam-epitaxy-grown Ga2O3(Gd2O3) on Ge (100): Electrical and chemical characterizations

High-κ dielectric Ga2O3(Gd2O3) (GGO) has been deposited on Ge (100) at room temperature using molecular beam epitaxy. In situ angular-resolved x-ray photoelectron spectroscopy on the GGO/Ge after gate dielectric deposition and 500°C postdeposition annealing has exhibited negligible Ge interdiffusion, thus revealing high thermal stability of the heterostructure. The CF4-plasma treatment on the passivated GGO/Ge has greatly improved the capacitance-voltage characteristics of the metal-oxide-semiconductor capacitors, besides the very low gate leakage current density of 3.2×10−9A∕cm2 at a flat-band voltage +1V. These excellent interfacial characteristics have been achieved without employing any intentional passivation layers.

Bilayer metal oxide gate insulators for scaled Ge-channel metal-oxide-semiconductor devices

We investigate the electrical properties of germanium-channel metal-oxide-semiconductor capacitors with an amorphous atomic-layer-deposited (ALD)-Al2O3 interlayer (IL) and higher-k ALD-TiO2 gate dielectric. An ALD-Al2O3 IL of ∼1 nm thickness reduces the gate leakage current density at the otherwise low band-offset TiO2/Ge interface by six orders of magnitude at flatband. Devices with the thinnest Al2O3 IL exhibited a low capacitance equivalent thickness of 1.2 nm. The hysteresis of the capacitance-voltage curves was <10 mV for TiO2/Al2O3/Ge capacitors with different Al2O3 thicknesses. We obtained a relatively low minimum density of interface states, Dit ∼3×1011 cm−2 eV−1, suggesting the potential of Al2O3 ILs for higher-k/Ge interface passivation.

Electrical characteristics and reliability properties of metal–oxide–semiconductor capacitors with HfZrLaO gate dielectrics

Metal–oxide–semiconductor (MOS) capacitors incorporating atomic-layer-deposition (ALD) HfZrLaO high- κ gate dielectric were fabricated and investigated. The equivalent oxide thickness (EOT) is 0.68 nm and the gate leakage current density ( J g ) is only 9.3 × 10 −1 A/cm 2. The time-dependence dielectric breakdown (TDDB) behavior agrees with the percolation model, and the TDDB characteristics are consistent with the thermochemical E-model for lifetime projection. The experimental results show that the Weibull slopes are almost independent of capacitor area and stress conditions. The field acceleration parameter ( γ) and activation energy (Δ H 0) are determined around 5.9–7.0 cm/MV and 0.54–0.60 eV, respectively. At 85 °C, the maximum voltage projected for 10-years TDDB lifetime is 1.87 V.

Fabrication and electrical properties of metal-oxide semiconductor capacitors based on polycrystalline p-Cu xO and HfO 2/SiO 2 high- κ stack gate dielectrics

Polycrystalline p-type Cu x O films were deposited after the growth of HfO 2 dielectric on Si substrate by pulsed laser deposition, and Cu x O metal-oxide-semiconductor (MOS) capacitors with HfO 2/SiO 2 stack gate dielectric were primarily fabricated and investigated. X-ray diffraction and X-ray photoelectron spectroscopy were applied to analyze crystalline structure and Cu +/Cu 2+ ratios of Cu x O films respectively. SiO 2 interlayer formed between the high- κ dielectric and substrate was estimated by the transmission electron microscope. Results of electrical characteristic measurement indicate that the permittivity of HfO 2 is about 22, and the gate leakage current density of MOS capacitor with 11.3 nm HfO 2/SiO 2 stack dielectrics is ∼ 10 − 4 A/cm 2. Results also show that the annealing in N 2 can improve the quality of Cu x O/HfO 2 interface and thus reduce the gate leakage density.

Air Stable Cross-Linked Cytop Ultrathin Gate Dielectric for High Yield Low-Voltage Top-Gate Organic Field-Effect Transistors

We demonstrate the use of a cross-linking chemistry for an amorphous fluoropolymer gate dielectric, poly(perfluorobutenylvinylether) commercially known as Cytop. Spin-coated films of Cytop exhibit good gate insulating properties as well as provide excellent OFET operational stability. However, these devices operate at large voltages because the dielectric layer thickness is typically ∼450−600 nm. When the thickness of a Cytop dielectric layer is decreased below 200 nm, the device yields are dramatically reduced due to pinhole formation. Our new cross-linked Cytop (C-Cytop) formulation deposited by spin-coating enables uniform thin films on top of various organic semiconductors that exhibits low gate leakage current densities ( 2 MV cm−1). Our approach results in C-Cytop dielectric films as thin as 50 nm, thus allowing the fabrication of reliable p- and n-channel top-gate OFETs operating at very low-voltages (<5 V). The most remarkable properties of thi...

AlGaN/GaN MOSHEMTs With Liquid-Phase-Deposited $ \hbox{TiO}_{2}$ as Gate Dielectric

TiO2 films deposited on GaN layers at room temperature through a simple and low-cost liquid-phase deposition (LPD) method are investigated and served as gate dielectrics in AlGaN/GaN MOSHEMTs. The electrical characteristics of the MOS structure on n-doped GaN show that the leakage current is about 1.01times10-7 A/cm2 at 1 MV/cm and that the breakdown field is more than 6.5 MV/cm. The maximum drain current density of MOSHEMTs is higher than that of conventional HEMTs, and a wider gate voltage swing can also be observed. The maximum transconductance and threshold voltage almost maintain the same characteristics, even after inserting a dielectric layer between the gate metal and the 2DEG channel by using TiO2 as a gate dielectric. The gate leakage current density is significantly improved, and the bias stress measurement shows that current collapse is much suppressed for MOSHEMTs.

Self-assembled nanodielectrics and silicon nanomembranes for low voltage, flexible transistors, and logic gates on plastic substrates

This letter reports the fabrication and electrical characterization of mechanically flexible and low operating voltage transistors and logic gates (NOT, NAND, and NOR gates) using printed silicon nanomembranes and self-assembled nanodielectrics on thin plastic substrates. The transistors exhibit effective linear mobilities of ∼680 cm2/V s, on/off ratios &amp;gt;107, gate leakage current densities &amp;lt;2.8×10−7 A/cm2, and subthreshold slopes ∼120 mV/decade. The inverters show voltage gains as high as 4.8. Simple digital logic gates (NAND and NOR gates) demonstrate the possible application of this materials combination in digital integrated circuits.

The Dependence of the Performance of Strained NMOSFETs on Channel Width

The dependence of the performance of strained NMOSFETs on channel width was investigated. When the channel width was varied, the stress in the channel varied accordingly. This changed the electron effective mass and, consequently, the on-state current I on. By shrinking the channel width of a strained NMOSFET from 1 to 0.1 mum and by keeping the channel length at 55 nm, the on-state drain current per unit channel width was enhanced by 22%. The gate leakage current was also affected by the stress in the channel, which can be explained by the increase in hole barrier height at the Si/SiO2 interface. Furthermore, when the film stress was increased by 1 GPa, the gate leakage current density Jg of a strained NMOSFET with a channel width of 0.1 mum and a length of 55 nm under a negative bias -3 V was reduced by 63%.

Selenium Segregation for Lowering the Contact Resistance in Ultrathin-Body MOSFETs With Fully Metallized Source/Drain

We report the first integration of selenium (Se) segregation contact technology in ultrathin-body (UTB) n-MOSFET featuring Ni fully silicided source and drain. During the Ni silicidation process, the implanted Se segregated at the NiSi-n-Si interface, leading to significant reduction of Schottky barrier height and contact resistance. The UTB n-MOSFETs integrated with Se segregation (SeS) contact technology show significant external series resistance reduction and drive current performance enhancement. Drain-induced barrier lowering and gate leakage current density are not adversely affected by the SeS process.

The effect of Si surface nitridation on the interfacial structure and electrical properties of (La 2O 3) 0.5(SiO 2) 0.5 high- k gate dielectric films

Thermal stability, interfacial structures and electrical properties of amorphous (La 2O 3) 0.5(SiO 2) 0.5 (LSO) films deposited by using pulsed laser deposition (PLD) on Si (1 0 0) and NH 3 nitrided Si (1 0 0) substrates were comparatively investigated. The LSO films keep the amorphous state up to a high annealing temperature of 900 °C. HRTEM observations and XPS analyses showed that the surface nitridation of silicon wafer using NH 3 can result in the formation of the passivation layer, which effectively suppresses the excessive growth of the interfacial layer between LSO film and silicon wafer after high-temperature annealing process. The Pt/LSO/nitrided Si capacitors annealed at high temperature exhibit smaller CET and EOT, a less flatband voltage shift, a negligible hysteresis loop, a smaller equivalent dielectric charge density, and a much lower gate leakage current density as compared with that of the Pt/LSO/Si capacitors without Si surface nitridation.

Atomic layer deposition of ZrO2/La2O3 high-k dielectrics on germanium reaching 0.5 nm equivalent oxide thickness

We investigate ultrathin ZrO2/La2O3 high-k dielectric stacks on germanium grown by atomic layer deposition. La2O3 is deposited from tris(N,N′-diisopropylformamidinate)-lanthanum and oxygen. Interfacial layer-free oxide stacks with a relative dielectric constant of 21 and equivalent oxide thickness values as low as 0.5 nm are obtained. Metal oxide semiconductor capacitors with platinum as the gate electrode exhibit well-behaved capacitance-voltage characteristics, gate leakage current densities in the range of 0.01–1 A/cm2, and interface trap densities in the range of ∼3×1012 eV−1 cm−2.

Impact on Performance, Positive Bias Temperature Instability, and Time-Dependent Dielectric Dreakdown of n-Type Field Effect Transistors Incorporating Mg into HfSiON Gate Dielectrics

We have investigated the effect on the device performance and reliability of incorporating Mg into the HfSiON gate dielectrics. Mg incorporation is effective for reducing the threshold voltage and gate leakage current in n-type metal–oxide–semiconductor field effect transistor. On the other hand, it may introduce interface states and degrade the mobility if the Mg atoms come close to the interface between the Si substrate and the gate oxide. Nonetheless, Mg incorporation has great potential for improving reliability, including positive bias temperature instability (PBTI) and time-dependent dielectric breakdown (TDDB). Its reliability improvement is mainly caused by gate leakage current reduction and trap density suppression as an result of Mg incorporation.

Electrical properties of metal-ferroelectric (PbZr0.53Ti0.47O3)-polysilicon-insulator (Y2O3)-silicon capacitors and field-effect transistors

In this work, Al∕PbZr0.53Ti0.47O3(PZT)∕n+-polysilicon/Y2O3∕Si (MFPIS) capacitors and transistors were fabricated. A n+-polysilicon floating gate was used to reduce the depolarization field of the ferroelectric layer. The gate leakage current density was as low as 1.68×10−10A∕cm2 at 5V. The IDS-VGS memory window shows a maximum of 2.5V at a sweeping VGS voltage range of 9V. The subthreshold slope is 169mV∕decade. The IDS-VGS on and off ratio of MFPIS field effect transistor was about 104. The MFPIS field effect transistors maintained a threshold voltage window of about 1.6V after an elapsed time of 104s.

Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics

We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high- k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd 2O 3) from a silicon oxide (SiO 2) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs).

Performance and reliability improvement of HfSiON gate dielectrics using chlorine plasma treatment

The effects of chlorine plasma treatment on HfSiON gate dielectrics were investigated with respect to device performance and reliability characteristics. The chlorine plasma treatment was performed on atomic layer deposited HfSiON films to remove the residual carbon content. The optimal chlorine plasma treatment is shown to lower gate leakage current density without increasing equivalent oxide thickness of the gate stack. Secondary ion mass spectroscopy depth profiling showed that the carbon residue in HfSiON was reduced by the chlorine plasma treatment. It is demonstrated that an optimized chlorine plasma treatment improves the transistor Ion-Ioff characteristics and reduces negative-bias temperature instability.

Interface-Engineered High-Mobility High-$k$/Ge pMOSFETs With 1-nm Equivalent Oxide Thickness

High-k/germanium (Ge) interfaces are significantly improved through a new interface engineering scheme of using both effective pregate surface GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> passivation and postgate dielectric (postgate) treatment incorporating fluorine (F) into a high-k/Ge gate stack. Capacitance-voltage (C-V) characteristics are significantly improved with minimum density of interface states (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> ) of 2 times 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> ldr eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> for Ge MOS capacitors. A hole mobility up to 396 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V ldr s is achieved for Ge p-metal-oxide-semiconductor field-effect transistors (pMOSFETs) with equivalent oxide thickness that is ~10 Aring and gate leakage current density that is less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> plusmn 1 V. A high drain current of 37.8 muA/mum at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> = -1.2 V is presented for a channel length of 10 mum. The Ge MOSFET interface properties are further investigated using the variable-rise-and-fall-time charge-pumping method. Over three times D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> reduction in both upper and lower halves of the Ge bandgap is observed with F incorporation, which is consistent with the observation that frequency-dependent flat voltage shift is much less for samples with F incorporation in the C-V characteristics of Ge MOS capacitors.

Interface and Electrical Properties of Atomic-layer-deposited HfAlO Gate Dielectric for N-channel GaAs MOSFETs

AbstractThe interface and electrical properties of HfAlO dielectric formed by atomic layer deposition (ALD) on sulfur-passivated GaAs were investigated. X-ray photoelectron spectroscopy (XPS) revealed the absence of arsenic oxides at the HfAlO/GaAs interface after dielectric growth and post-deposition annealing at 500 °C. A minimal increase in the amount of gallium oxides at the interface was detected between the as-deposited and annealed conditions highlighting the effectiveness of HfAlO in suppressing gallium oxide formation. An equivalent oxide thickness (EOT) of ∼ 2 nm has been achieved with a gate leakage current density of less than 10-4 A/cm2. These results testify a good dielectric interface with minimal interfacial oxides and open up potential for further investigation of HfAlO/GaAs gate stack properties to determine its viability for n-channel MOSFETs.

Effect of NH3 and N2 annealing on the interfacial and electrical characteristics of La2O3 films grown on fully depleted SiGe-on-insulator substrates

The interfacial structure and the electrical properties of pulsed laser deposition derived La2O3 ultra-thin films on fully depleted SiGe-on-insulator (FD SGOI) substrates before and after post-annealing in NH3 and N2, respectively, have been investigated comparatively. The results from high-resolution transmission electron microscopy and x-ray photoelectron spectroscopic revealed that interface reactions take place after the NH3 and N2 annealing process, but, as compared with the N2 annealing process, the NH3 annealing process can effectively decrease the thickness of the interfacial layer and incorporate more nitrogen at the dielectric/SiGe interface, resulting in smaller equivalent oxide thickness. The La2O3 capacitors annealed in NH3 show good capacitance–voltage characteristics with negligible hysteresis, smaller interface trap density and lower gate-leakage current density in comparison with those of capacitors annealed in N2. It is demonstrated that the NH3 annealing process can be a promising technology in improving the quality of high-k dielectric on FD SGOI substrates.

Metal-oxide-semiconductor devices with molecular beam epitaxy-grown Y 2O 3 on Ge

Excellent electrical performance has been achieved on Ge metal-oxide-semiconductor (MOS) devices using molecular beam epitaxy (MBE)-deposited dielectrics of Al 2O 3/Y 2O 3 directly on Ge(1 0 0) without utilizing any interfacial layers, such as GeO x N y or Si. Slight Ge diffusion into Y 2O 3 was observed using in-situ X-ray photoelectron spectroscopy. The interface between Y 2O 3 and Ge is atomically smooth after a high-temperature anneal at 500 °C for 10 min as characterized using high-resolution transmission electron microscopy. A high κ value of Y 2O 3 of ∼17.3 and a low gate leakage current density of 7.6×10 −9 A/cm 2 have been obtained from the MOS capacitors with a total capacitance equivalent thickness (CET) of 2.41 nm. Furthermore, ring-type p-channel MOS field-effect transistors with the same gate oxides have exhibited a high drain current density of 98 mA/mm, a peak transconductance of 43 mS/mm, and a hole mobility of 241 cm 2/V s with a gate length and a gate width of 4 and 400 μm, respectively.

Dependences of nitrogen incorporation behaviors on the crystallinity and phase distribution of atomic layer deposited Hf-silicate films with various Si concentrations

This study examined the nitrogen incorporation behavior of atomic layer deposited HfO2 and Hf-silicate films with various Si concentrations during thermal annealing under a NH3 atmosphere. The level of crystallization and the phase distribution of the films (crystalline HfO2 and amorphous Hf-silicate and SiO2) had a significant effect on extent of nitrogen incorporation. There was virtually no nitrogen incorporation in the crystallized HfO2. Under the condition that the Hf-silicate films were not phase-separated and crystallized during thermal nitridation, the excess HfO2 and SiO2 phases that did not contribute to the amorphous HfSiO4 phase were easily nitrided. On the other hand, the amorphous HfSiO4 phase was barely nitrided. Therefore, it was concluded that the level of nitrogen concentration in the Hf-silicate films decreased with increasing Si concentration in the films. The changes in the capacitance equivalent thickness, gate leakage current density, and flatband voltage shift of the various films after thermal nitridation were consistent with the nitrogen concentration in the films.