Quantum-dot Cellular Automata Gate Research Articles

A Defect Tolerant Design for 5-Input Majority Gate in Quantum-dot Cellular Automata

A Defect Tolerant Design for 5-Input Majority Gate in Quantum-dot Cellular Automata

Design of a new multiplexer structure based on a new fault-tolerant majority gate in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology is believed to be a good alternative to CMOS technology. This nanoscale technology can provide a platform for design and implementation of high performance and power efficient logic circuits. However, the fabrication of QCA circuits is susceptible to faults appearing in this form of missing cells, additional cells, rotated cells and displaced cells. Over the years, several solutions have been proposed to address these problems. This paper presents a new solution for improving the fault tolerance of three input majority gate. The proposed majority gate is then used to design 2-1 multiplexer and 4-1 multiplexer. The proposed designs are implemented in QCA Designer. Simulation results demonstrate significant improvements in terms of fault tolerance and area requirement. The proposed gate consists of 11 cells and requires an area of 0.0096 μm2. The proposed design has 100% tolerance to the fault of a single missing cell and 71.43% tolerance to the rotation of one cell. The proposed 2-1 multiplexer consists of 41 cells and requires an area of 0.066 μm2. This multiplexer has 95.24% tolerance to the fault of a single missing cell.

Synthesis of composite logic gate in QCA embedding underlying regular clocking

Quantum-dot Cellular Automata (QCA) has emerged as one of the alternative technologies for current CMOS technology. It has the advantage of computing at a faster speed, consuming lower power, and work at Nano- Scale. Besides these advantages, QCA logic is limited to its primitive gates, majority voter and inverter only, results in limitation of cost-efficient logic circuit realization. Numerous designs have been proposed to realize various intricate logic gates in QCA at the penalty of non-uniform clocking and improper layout. This paper proposes a Composite Gate (CG) in QCA, which realizes all the essential digital logic gates such as AND, NAND, Inverter, OR, NOR, and exclusive gates like XOR and XNOR. Reportedly, the proposed design is the first of its kind to generate all basic logic in a single unit. The most striking feature of this work is the augmentation of the underlying clocking circuit with the logic block, making it a more realistic circuit. The Reliable, Efficient, and Scalable (RES) underlying regular clocking scheme is utilized to enhance the proposed design?s scalability and efficiency. The relevance of the proposed design is best cited with coplanar implementation of 2-input symmetric functions, achieving 33% gain in gate count and without any garbage output. The evaluation and analysis of dissipated energy for both the design have been carried out. The end product is verified using the QCADesigner2.0.3 simulator, and QCAPro is employed for the study of power dissipation.

Efficient structures for fault-tolerant majority gate in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology is a proper alternative to CMOS circuits, which is a Nano-scale technology that is capable of designing and implementing logic circuits via high efficiency and low power. In this regard, one of the major challenges to design the circuit at QCA is the loss, addition, cells, rotation, and displacement of the cells. Some solutions have been provided to handle these challenges. In this paper, three new structures are proposed to increase the fault tolerance in the three-input majority gate. QCA Designer implements the proposed structures. The simulation results show an increase in fault tolerance and an improvement in the number of cells and space requirements.

Single-bit comparator in quantum-dot cellular automata (QCA) technology using novel QCA-XNOR gates

To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor (CMOS) technology developers. The scaling scenario is not an option nowadays and other technologies need to be investigated. The quantum-dot cellular automata (QCA) technology is one of the important emerging nanotechnologies that have attracted much researchers’ attention in recent years. This technology has many interesting features, such as high speed, low power consumption, and small size. These features make it an appropriate alternative to the CMOS technique. This paper suggests three novel structures of XNOR gates in the QCA technology. The presented structures do not follow the conventional approaches to the logic gates design but depend on the inherent capabilities of the new technology. The proposed structures are used as the main building blocks for a single-bit comparator. The resulted circuits are simulated for the verification purpose and then compared with existing counterparts in the literature. The comparison results are encouraging to append the proposed structures to the library of QCA gates.

Fredkin gate based energy efficient reversible D flip flop design in quantum dot cellular automata

The latest developments in the electronics industry demands for ultra-low power dissipation circuit designing. Reversible logic, an emerging technology for designing digital circuits, is being investigated along with Quantum dot Cellular Automata (QCA) technology for designing high density and ultra-low power circuits in the sub-nano regime. Considering this, in this paper, a new and efficient design of 3x3 reversible Fredkin gate in QCA is proposed which utilizes only 48 cells. It is then used to design a new reversible logic based D Flip Flop. The proposed QCA circuit of reversible D Flip Flop is designed using only 59 cells. From the performance evaluation, it is seen that the proposed reversible logic based D Flip Flop achieves performance improvement of 41% percent in terms of cell count and cell area and 44% in terms of total area from the existing best design in the literature. In addition to this, proposed designs are more energy efficient hence making them more feasible and suitable for implementation in various ultra-low power applications.

Fault Tolerant Reversible Gate Based Sequential Quantum Dot Cellular Automata Circuits: Design and Contemplation

In the era of quantum computing, Quantum Dot Cellular Automata (QCA) is a phenomenal technology which can produce low power, high speed and area efficient circuits. On the other hand, reversible logic is a promising paradigm which is used to construct low power circuits. This paper presents a design of a unique reversible gate based on QCA. This gate can facilitate the design of complex, cost efficient sequential circuits. The proposed gate is examined for various performance parameters such as realization of standard Boolean functions, cost function, energy dissipation and fault characterization. It is observed that the proposed gate exhibits superior performance as compared to the previously reported cost efficient designs in all the performance parameters. Furthermore, to evaluate the efficacy of the proposed QCA gate, reversible sequential latches are designed. The proposed structures of latches excel over the similar existing designs and have shown 50% improvement in latency, 58% improvement in effective cell area and around 70% improvement in cost function. The proposed latches are further investigated for temperature alterations to find the operating range of temperature for the circuits. The reversible QCA gate, proposed in this paper can be effectively used to design D latch, T latch, JK latch with improved performance. Hence, the proposed gate can find extensive scope in designing cost effective, low power, reversible sequential and combinational circuits.

An efficient fault-tolerant arithmetic logic unit using a novel fault-tolerant 5-input majority gate in quantum-dot cellular automata

This paper proposes a novel fault-tolerant 5-input majority gate using 28 simple and rotated cells in Quantum-dot Cellular Automata (QCA) technology. The proposed gate is evaluated against cell omission, extra-cell deposition, and cell displacement defects to check the stability. The simulation results using QCADesigner 2.0.3 software show that the proposed gate is 59% and 100% fault-tolerant against single-cell omission and extra-cell deposition defects, respectively. It also shows good tolerance against cell displacement defects. Moreover, the functionality of the proposed structure is confirmed by physical proofs. QCAPro tool is used to analyze the power consumption of the proposed structure. Fault-tolerant versions of basic gates including 2-input AND, 2-input XOR, and 3-input XOR are suggested using the proposed gate. Moreover, a fault-tolerant 2:1 multiplexer, a 4-bit even parity generator, and an Arithmetic Logic Unit (ALU) are developed and implemented using the proposed fault-tolerant basic gates.

A matrix representation method for decoders using majority gate characteristics in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is a highly attractive alternative to CMOS for the future digital circuit design. Current methods for designing circuits in QCA, especially decoders, mainly refer to traditional CMOS circuit design methods, which do not make full use of the characteristics of QCA technology. For our purpose, the three-input majority gate in QCA is analyzed and a combinational logic gate that fully embodies the majority characteristics is then proposed. A matrix representation method for decoders using the logic gates is proposed, which combines matrix decomposition with majority characteristics. To verify the superiority of this method, a 2–4 and a 3–8 decoders are proposed and implemented in QCA. The proposed decoders have better physical properties in terms of area, latency, cell, gate count, power dissipation and cost function, compared with previous designs. In addition, a schematic diagram of a 4–16 decoder is also presented for demonstrating the scalability of this method. The experimental results show that this method is more suitable for the design of QCA decoders in contrast to previous methods, which can help to reduce the cost of QCA circuits.

A Novel Full Adder/Subtractor in Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA), one of the alternative CMOS technologies at a nano scale, promises to design digital circuits with extra low-power, extremely dense and high speed structures. In this paper, a new QCA gate with three inputs and two outputs is first introduced; this operates on the basis of cell interactions. Then, low complexity and high-speed QCA full-adder and full-subtractor structures are proposed by applying different formulations, which are based on the introduced gate. Finally, a novel QCA full adder/subtractor is presented with the synergy of the proposed QCA full-adder and full-subtractor structures as well as a proposed optimal single layer 2:1 QCA multiplexer. The proposed designs are simulated using the QCA Designer 2.0.3. The simulation results confirm that the proposed circuits work well. A comparative analysis indicates the superiority of the proposed designs compared to the other related designs. Moreover, the QCAPro power estimator tool is utilized to evaluate the power dissipation of the proposed designs.

A Parity-Preserving Reversible QCA Gate with Self-Checking Cascadable Resiliency

A novel Parity-Preserving Reversible Gate (PPRG) is developed using Quantum-dot Cellular Automata (QCA) technology. PPRG enables rich fault-tolerance features, as well as reversibility attributes sought for energy-neutral computation. Performance of the PPRG design is validated through implementing thirteen standard combinational Boolean functions of three variables, which demonstrate from 10.7 to 41.9 percent improvement over the previous gate counts obtained with other reversible and/or preserving gate designs. Switching and leakage energy dissipation as low as 0.141 eV and 0.294 eV, for 1.5 $E_k$ energy level are achieved using PPRG, respectively. The utility of PPRG is leveraged to design a one-bit full adder with 171 cells occupying only 0.19 $\mu \text{m}^2$ area. Finally, fault detection and isolation properties are formalized into a concise procedure. PPRG-based circuits capable of self-configuring active recovery for selected three-variable standard functions are realized using a memoryless method irrespective of garbage outputs.

A Novel Design and Implementation of new Peres and Six- Correction (PSCL) gate in Quantum-dot Cellular Automata (QCA) Technology

A Novel Design and Implementation of new Peres and Six- Correction (PSCL) gate in Quantum-dot Cellular Automata (QCA) Technology

Innovative model for ternary QCA gates

Implementation of basic ternary logic gates is more complex than binary gates in quantum-dot cellular automata (QCA) technology. Several models have been presented for designing ternary logic gates. Most of these models are different solutions and are based on manual calculations. It seems that no simulation tool for designing ternary QCA (tQCA) logic gates has been presented. Unlike previous works, this study is an attempt to introduce an alternative model and the related software for tQCA logic gates. Prominent basic ternary logic gates - such as Min gate, Max gate and inverter - are proposed and simulated in the newly designed TQCAsim software which is an accurate simulation and design tool and is based on the algorithm proposed in this study. Unlike QCA designer software, which has been designed for binary QCA, TQCAsim is designed exclusively for tQCA. Thus, this software can be used to verify and implement the proposed tQCA gates and even earlier designs.

A Novel robust Design of Toffoli gate in Quantum-Dot Cellular Automata

A Novel robust Design of Toffoli gate in Quantum-Dot Cellular Automata

Reversible binary subtractor design using quantum dot-cellular automata

In the field of nanotechnology, quantum dot-cellular automata (QCA) is the promising archetype that can provide an alternative solution to conventional complementary metal oxide semiconductor (CMOS) circuit. QCA has high device density, high operating speed, and extremely low power consumption. Reversible logic has widespread applications in QCA. Researchers have explored several designs of QCA-based reversible logic circuits, but still not much work has been reported on QCA-based reversible binary subtractors. The low power dissipation and high circuit density of QCA pledge the energy-efficient design of logic circuit at a nano-scale level. However, the necessity of too many logic gates and detrimental garbage outputs may limit the functionality of a QCA-based logic circuit. In this paper we describe the design and implementation of a DG gate in QCA. The universal nature of the DG gate has been established. The QCA building block of the DG gate is used to achieve new reversible binary subtractors. The proposed reversible subtractors have low quantum cost and garbage outputs compared to the existing reversible subtractors. The proposed circuits are designed and simulated using QCA Designer-2.0.3.

Design of novel carry save adder using quantum dot-cellular automata

Complex adder designs in Quantum Dot-Cellular Automata (QCA) are primary focus of researchers on lowering cell-count, delay and QCA gates. The cell count, area and delay of two input adders such as Brent-Kung, Ladner-Ficher, Han-Carlson and Kogg-Stone are at least doubles when three numbers are added, compared to adding two numbers. Besides, the interconnected QCA wires for these adders decrease the addition time. To eliminate this problem, a new 4-bit Carry Save Adder (CSA) is proposed in this paper. To design the CSA circuit, a novel design of full adder circuit using 5-input majority gate (MV) has been proposed. The proposed design has around 11.76% improvement in cell count and 33.33% improvement in latency compared to the existing QCA full-adders. Besides, when three binary numbers are added, CSA is far more advantageous compared to similar addition using two input prefix adders, in terms of QCA cell count, area and clock delay. Compared to 4-bit traditional adders, proposed CSA has around 80% decreases in overall circuit cost. The QCA layout of CSA is the first one of its kind. An improved QCA layout of a 4-bit ripple carry adder (RCA) is also proposed in this paper. The RCA has around 7.6% improvement in cell count, 33.33% improvement in latency and around 5.56% improvement in overall cost over compared to the existing layouts.

Application of Artificial Neural Network and Adaptive Neuro-Fuzzy Inference System for the Modelling and Simulation of QCA Circuits

ABSTRACTIn this paper, artificial neural network (ANN) and adaptive neuro-fuzzy inference system (ANFIS) are used for the modelling and simulation of quantum-dot cellular automata (QCA) circuits. For this purpose, all QCA basis components and gates are modelled using ANN and ANFIS. The accuracy and performance of the proposed methods are analysed through a few circuits. Finally, we compared the simulation speed of the proposed methods with QCADesigner software. The results show that the proposed ANN and ANFIS models are much faster than QCADesigner. Also, these models are imported into HSPICE software to design and simulate complex QCA logic circuits.

Design of reliable universal QCA logic in the presence of cell deposition defect

ABSTRACTThe emergence of Quantum-dot Cellular Automata (QCA) has resulted in being identified as a promising alternative to the currently prevailing techniques of very large scale integration. QCA can provide low-power nanocircuit with high device density. Keeping aside the profound acceptance of QCA, the challenge that it is facing can be quoted as susceptibility to high error rate. The work produced in this article aims towards the design of a reliable universal logic gate (r-ULG) in QCA (r-ULG along with the single clock zone and r-ULG-II along with multiple clock zones). The design would include hybrid orientation of cells that would realise majority and minority, functions and high fault tolerance simultaneously. The characterisation of the defective behaviour of r-ULGs under different kinds of cell deposition defects is investigated. The outcomes of the investigation provide an indication that the proposed r-ULG provides a fault tolerance of 75% under single clock zone and a fault tolerance of 100% under dual clock zones. The high functional aspects of r-ULGs in the implementation of different logic functions successfully under cell deposition defects are affirmed by the experimental results. The high-level logic around the multiplexer is synthesised, which helps to extend the design capability to the higher-level circuit synthesis.

Novel 8-bit reversible full adder/subtractor using a QCA reversible gate

Conventional digital circuits consume a considerable amount of energy. If bits of information remain during logical operations, power consumption decreases considerably because the data bits in reversible computations are not lost. The types of reversible gate used in quantum computations are quantum-dot cellular automata (QCA), nuclear magnetic resonance, and optical computations. QCA systems offer low power consumption, high density, section regularity and support new devices designed for nanotechnology. A QCA-based reversible gate has minimal delay, complexity and considering the potential quality of a QCA pipeline, computes at maximum speed. The present study designed a novel $$3 \times 3$$3×3 reversible gate that is universal and testable. A reversible logic gate is also designed based on the majority gate in the QCA and as a QCA reversible (QR) gate. A new 8-bit reversible full adder/subtractor based on the QR gate in QCA with a minimum number of cells and area combines both designs for implementation of a reversible full adder/subtractor in QCA. The performance of these gates was compared with testable Fredkin and Toffoli gates and improved performance of logic functions in terms of complexity and delay over those of the Fredkin and Toffoli gates.

A testable parity conservative gate in quantum-dot cellular automata

There are important challenges in current VLSI technology such as feature size. New technologies are emerging to overcome these challenges. One of these technologies is quantum-dot cellular automata (QCA) but it also has some disadvantages. One of the very important challenges in QCA is the occurrence of faults due to its very small area. There are different ways to overcome this challenge, one of which is the testable logic gate. There are two types of testable gate; reversible gate, and conservative gate. We propose a new testable parity conservative gate in this paper. This gate is simulated with QCADesigner and compared with previous structures. Power dissipation of proposed gate investigated using QCAPro simulator as an accurate power estimator tool.