GaN Gate Research Articles

Suppressed gate leakage and enlarged gate over-drive window of E-mode p-GaN gate double channel HEMTs

A 600-V p-GaN gate double channel HEMT (DC-HEMT) is presented with a systematic investigation of the gate characteristics, including the leakage current, breakdown, and reliability under forward bias stress. It is found that the gate leakage of the DC-HEMT is substantially lower than that of the p-GaN single channel HEMT (SC-HEMT) owing to suppressed electron spillover that stems from hole storage in the quantum well upper channel. Consequently, the gate breakdown voltage of the DC-HEMT is improved to 14.7 V compared to 12.2 V of the SC-HEMT. Besides, the gate operating voltage margin of the DC-HEMT is expanded to 4.2 V compared to 3.3 V of the SC-HEMT according to the gate lifetime evaluation.

Study and optimising performance of enhancement‐mode monolithically integrated white‐light HEMT‐LED by inserting of InGaN quantum wells

AbstractIn this paper five enhancement‐mode monolithically integrated white‐light High electron mobility transistors‐light emitting diodes (HEMT‐LED) structures are proposed and simulated to obtain maximum light intensity, drain current Id and maximum trans‐conductance gm. In first four HEMT‐LED structures white light is generated by combining inbuilt yellow and blue lights and in fifth proposed structure the white light is generated with the combination of inbuilt red, green and blue lights. The InGaN quantum wells (QWs) are inserted in to e‐mode ITO/p‐GaN gate HEMT structures and the desired wavelength of light spectrums are generated by changing the in content (mole fraction), to obtain inbuilt white light. Among five proposed structures one shows Maximum Id‐max of 925 mA and maximum gm of 250 mS, which is significantly higher than any HEMT‐LED structures reported before. All the proposed structures are simulated in Silvaco TCAD software.

Revisiting the effectiveness of diamond heat spreaders on multi-finger gate GaN HEMT using chip-to-package-level thermal simulation

The study of chip-level and package-level heat transfer in a GaN high electron mobility transistor (HEMT) is often disconnected due to limited resources and tools. In this work, device simulation from Silvaco Victory Device is carried forward to the chip-to-package-level simulation using Icepak to provide a complete picture of the proposed thermal management strategies using polycrystalline diamond (PCD) heat spreaders. The max junction temperature, Tj = 105.8 °C and the relative magnitude of max temperature on the GaN surface, ΔTj = 18 % are recorded for the original Si-GaN-Si3N4 chip inside TO-220 at 6.0 Wmm−1. Replacing the Si3N4 with PCD (thermal conductivity of 500 Wm−1 K−1) results in Tj = 98.2 °C and ΔTj = 8 %, while replacing the Si results in Tj = 97.0 °C and ΔTj = 11 %. The top layer PCD spreads the heat from hotspot regions to the surrounding epoxy, while the bottom layer PCD improves the heat path from the hotspots to the base plate. Therefore, the reduction in Tj by the bottom layer PCD is more important than the reduction in ΔTj by the top layer PCD. Implementing both the top and bottom layers of PCD results in the best offers of Tj = 92.9 °C and ΔTj = 6 %. The performance of PCD as heat spreaders in multi-finger gate GaN HEMT suggested by these chip-to-package-level simulations are more reliable than device simulation alone since they cover the complete heat path from generation, conduction within the package, and convection to the ambient air.

Transport Properties in GaN Metal–Oxide–Semiconductor Field‐Effect Transistor Almost Free of Interface Traps with AlSiO/AlN/p‐Type GaN Gate Stack

The factors limiting channel mobility in AlSiO/p‐type GaN metal–oxide–semiconductor (MOS) field‐effect transistors are examined by performing Hall‐effect measurements in conjunction with a gate bias, with and without a thin AlN interlayer. In the absence of this interlayer, the free carrier concentration associated with the Hall effect is significantly reduced compared with the net gate charge density estimated from capacitance–voltage data, indicating that electrons are trapped to a significant extent at the MOS interface. These interface traps are found to have an energy ≈20 meV above the Fermi level in strong inversion based on temperature‐dependent Hall effect data. The insertion of a 0.8 nm‐thick AlN interlayer eliminates charge trapping such that almost all gate charges are mobile. The mobility components could be divided into types based on their effect on the effective electric field perpendicular to the channel. Coulomb scattering centers resulting from interface states are evidently reduced by inserting the AlN interlayer, which also enhances the channel mobility to over 150 cm2 V−1s−1.

Threshold Voltage Modulation and Gate Leakage Suppression of Enhancement‐Mode GaN HEMT by Metal/Insulator/p‐GaN Gate Structure

Herein, a metal/insulator/p‐GaN gate HEMT (MIP‐HEMT) with Si3N4 gate dielectric layer is fabricated. Compared to the conventional p‐GaN HEMT, the MIP‐HEMT has a higher threshold voltage (Vth) of 4.8 V and better gate leakage suppression. The mechanism of threshold voltage increase in MIP‐HEMT is elucidated through an analysis of the electric field distribution in the gate region and the proposed gate capacitance model. Furthermore, MIP‐HEMTs with gate dielectric layers of varying dielectric constants and thicknesses are designed and simulated. The obtained results lead to the derivation of an empirical formula for the threshold voltage of the MIP‐HEMT under ideal dielectric/p‐GaN interface conditions, in relation to the dielectric constant and thickness of the gate dielectric layer. Additionally, simulations are conducted on the MIP‐HEMT incorporating fixed charges at the dielectric/p‐GaN interface, and the impact of interface charges is investigated. This refinement enables a more accurate prediction of the MIP‐HEMT's threshold voltage. Conclusively, MIP‐HEMTs can effectively modulate the threshold voltage by manipulating the parameters of the gate dielectric layer, thereby extending the threshold voltage range of conventional enhancement‐mode devices.

P-GaN gate power HEMT heterostructure as a versatile platform for extremely wide-temperature-range (X-WTR) applications

In this work, we manifest that the epitaxial structure for p-GaN gate high-electron-mobility transistor is a versatile platform to develop electronics for operating in an extremely wide temperature range (X-WTR) from 2 to 675 K, with comprehensive X-WTR studies on device operation and circuit behaviors. The key enabler for the high-temperature operation is the wide bandgap that substantially suppresses the thermal excitation of the intrinsic carrier. However, for the low-temperature side, the two-dimensional electron and hole gas (2DEG and 2DHG) channels at the heterojunctions are formed by the temperature-insensitive polarization fields, which free the carriers from freezing out. The monolithically integrated GaN n-FET, p-FET, and the resultant complementary circuits are, therefore, shown to operate in X-WTR.

An AlGaN-GaN HEMT with p-GaN Extended Gate for Improvements on Current Dispersion and Breakdown Characteristics

This study introduces a novel p-GaN/AlGaN/GaN heterostructure wafer, implementing a unique p-type GaN gate AlGaN/GaN HEMT configuration. In this design, the p-GaN region extends toward the drain, eliminating the need for a gate electrode. This innovation significantly enhances the HEMT’s performance, with a 45.2% increase in breakdown voltage (BV) and a 17% higher threshold voltage (VTH) compared to conventional p-GaN gate HEMTs. The extended gate design redistributes the electric field, acting as a field plate to elevate the breakdown voltage. Furthermore, the proposed device, by reducing 17.4% of the saturation current without increasing the on-resistance, possibly offers improved short-circuit capability.

Reliability of enhancement-mode p-GaN gate GaN HEMT with multiple field plates

In this paper, we fabricate enhancement-mode p-GaN gate GaN HEMTs with multiple field plates (MFPs) and analyze the reliability of the devices by means of simulation and experiment. Simulations of the electric-field distribution indicate that the MFPs effectively weaken the electric field peak near the gate to below the theoretical breakdown value and smooth the electric field between the gate edge and drain-side field plate edge. The simulated electric field peak leading to the breakdown of the device with MFPs at high drain voltage is located at the drain edge, which is validated by experimental results. The GaN HEMTs with MFPs exhibit excellent long-term reliability under high temperature and drain voltage, while deviations from threshold voltage and on-resistance were observed in the device subjected to drain stress. We attribute these deviations to electron accumulation and high field-assisted detrapping processes in the p-GaN layer. This investigation provides new insight into the mechanism of variations in threshold voltage and on-resistance under off-state drain stress.

Study of Magnesium Activation Effect on Pinch-Off Voltage of Normally-Off p-GaN HEMTs for Power Applications

The role of the magnesium (Mg) doping and its electrical activation on the off-state of p-GaN/AlGaN/GaN HEMTs has been investigated in this work. Firstly, the effect of different Mg doping profiles has been studied via the help of Technology Computer-Aided Design (TCAD) simulations, with the objective of analyzing the band diagrams of the structure. Then, it has been shown how experimental Capacitance–Voltage measurements can be useful to obtain information on the net acceptor concentration in the p-GaN. As a result, devices with an undoped (magnesium-free) GaN gate have been experimentally compared to devices whose p-GaN gate has been activated via a reference annealing process. Finally, results on a device characterized by an improved p-GaN activation have been presented and compared, showing improvements on several parameters of both off- and on-state, thus underlining the key role of the Mg activation process in the overall performances of normally-off GaN HEMTs.

Recent Progress of E‐mode Gallium Nitride Metal–Insulator–Semiconductor ‐High Electron Mobility Transistors with Hybrid Ferroelectric Charge Trap Gate (FEG‐HEMT) for Power Switching Applications

Aluminum gallium nitride/gallium nitride (AlGaN/GaN) heterostructure devices have proven to be highly effective for high‐frequency power amplifiers and power switching applications with improved performance compared to those made with traditional silicon technology and other advanced semiconductor technologies. The development of enhancement‐mode (E‐mode) AlGaN/GaN high electron mobility transistors (HEMTs) and metal–insulator–semiconductor HEMTs (MIS‐HEMTs) has been a focus in recent years due to their potential applications. Arising from the concept of a flash‐memory‐like hybrid ferroelectric charge storage structure, the high‐performance hybrid ferroelectric charge storage gate (FEG) GaN HEMT has gradually gained a great deal of attention due to the concept being a useful and versatile tool to realize E‐mode operations. This article attempts to review the latest progresses in this technology, including alternative improvements and device characteristics. Future challenges for the E‐mode FEG‐HEMT are also discussed.

Recent Developments and Prospects of Fully Recessed MIS Gate Structures for GaN on Si Power Transistors

For high electron mobility transistors (HEMTs) power transistors based on AlGaN/GaN heterojunction, p-GaN gate has been the gate topology commonly used to deplete the two dimensional electron gas (2-DEG) and achieve a normally-OFF behavior. But fully recessed MIS gate GaN power transistors or MOSc-HEMTs have gained interest as normally-OFF HEMTs thanks to the wider voltage swing and reduced gate leakage current when compared to p-GaN gate HEMTs. However the mandatory AlGaN barrier etching to deplete the 2-DEG combined with the nature of the dielectric/GaN interface generates etching-related defects, traps, and roughness. As a consequence, the threshold voltage (VTH) can be unstable, and the electron mobility is reduced, which presents a challenge for the integration of a fully recessed MIS gate. Recent developments have been studied to solve this challenge. In this paper, we discuss developments in gate recess with low impact etching and atomic layer etching (ALE) alongside surface treatments such as wet cleaning, thermal or plasma treatment, all in the scope of having a surface close to pristine. Finally, different interfacial layers, such as AlN, and alternative dielectrics investigated to optimize the dielectric/GaN interface are presented.

Design of 30 nm multi-finger gate GaN HEMT for high frequency device

ABSTRACT In this study, the DC and RF performances of multi fingered AlGaN/GaN are studied in simulation, and the DC and RF performance of the traditional T-gate HEMT and the multi-finger HEMT are compared.The reason for the performance difference is that the use of multi finger gate technology reduces the total parasitic capacitance and the total transit time of the carrier through the device compared to conventional T-gate devices, resulting in an increase in FT and Fmax. Based on the study of conventional AlGaN/GaN HEMT devices, an InAlN/GaN HEMT device with two-finger gate is designed. Due to the matching of InAlN and GaN lattice, the polarisation effect and carrier density of the heterojunction formed by InAlN and GaN are larger than those of conventional AlGaN/GaN heterojunction, which can ensure the device to have a larger output current while operating at high frequency. The results show that the peak FT and Fmax of the proposed InAlN/GaN HEMT are 239.5 GHz and 331.5 GHz, respectively.

Adaptive Dead-Time Control Design with Low Dead-Time Error in 20 MHz 90 V GaN Gate Driver

This paper presents an adaptive dead-time control circuit for a maximum work frequency 20 MHz, maximum voltage level 90 V GaN gate driver. The dead-time is set to prevent straight-through of the upper and lower power transistors of the bridge arm structure and ensure the reliability of the motor driver. For GaN drivers on the market today, fixed or configurable dead-time is widely used in more-than-10 MHz application scenarios. However, the switching loss caused by insufficient dead-time and reverse turn-on loss caused by excessive dead-time of GaN devices have a hazardous influence on the efficiency of drivers, which fixed or configurable dead-time cannot avoid. The gate driver with the proposed adaptive dead-time control circuit has been implemented in a 0.18 um BCD process. The proposed adaptive control circuit dissipates 56.3 uA quiescent current in a simulation situation and is able to provide maximum 5 ns dead-time error for a GaN gate driver.

Gate Drive Circuit Suitable for a GaN Gate Injection Transistor

A GaN gate injection transistor (GIT) has great potential as a power semiconductor device. However, a GaN GIT has a diode characteristic at the gate-source, and a corresponding gate drive circuit is thus required. Several studies in the literature have proposed the gate drive circuits with the speed-up capacitors, but adding these capacitors complicates the gate drive circuit, and increases both the drive and reverse conduction losses. Moreover, driving a GaN GIT with such gate drive circuits becomes more susceptible to the false turn-on. In this paper, a gate drive circuit suitable for a GaN GIT without a speed-up capacitor is proposed. This type can provide the high-speed switching, and exhibit the low gate drive loss and reverse conduction loss. The proposed circuit also has high immunity against the false turn-on and stable gate-source voltage before and after startup. The drive loss of the proposed type is calculated and its validity is confirmed experimentally. Furthermore, the drive loss of the proposed type is compared with the conventional circuits. The result shows that the drive loss of the proposed type is improved by up to 50 %, compared with the conventional type. Finally, the proposed type is experimentally tested to drive a buck converter at the switching frequency of 150 kHz. The entire loss of the converter can be reduced by up to 9.2% at 250 W, compared with the conventional type.

Monolithically Integrated GaN Gate Drivers– A Design Guide

Monolithically Integrated GaN Gate Drivers– A Design Guide

Research on self-supporting T-shaped gate structure of GaN-based HEMT devices

A self-supporting T-shaped gate (SST-gate) GaN device and process method using electron beam lithography are proposed. An AlGaN/GaN high-electron-mobility transistor (HEMT) device with a gate length of 100 nm is fabricated by this method. The current gain cutoff frequency (f T) is 60 GHz, and the maximum oscillation frequency (f max) is 104 GHz. The current collapse has improved by 13% at static bias of (V GSQ, V DSQ) = (–8 V, 10 V), and gate manufacturing yield has improved by 17% compared with the traditional floating T-shaped gate (FT-gate) device.

On-Chip Dynamic Gate-Voltage Waveform Sampling in a 200-V GaN-on-SOI Power IC

The continual improvement of GaN-on-Si processes motivates the integration of more complex circuits alongside GaN power devices. Additional transistors can be leveraged to provide control, logic, and protection; however, low-voltage GaN devices consume more power and area than similar CMOS counterparts. This article investigates the feasibility of a monolithic gate-monitoring circuit integrated with a GaN power device and gate driver. The monitoring circuit captures 16 samples within 50 ns during the gate rising transient and stores them in on-chip capacitors. The stored voltages are asynchronously read off-chip through integrated source-follower buffers and a digitally controlled multiplexer. The proposed design incorporates approximately 330 e-HEMT transistors and was fabricated in a 200-V GaN-on-SOI process. A detailed characterization was performed to calibrate the dynamic on-chip gate voltage from the sampled values that are read off-chip, paving the way for future active control based on this feedback. Experimental results and the postcalibration estimate of the on-chip gate voltage highlight that off-chip measurements are poor and pessimistic estimators for the on-chip dynamic excursions. The on-chip gate-voltage waveform was estimated using the sampling circuit while switching the power device at 80 V, 1.5 A, demonstrating more accurate measurements of on-chip signals. This circuit stands as a proof-of-concept for the viability of integrating relatively complex circuits in GaN power ICs to perform critical monitoring and sensing tasks.

Thermal property evaluation of a 2.5D integration method with device level microchannel direct cooling for a high-power GaN HEMT device

Gallium nitride high electron mobility transistor (GaN HEMT) devices have become critical components in the manufacturing of high-performance radio frequency (RF) or power electronic modules due to their superior characteristics, such as high electron saturation speeds and high power densities. However, the high heat characteristics of GaN HEMTs make device level cooling a critical problem to solve since performance degradation or even failure may occur under high temperatures. In this paper, we proposed a 2.5D integration method with device-level microchannel direct cooling for a high-power GaN HEMT device. To demonstrate this technological concept, a multigate GaN HEMT device featuring a gate length/width/source drain spacing of 0.5 μm/300 μm/6 μm that underwent in-house backside thinning and metallization was used as the test vehicle. A high-resistivity silicon (HR Si) interposer embedded with four-layer microchannels was designed, having widths/pitches of 30 μm/30 μm at the top microchannel. The high-power GaN HEMT device was soldered on a Si interposer embedded with open microchannels for heat dissipation. A pair of GSG Pad chips was soldered simultaneously to display the capacity for the heterogeneous integration of other chip types. Thermal property evaluation was conducted with experiments and simulations. The test results showed that the maximum surface temperature of the GaN HEMT device decreased to 93.8 °C when it experienced a heat dissipation density of 32 kW/cm2 in the gate finger area and an average heat dissipation density of 5 kW/cm2 was found in the active area with the DI water coolant at a flow rate of 3 mL/min. To our knowledge, among recently reported works, this finding was the best cooling capacity of heterogeneously integrated microchannels for GaN HEMT devices. In addition, this technology was scalable regarding the numbers of gate fingers or GaN HEMT devices.

Unclamped-Inductive-Switching Behaviors of p-GaN HEMTs at Cryogenic Temperature

In this letter, the unclamped-inductive-switching (UIS) behaviors of GaN-based high-electron-mobility transistors with p-type GaN gate (p-GaN HEMTs) at cryogenic temperature (CT) are first revealed. Unlike the temperature-dependent avalanche-induced failure for SiC devices during UIS process, the withstanding behaviors and final critical breakdown voltage of p-GaN HEMT during UIS process at CT are completely consistent with the results at room temperature. As proved, the resonant circuit formed by device output capacitance and load inductor is the key factor influencing UIS waveforms, and such state is temperature insensitive. Furthermore, the inverse-piezoelectric effect induced by high electric field during UIS process is demonstrated to be the original cause that makes this temperature-independent failure phenomenon. In conclusion, the UIS withstanding capability of p-GaN HEMT will not be degraded in such an extremely low temperature scene, indicating a superiority of p-GaN HEMT for special applications compared with traditional devices.

Monolithic Integration of Gate Driver and Protection Modules With P-GaN Gate Power HEMTs

The high-speed superiority of GaN power devices with silicon-based peripheral circuits is not yet fully leveraged, mainly due to the parasitic inductance of interconnections. In this article, we demonstrate a GaN-based gate driver with an overcurrent (OC) protection circuit and an undervoltage lockout (UVLO) circuit on a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> -GaN gate power HEMT platform. The gate driver features a rail-to-rail output voltage, suppressed gate ringing, and tunable driving speed, all of which are highly desired in high-efficiency and high-speed GaN power systems. To offer timely but reliable protections, the OC protection and UVLO circuit are designed with reference to the switching speed and the threshold voltage of GaN power devices. The OC protection is implemented with a separated sensing branch and blanking time controller, and the response time to an OC event is reduced to 10 ns after the blanking time. The UVLO circuit has a fixed hysteresis of 0.5 V, and its threshold voltage is especially tailored for the GaN integrated circuits.