Gate Driver Power Research Articles

A New Symmetrical Source-Based DC/AC Converter with Experimental Verification

This research paper introduces a new topology for multilevel inverters, emphasizing the reduction of harmonic distortion and the optimization of the component count. The complexity of an inverter is determined by the number of power switches, which is significantly reduced in the presented topology, as fewer switches require fewer driver circuits. In this proposed topology, a new single-phase generalized multilevel inverter is analyzed with an equal magnitude of voltage supply. A 9-level, 11-level, or 13-level symmetrical inverter with RL load is analyzed in MATLAB/Simulink 2019b and then experimentally validated using the dSPACE-1103 controller. The experimental verification of the load voltage and current with different modulation indices is also presented. The analysis of the proposed topology concludes that the total required number of components is lower than that necessary for the classical inverter topologies, as well as for some new proposed multilevel inverters that are also compared with the proposed topology in terms of gate driver circuits, power switches, and DC sources, which thereby enhances the goodness of the proposed topology. Thus, a comparison of this inverter with the other topologies validates its acceptance.

A Novel Isolated Gate Driver Power Supply Method for Self-Powered SiC DC Solid-State Switch Using Thermoelectric Generation

DC switches using power electronics technology are increasingly used in dc power systems. Unlike other typical power electronic equipment, it is difficult for the DC switch to acquire energy from the primary circuit in the long-term closure state without d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</i> /d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> or potential difference. As a result, the gate drivers of the devices in DC switches can only be powered from the ground via a complicated and expensive secondary isolation power supply system. This paper proposes a novel isolated gate driver power supply method based on thermoelectric generation for SiC DC switches. By utilizing the unique high operating temperature of wide-bandgap devices, self-power generation can be achieved through the temperature difference between the device and the environment even without d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</i> /d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> or voltage difference. Following the comprehensive integration of the thermoelectric generator and the radiator, a 1.7kV/400A DC switch prototype capable of long-term steady self-power supply is developed, proving the efficacy of the proposed method.

A Novel SiC Device Model With Power Stage and Gate Driver Uncoupled

Silicon Carbide (SiC) power transistors have fast switching speed but are more inclined to be affected by parasitics. Miller capacitor ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C_gd</i> ) and common source inductor ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L_s_com</i> ) are two major cross coupled parameters across gate driver loop and power loop, which cause overshoots, crosstalk and decreased switching speed. To ensure a reliable and efficient switching, the impacts of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C_gd</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L_s_com</i> need to be identified and fully compensated in the gate driver. However, state-of-arts failed to provide a straightforward compensation approach with the coupling effects extracted and un-coupled model accurately represented. In this paper, a novel SiC device model with decoupled equivalent miller capacitance and common-mode inductance extracted for both gate driver loop and power loop is presented following the Miller theorem in micro-electronics. The decoupled equivalent circuit is verified to have decent accuracy in predicting the actual SiC switching transients. Furthermore, this paper proposed an improved resonant gate driver (RGD) design using the proposed decoupling model under the effects of common-mode inductance. The pre-charging current and driving pulse width are adjusted to ensure a full resonance driving transient with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L_scom</i> . The experimental results show that impact of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L_scom</i> is fully compensated, where SiC's <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">di_ds/dt</i> is improved from 1.88A/ns to 2.102A/ns, which is close to the results without <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L_scom</i> .

Integrating 10-kV SiC MOSFET Into Battery Energy Storage System With a Scalable Converter-Based Self-Powered Gate Driver

In the hardware design of battery energy storage system (BESS) interface, in order to meet the high-voltage requirement of grid side, integrating 10-kV silicon-carbide (SiC) MOSFET into the interface could simplify the topology by reducing the component count. However, the conventional gate driver design is challenging and inextensible in BESS, since the high-voltage rating and high dv/dt bring the requirements of high-voltage isolation and low common-mode capacitance. Therefore, in this article, a scalable converter-based self-powered (SCS) gate driver is further proposed. A 5-kV input power extracting converter based on a voltage-balanced SiC MOSFET stack is constructed to self-power the gate driver, which exhibits simplification of basic topology and sufficient gate driver power handling capability regardless of the switching requirement of main loop power device. Besides this, the power extracting converter is designed to act as a clamping resistor-capacitor-diode (RCD) snubber circuit, which makes the SCS gate driver scalable to the series connection of power devices. Analysis and design consideration are given in detail, followed by the experimental verification using 10-kV/10-A SiC MOSFETs.

Gate driver power supply arrangement for cascode‐connected super‐junction MOSFETs in a bridge‐leg

This letter presents a circuit for powering cascode gate driver circuits with super-junction (SJ) MOSFETs in a bridge-leg. The cascode gate driver gives inherent MOSFET intrinsic diode deactivation, and the bridge-leg incorporates an inductive turn-on snubber which controls the charging currents into the MOSFETs’ output capacitances. The cascode driver circuits and snubber inductor are configured such that the gate-drive energy is derived from the power stage.

High-Performance Isolated Gate-Driver Power Supply With Integrated Planar Transformer

Wide-bandgap and silicon power semiconductor devices require advanced pulsewidth gate-driver capability to successfully convert power for high-performance operation. In this article, a simplified forward isolated resonant converter structure with an integrated planar transformer is proposed, a cost-effective solution which eliminates the need of an output filter inductor while rearranging the clamp circuit for reduced component ratings and voltage stress. The first design option uses a simple back-to-back Zener diode voltage clamp circuit for low-power dc–dc isolated power supply applications. The second design employs a lossless voltage-clamped converter with auxiliary energy-recovering winding with an application example for an isolated gate-driver power supply. Through analysis of the converter, the switching frequency has been selected in relationship to the transformer inductance and the equivalent circuit capacitance for the benefit of soft-switching power device transitions. The proposed resonant converter structure features an integrated planar transformer designed with a specific layer disposition to ensure low interwinding capacitance. The converter offers isolated supplies for a gate-driver power devices pair, such as half-bridge SiC devices. The simulation and experimental results are obtained from a gate-driver application platform to demonstrate the validity of the proposed isolated dc–dc converter design and integrated planar transformer with a total conversion efficiency of 87.7%.

A universal automatic and self‐powered gate driver power supply for normally‐ON SiC JFETs

A universal automatic and self‐powered gate driver power supply for normally‐ON SiC JFETs

Isolated Gate Driver for Medium-Voltage SiC Power Devices Using High-Frequency Wireless Power Transfer for a Small Coupling Capacitance

A high-voltage operation and breakneck switching speed of medium-voltage (MV) silicon carbide (SiC) devices demand gate drivers (GDs) with high voltage withstanding capability, high common-mode (CM) transient immunity and a reliable short-circuit protection. An isolated GD to meet these challenging requirements is presented in this article. A novel isolated gate driver power supply using high-frequency wireless power transfer (WPT) with a nonoverlapped winding arrangement for a small coupling capacitance is proposed. Moreover, a grounded shield is added to further reduce the effective coupling capacitance and the CM current. The receiver (Rx) coil of the WPT system along with its power processing circuit have been epoxy encapsulated to achieve a very high breakdown voltage and an extremely small form factor without violating very demanding clearance and creepage distance requirements. The impact of epoxy, winding arrangement, Rx circuits, and the grounded shield on the coupling capacitance is analyzed in details. In addition, a sophisticated overcurrent protection (OCP) scheme with soft-turn-off capability for MV SiC devices is developed. The designed OCP scheme achieves fast protection and simultaneously avoids false tripping due to very high current overshoot associated with the MV SiC devices during turn-on transitions. An experimental prototype is developed and the performance of the proposed GD under various operating conditions is evaluated experimentally.

An S-CLC Compensated Load-Independent Inductive Power Relay System With Constant Voltage Outputs

This article proposes an S-CLC compensation network to achieve a relay system to power multiple gate drivers of series modules. There are three major contributions. First, it achieves the constant voltage (CV) and load-independent property, meaning the induced voltage on each receiver is immune to load variations. Second, the S-CLC circuit topology is compact to be constructed, and an integrated coil structure is proposed to limit the system size. Third, the efficiency of the power relay system is analyzed, including parasitic resistances of resonant components and coils, which reveal the load regulation phenomenon in practical applications. In order to validate the proposed topology, the parameter design methodology to achieve the highest efficiency is proposed, and a single-input-four-output prototype is implemented. The coil size is 180 mm × 175 mm, the transfer distance between receivers is 50 mm, and the switching frequency is 200 kHz. When the input dc voltage is 18 V, the induced voltage of each receiver is around 15 V, and the voltage difference between receivers is within 2 V. When the load resistances vary in a wide range from 15 to 100 Ω, the output voltage regulation rate is within 17.01%. The maximum power of the receiver can reach 13.53 W, and the maximum efficiency can reach 89.79%, showing that the proposed system can be used in practical applications. Besides, the prototype is exploited to power gate drivers with a total power consumption of 2.75 W, further verifying the practical application value.

A bidirectional diode containing multilevel inverter topology with reduced switch count and driver

SummaryIn this paper, a bidirectional diode containing multilevel inverter is introduced to reduce the number of switching elements especially in the case of a high number of output voltage levels. In comparison with classic and recently introduced symmetrical topologies, which are trying to reduce the switch count, this topology has a lower number of semiconductor switches in the same number of output voltage levels. This makes the proposed inverter to be a suitable choice for medium voltage applications like renewable energy applications as well as medium voltage electric drives. Moreover, it can be used in a cascaded configuration for high voltage levels. To depict the performance of the proposed structure, a comprehensive comparison is made between this topology and classic and recently proposed symmetric topologies in terms of switch and gate driver count, power losses, and cost. The performance of the proposed symmetrical 11‐level converter is analyzed and simulated in MATLAB/Simulink for both PWM and selective harmonic elimination switching methods. Not only the results are desirable but also the experimental results of laboratory prototype validate the simulation results.

Gate-Drive Power Supply With Decayed Negative Voltage to Solve Crosstalk Problem of GaN Synchronous Buck Converter

Gallium-Nitride (GaN) transistor suits for high switching frequency condition to build high power density converters. However, it suffers from crosstalk problem especially in bridge-structure applications, that is, the fast voltage changing of the switching node causes a positive or negative voltage spike on the gate-source voltage of GaN transistor, which results in false turn-on and gate breakdown of the transistor, respectively. Rather than specially designing the gate driver, this letter proposes an idea of using a gate-drive power supply (GDPS) with decayed negative output to solve the crosstalk problem. With the proposed GDPS, a negative driving voltage is provided when the positive voltage spike appears to avoid false turn-on, and then the negative driving voltage naturally decays to zero before the negative voltage spike appears to avoid gate breakdown. Such a GDPS is realized by a simple forward-flyback topology, and the commercial gate-drive ICs can be cooperated with it conveniently. Experimental results show the effectiveness of the proposed method.

A Time-Segmented Resonant Gate Driver Analysis for Loss, Speed, and SiC Switching Performance Trioptimization

A novel “time-segmented” transient analysis approach is proposed in this article for resonant gate driver (RGD) with triaspect optimization. RGD is a more advanced solution in high-frequency and high-power-density applications than the conventional gate driver (CGD). RGD will achieve lower gate driver loss, faster driving speed, and better SiC switching characteristics. However, the majority of current works on RGD only focused on gate driver loss and ignored its effect on power transistors' switching behavior. The characteristics of RGD are not well understood and modeled due to the ignorance of nonlinear components, such as power transistor's nonlinear input capacitor and nonlinear resonant intervals, and driving resistances. All of those result in false estimation of switching time and energy, which will cause underdesign of gate driver power supply and overdesign of resonant inductor. To fully investigate the potential of RGD, a “time-segmented” analysis approach proposed in this article utilizes the second-order equivalent circuit with actual switching transients. Different equivalent input capacitors are adopted for each segment. The impacts of the resonant inductor and gate resistor are studied. An optimized resonant inductor design is summarized by considering the three aspects mentioned earlier. Based on these, a full-bridge series RGD is designed for SiC power transistors. Compared with CGD, RGD can realize a 25% reduction in power consumption and 75.5% faster driving time. The designed RGD also improves SiC's di/dt and dv/dt up to 32%.

A Multiload Inductive Power Transfer Repeater System With Constant Load Current Characteristics

In this article, an inductive power transfer (IPT) system is designed to power multiple loads with nearly constant load currents using repeater coils. In the proposed IPT repeater system, every two repeater coils are grouped into a repeater unit and the load is connected to the first repeater coil in each repeater unit. It is deduced that the constant load current can be obtained when only considering the coupling coefficients between any two adjacent coils and omitting the coil resistances. Thus, the load power can be regulated independently, which greatly simplifies the power control design. A feasible magnetic structure is designed to meet the requirement that the coupling coefficients between the nonadjacent coils can be omitted. The relationship between the load resistances to achieve equal power distribution when considering coil resistances is derived. The proposed IPT system can be used to power gate drivers of the multiple submodules (SMs) that are connected in series in the modular multilevel converter (MMC). An experimental setup with six loads is constructed where the distance between two adjacent repeater units is 65 mm. The maximum system efficiency is around 60%.

High-Density Current-Transformer-Based Gate-Drive Power Supply With Reinforced Isolation for 10-kV SiC MOSFET Modules

With features such as faster switching frequency and higher breakdown voltage, wide bandgap power devices are key enablers to address the increasing demand for higher power density and higher efficiency in future medium-voltage converters. The 10-kV SiC MOSFET is one of such devices; yet, to fully utilize its benefits, a gate-drive power supply capable of meeting the necessary insulation (voltage) and isolation ( dv/dt voltage slew rate) requirements is needed. To this end, this article presents the complete design and optimization of such a power supply meeting four critical objectives: 1) high power density with high-voltage (HV) insulation; 2) minimum input–output capacitance; 3) fault ride-through capability; and 4) good voltage regulation. To this end, a GaN-based inductor-capacitor-capacitor-inductor (LCCL)- LC resonant converter switching at 1 MHz was used to produce a resonant current source and to supply multiple isolated loads (gate-drivers) through the single-turn primary winding loop. Experimental results are shown demonstrating the attained power density (6.3 W/in3), input–output capacitance (1.67 pF), peak efficiency (86.0%), short- and open-circuit fault withstanding capacity, and insulation rating (partial discharge inception voltage of 12 kV).

Self-Powering High Frequency Modulated SiC Power MOSFET Isolated Gate Driver

A novel implementation of an isolated gate driver for power switches is proposed in this study. The driver is bespoke designed for SiC power mosfet s. The proposal achieves the main driver characteristics—isolation capability, gate switching command, and power transfer to the secondary side by using a unique magnetic transformer. The resulting simple circuitry enables the integration of the driver into the power cell, achieving theoretical higher power density values of the final system. The principle of operation of the driver is described in detail. The original pulsewidth modulation signal is modulated with a pure ac square waveform under a two-level modulation scheme, that guarantees no saturation of the magnetic core. The signal is then magnetically coupled to the secondary side, where it is rectified and reconstructed to effectively drive the target device. In addition, the steps needed to provide a suitable design taking into account the parameters of the target power switch are also detailed. The resulting driver is characterized and a prototype of the driver is built and tested. The main results of the driver performance on a SiC mosfet -based prototype are presented. Based on the analysis of these results, this study experimentally demonstrates the feasibility of the proposal.

Ultralow Input–Output Capacitance PCB-Embedded Dual-Output Gate-Drive Power Supply for 650 V GaN-Based Half-Bridges

Wide-bandgap devices have been widely used to reduce the size and increase the efficiency of power converters by operating at a high switching frequency, at the expense of heightened radiated and conducted electromagnetic inference (EMI) emissions, of which the latter circulates through the power loop and ancillary circuitry. In effect, the parasitic isolation capacitance $C_{i}$ of the gate-driver power supply represents a key EMI propagation path to be controlled in order to ensure the operational integrity of power converters. To this end, this paper proposes an integrated, dual-output gate-drive power supply for gallium-nitride (GaN) 650 V, 60 A, half-bridge phase legs, rated at 2 W (2 × 1 W), 15 to 2 × 7 V, featuring an ultralow $C_{i}$ of 1.6 pF, an output-to-output parasitic capacitance of 1.6 pF, a power density of 72 W/in3, and an efficiency of 85%. All this is attained using an active-clamp flyback converter switching at 1 MHz using 65 V GaN high-electron-mobility transistor devices and Schottky output rectifiers, and a Pareto-optimized transformer design minimizing its interwinding capacitances, volume, and losses. Finally, the transformer is fully embedded in a printed circuit board (PCB) material, doubling as a substrate for the topside active layer of the power supply. The paper presents the complete design procedure, processing, and experimental demonstration of the proposed integrated power supply, evaluating as well the reliability impact of the magnetic-PCB material interface in high ambient temperature applications (>200 °C).

Monolithic integration of gate driver and p-GaN power HEMT for MHz-switching implemented by e-mode GaN-on-SOI process

Monolithic integration of gate driver and p-GaN power HEMT for MHz-switching implemented by e-mode GaN-on-SOI process

53‐1: Distinguished Student Paper: A Novel Low Power Gate Driver Architecture for Large 8K 120Hz LCD Display Employing IGZO Technology

A novel low power gate driver architecture was developed for large 8K 120Hz LCD panel. For this application, not only high speed driving but also low power consumption is required. We employed a high mobility IGZO, dual VGL level driving method and gate driver circuit driven by DC supply. The simulation results show that our proposals meet 8K 120Hz driving requirements. Also, we have fabricated a prototype panel and confirmed high speed driving and low power consumption.

Influence of Parasitic Inductances on Switching Performance of SiC MOSFET

Compared to the silicon power devices, silicon carbide device has shorter switch time. Hence, as a result of the faster transition of voltage (dv/dt) and current (di/dt) in SiC MOSFET, the influence of parasitic parameters on SiC MOSFET’s switching transient is more serious. This paper gives an experimental study of the influence of parasitic inductance on SiC MOSFET’s switching characteristics. Most significance parameters are the parasitic inductances of gate driver loop and power switching loop. These include the SiC MOSFET package’s parasitic inductance, interconnect inductance and the parasitic inductance of dc link PCB trace. This paper therefore focuses on analysis and comparison of different parasitic parameters under various operation conditions in terms of their effect on overvoltage, overcurrent and switching power loss.

Cascaded multilevel inverter based on symmetric–asymmetric DC sources with reduced number of components

This study presents a new module for multilevel inverters with reduced components. Each module produces 25 levels using four asymmetrical DC voltage sources (two 1V DC and two 5V DC sources) and 10 semiconductor switches. A significant advantage of the suggested module is its potentiality in producing voltage levels with negative polarity without any end side H-bridge inverter. Therefore, switches with lower voltage ratings are used in its structure. Series connection of the proposed structure leads to a modular topology which produces more voltage levels using reasonable number of switches, gate driver circuits, power diodes and less DC voltage sources. These advantages are analysed by comparing this structure with other state-of-the-art topologies. Selective harmonic elimination pulse width modulation (SHE-PWM) scheme is used to achieve output voltage with high quality. To produce all voltage levels, two algorithms are proposed to determine DC voltage sources magnitude. The accuracy of the suggested module performance in producing all voltage levels is verified by simulation and experimental results.