Gate Drain Bias Research Articles

Graphene/MoS₂ Thin Film Based Two Dimensional Barristors With Tunable Schottky Barrier for Sensing Applications

In this work, a large-area MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /graphene barristor device, with an electrically tunable Schottky barrier height, has been studied for detection of various gaseous analytes. The Schottky barrier height could be modulated by over 0.65 eV, allowing the drain current to be tuned by many orders of magnitude. Using diluted NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gases as analytes, the performance of the barristor device was compared with individual MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and graphene based planar FETs, where the barristor device outperformed its counterparts in terms of response magnitude and limit of detection. Due to the atomically thin nature of MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and graphene, electric field applied to one material could not be fully screened from the other one, which allowed both materials to act as a composite structure when analyte molecules interacted with the barristor device. This apparently reversed the dopant behavior of NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , while increasing the device sensitivity through subthreshold operation. Both conductance and capacitance based measurements are presented to highlight the charge transfer and barrier height modulation, to support the unique sensing mechanism observed in the 2D barristor device. A lower limit of detection in low ppb is established for NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and low ppm for NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , which could be further tuned by altering gate-drain bias conditions.

Current-voltage analytical model and multiobjective optimization of design of a short channel gate-all-around-junctionless MOSFET

In this paper we investigate the optimized design of a short channel gate-all-around-junctionless (GAAJ) metal-oxidesemiconductor field-effect-transistor (MOSFET), including the source-drain extensions, by means of genetic algorithm solutions applied to a compact current-voltage analytical model. In fact, due to the complex device structure, it seems useful to exploit a metaheuristic-based approach to search the optimal combination of the fundamental geometrical and physical parameters that lead to an improved performance. Through this analysis, different parameter constraints are imposed for the calculation of specific objective functions. In particular, for a fixed gate-drain bias level, the task pursues the maximization of the drain current and cut-off frequency while limiting the short channel (SC) effects. The MOSFET series resistance is also evaluated in the transition region of the Id – Vgs characteristics which appear, however, strongly affected by SC effects. The accuracy of the model is verified by comparison with experimental data reported in literature.

High performance, low temperature processed Hf-In-Zn-O/HfO2 thin film transistors, using PMMA as etch-stop and passivation layer

High performance, low operating voltage and low temperature processed Hf-In-Zn-O/HfO2 thin film transistors (HIZO/HfO2 TFTs), using spin-coated polymethyl-methacrylate (PMMA) as passivation and etch-stop layer (ESL), were fabricated and characterized. Devices showed an average field-effect mobility of 15 cm2/Vs and threshold voltage (VT) of 0.2 V, working in the operating voltage range below 2 V. The Ion/off ratio was 104. Device parameters remained without significant change after months of fabrication. Stability of PMMA passivated devices, after gate and gate-drain bias stress is compared with data reported for other materials used as ESL or passivation layer, showing similar or better performance in preventing threshold voltage shifts, hump, reduction of mobility or of the on/off current ratio.

Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective

This paper highlights the output current saturation in a line tunneling-based tunnel FET (LT-TFET). Thereafter, a novel method to extract the onset of saturation voltage ( ${V}_{\textsf {DSAT}}$ ) for LT-TFET is proposed for the first time. A soft saturation state is attained when the electron density in the epitaxial layer over the source region saturates with the drain bias ( ${V}_{\textsf {DS}}$ ) and the conduction band energy ( ${E}_{\textsf {C}}$ ) gets pinned. In addition, at the onset of deep saturation, the electron density in the epitaxial layer over the channel region drops below its doping level and ${E}_{\textsf {C}}$ becomes invariant for any further increase in ${V}_{\textsf {DS}}$ . The difference between gate–drain bias ( ${V}_{\textsf {GD}}$ ) is found to be a constant at the onset of saturation and remains independent of the gate–source overlap lengths ( ${L}_{\textsf {OV}}$ ). A shift in ${V}_{\textsf {DSAT}}$ and ${V}_{\textsf {GD}}$ is also observed with change in the thickness and doping of the epitaxial layer. The transconductance and output resistance are reasonably good in the soft saturation regime. Furthermore, a nominal change of ~5% in the voltage gain ( ${A}_{\textsf {V}}$ ) of a common source amplifier is observed when the n-device is biased in the either soft or deep saturation regime, without any tradeoff in the bandwidth.

Universal charge-conserving TFET SPICE model incorporating gate current and noise

An analytical compact model for tunnel field-effect transistor (TFET) circuit simulation is extended by adding a gate tunnel current model, a charge-based capacitor model, and a noise model. The equation set is broadly applicable across materials systems and TFET geometries and is readily fitted to rigorous physics-based device simulations and experimental results. To validate the gate current and charge models, technology computer-aided design (TCAD) simulations of a GaN/InN/GaN TFET are used. TCAD simulations show that the gate tunneling current depends on the gate-drain bias with a 100%/0% drain/source current partition. Terminal capacitances evaluated from the charge model agree well with simulations. The model is implemented in Verilog-A and the significance of gate current in the circuit design is illustrated in an amplifier design.

Room-temperature amorphous alloy field-effect transistor exhibiting particle and wave electronic transport

The realization of room-temperature macroscopic field effect transistors (FETs) will lead to new epoch-making possibilities for electronic applications. The Id-Vg characteristics of the millimeter-sized aluminum-oxide amorphous alloy (Ni0.36Nb0.24Zr0.40)90H10 FETs were measured at a gate-drain bias voltage of 0–60 μV in nonmagnetic conditions and under a magnetic fields at room temperature. Application of dc voltages to the gate electrode resulted in the transistor exhibiting one-electron Coulomb oscillation with a period of 0.28 mV, Fabry-Perot interference with a period of 2.35 μV under nonmagnetic conditions, and a Fano effect with a period of 0.26 mV for Vg and 0.2 T under a magnetic field. The realization of a low-energy controllable device made from millimeter-sized Ni-Nb-Zr-H amorphous alloy throws new light on cluster electronics.

600 V Diamond Junction Field-Effect Transistors Operated at 200$^{\circ}{\rm C}$

Blocking characteristics of diamond junction field-effect transistors were evaluated at room temperature (RT) and 200 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C. A high source-drain bias (breakdown voltage) of 566 V was recorded at RT, whereas it increased to 608 V at 200 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C. The positive temperature coefficient of the breakdown voltage indicates the avalanche breakdown of the device. We found that the breakdown occurred at the drain edge of the p-n junction between p-channel and the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -gates. All four devices measured in this letter showed a maximum gate-drain bias over 500 V at RT and 600 V at 200 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C.

The asymmetrical degradation behavior on drain bias stress under illumination for InGaZnO thin film transistors

This paper investigates behavior of drain bias stress and gate-drain bias stress under illumination for InGaZnO thin film transistors as the current-driver operated. Properties exhibit two-stage degradation behavior during drain bias stress. The photo-excited hole non-uniform trapping from illumination induces drain side barrier lowering and causes an apparent hump phenomenon of the subthreshold swing. However, the positive threshold voltage shift without a hump phenomenon after gate-drain bias stress is different degradation behaviors. It is reliant on whether or not an inversion layer exists in the channel. This work also employs capacitance-voltage measurement to further clarify the mechanism of degradation behaviors.

Capacitance Parameter Extraction and Modeling for Amorphous Silicon Thin-Film Transistors

This paper presents modeling and parameter extraction of the capacitance characteristics of the inverted-staggered a-Si:H TFT in both the depletion and inversion regions of operation. The need for a model of the capacitance with variable gate-source or gate-drain bias is imperative for a robust circuit design. However, the previous model parameter expression is applied to the staggered a-Si:H TFT. In this paper, we investigated the capacitance characteristics and modeling using the new extracted method for the inverted staggered structure. The accuracy of the simulated curves using parameters extracted with the new procedure is verified with measured and calculated data.

ROOM-TEMPERATURE COULOMB OSCILLATION OF Ni–Nb–Zr–H GLASSY ALLOY

The Ids–Vg characteristics of the aluminum-oxide glassy alloy ( Ni 0.36 Nb 0.24 Zr 0.40)90- H 10 field-effect transistor (GAFET) for gate–drain bias voltage from -50 to +50 μV were measured at room temperature. We observed four kinds of drain current oscillations for gate voltage at two-current plateau regions of -20~-15 and +35~+40 μV. The transistor showed the three-dimensional Coulomb diamond structure. From DC current standards I=ef, we get f=256 GHz for the first peak, being tunneling of one electron.

Corrosion-induced degradation of GaAs PHEMTs under operation in high humidity conditions

We have comprehensively investigated the degradation mechanism of AlGaAs/InGaAs pseudomorphic high-electron-mobility transistors (PHEMTs) under operation in high humidity conditions. PHEMTs degradation under high humidity with bias consists of a decrease in maximum drain current ( I max) caused by a corrosion reaction at the semiconductor surface at the drain side. The decrease in I max is markedly accelerated by the external gate–drain bias ( V dg ). This originates from a reduction in the actual activation energy ( E a 0) by V dg . The degradation depends on the surface treatment prior to deposition of the SiN x passivation film. The reduction of As-oxide at the SiN x /semiconductor interface suppresses the corrosion reaction.

Correlation Between DC–RF Dispersion and Gate Leakage in Deeply Recessed GaN/AlGaN/GaN HEMTs

Employing deeply recessed GaN/AlGaN/GaN high-electron mobility transistors, we experimentally demonstrate the correlation between the DC-RF dispersion and the gate leakage current. It was found that both the DC-RF dispersion and the gate leakage are strongly affected by surface charging. The impact of surface charging can be controlled by using GaN/AlGaN/GaN structures with varied GaN cap thickness. In the absence of field plates, the tradeoff between the DC-RF dispersion and the gate leakage can be compromised by choosing a proper GaN cap thickness. Our optimum epistructure design yields an output power density of 5.6 W/mm with an associated power added efficiency of 72% at 28-V bias and 4-GHz frequency. The gate leakage current is as low as 30 muA/mm at up to 40-V gate-drain bias.

Anomalous polarization switching in organic ferroelectric field effect transistors

The authors demonstrate organic ferroelectric field effect transistors using poly(vinylidene fluoride-trifluoroethylene) as dielectric in bottom common gate and patterned gate devices. Drain current hysteresis is resulted from the dipole switching at channel region due to gate-source bias. For common gate device, an additional anomalous polarization switching is observed due to gate-drain bias. This switching has no effect on the hysteresis direction yet incurs a strong peak in the off drain current leading to unstable and uncontrollable off state in memory device. Reduction of gate-drain overlapping using patterned metal gate shows diminishing the anomalous switching hence improves performance of the ferroelectric transistors.

Passivation of Poly-Si Thin-Film Transistors With Ion-Implanted Deuterium

AbstractA comparison of ion-implanted deuterium and ion implanted hydrogen for passivation of grain boundary states in poly-Si thin film transistors (TFTs) is presented for the first time. Gate-drain bias stressing was carried out after anneals at 350 °C, 400 °C, and 450 °C. Under stress, deuterated TFTs are more resistant to bias stress than hydrogenated TFTs in terms of most PMOS performance parameters and NMOS leakage current, but are markedly less resistant to NMOS threshold degradation. While still showing promise, these results are not as impressive as those shown for hot carrier degradation in very large scale integration (VLSI) MOS devices. After 350 °C activation anneal, deuterium is less effective than hydrogen at initial device passivation, probably as a result of excessive implant damage. After anneals at 400 or 450 °C, deuterium becomes more effective at passivation than hydrogen, possibly due to differences in diffusion between hydrogen and deuterium.

An analytic solution of the two-dimensional poisson equation and a model of gate current and breakdown voltage for reverse gate-drain bias in GaAs MESFETs

The breakdown voltage of a GaAs MESFET is generally specified by a two-terminal measurement, either with the source and drain grounded or with the source floating. To predict the breakdown voltage, the 2-D Poisson equation is solved analytically to obtain the field distribution. A model is proposed for the reverse gate current-voltage characteristics. Using this model the reverse gate-drain breakdown voltage is calculated with a defined gate current for different doping concentrations and active layer thicknesses.