Gate Diode Research Articles

Gan Vertical Power Finfets Using BN As Gate Dielectric

Over the past few decades, the semiconductor industry has undergone rapid advancements and transformative evolution, particularly in semiconductor materials. Wide bandgap (WBG) semiconductors, represented by gallium nitride (GaN) and silicon carbide (SiC), offer significant advantages over traditional silicon-based technologies. This research explores the suitability of BN as a dielectric material in GaN vertical power FinFETs, specifically targeting high-temperature applications. BN thin films are directly deposited by microwave-plasma-assisted chemical vapor deposition (CVD). The presence of BN is confirmed by X-ray photoelectron spectroscopy (XPS). GaN/BN vertical FinFETs are demonstrated for the first time with a current on-off ratio of 10. The high-resolution transmission electron microscopy (HRTEM) reveals the presence of BN on GaN non-polar sidewalls. BN metal-insulator-semiconductor (MIS) gate diode demonstrates increased breakdown voltage compared to GaN Schottky gate diode. Hydrogen plasma has been pinpointed as the main culprit behind variations in dielectric film thickness and the deterioration of crystal quality, both of which contribute to increased gate leakage current. Through the optimization of deposition conditions, the enhanced device demonstrates outstanding performance and maintains stable operation at temperatures up to 573K. This study provides a valuable foundation for future research on BN-based gate dielectrics in GaN vertical transistors.

Enhanced device performance of GaN high electron mobility transistors with in situ crystalline SiN cap layer

In this paper, a ∼2 nm in situ SiN cap layer on AlGaN barrier layer is grown, which is revealed to be crystalline using high-resolution cross-sectional transmission electron microscopy. Benefitting from superior interface quality of epitaxial crystalline SiN/AlGaN interface, the gate diodes with in situ SiN cap layer feature lower interface trap state density than that with GaN cap layer. By comparing the GaN high electron mobility transistors (HEMTs) with the conventional GaN cap layer, the GaN HEMTs with in situ SiN cap layer exhibit improved device performance, showing higher electron mobility, higher drain current, larger on/off current ratio, and higher transconductance. For breakdown characteristics, the devices with in situ crystalline SiN cap layer show prominent advantages over the GaN cap layer with a 30% breakdown voltage increase to 810 V.

Research on Single-Event Burnout Reinforcement Structure of SiC MOSFET.

In this paper, the single-event burnout (SEB) and reinforcement structure of 1200 V SiC MOSFET (SG-SBD-MOSFET) with split gate and Schottky barrier diode (SBD) embedded were studied. The device structure was established using Sentaurus TCAD, and the transient current changes of single-event effect (SEE), SEB threshold voltage, as well as the regularity of electric field peak distribution transfer were studied when heavy ions were incident from different regions of the device. Based on SEE analysis of the new structural device, two reinforcement structure designs for SEB resistance were studied, namely the expansion of the P+ body contact area and the design of a multi-layer N-type interval buffer layer. Firstly, two reinforcement schemes for SEB were analyzed separately, and then comprehensive design and analysis were carried out. The results showed that the SEB threshold voltage of heavy ions incident from the N+ source region was increased by 16% when using the P+ body contact area extension alone; when the device is reinforced with a multi-layer N-type interval buffer layer alone, the SEB threshold voltage increases by 29%; the comprehensive use of the P+ body contact area expansion and a multi-layer N-type interval buffer layer reinforcement increased the SEB threshold voltage by 33%. Overall, the breakdown voltage of the reinforced device decreased from 1632.935 V to 1403.135 V, which can be seen as reducing the remaining redundant voltage to 17%. The device's performance was not significantly affected.

Improved electrical performance of InAlN/GaN high electron mobility transistors with forming gas annealing

The surface electronic states and defects of gallium nitride based high-electron-mobility transistors (HEMTs) play a critical role affecting channel electron density, electron mobility, leakage current, radio frequency (RF) power output and power added efficiency of devices. This article demonstrates the improved surface properties of InAlN/GaN HEMTs through forming gas (FG) annealing, resulting in a significantly improved electrical properties. The X-ray photoelectron spectra reveals a reduction of surface native oxide after FG H2/N2 annealing whereby the amount of Ga–O bonds is decreased. Compared with N2 annealing, an on-resistance of 1.68 Ω·mm, a subthreshold swing of 118 mV/dec, a transconductance peak of 513 mS/mm, a gate diode breakdown voltage of surpassing 42 V, and a high current/power gain cutoff frequency (fT/fmax) of 165/165 GHz are achieved by the 50-nm InAlN/GaN HEMT on Si substrate.

Dual-directional SCR device with dual-gate controlled mechanism for ESD protection in photoelectric chip

The dual-directional silicon-controlled rectifier (DDSCR) is an electrostatic discharge (ESD) protection device. It can provide positive and negative ESD surge paths and has excellent robustness. However, industry-level sensors operating in strong electromagnetic interference environments impose higher reliability requirements on photoelectric chips. This paper proposed a novel DDSCR with a dual-gate controlled mechanism. By incorporating the gate diode triggering and the gate field modulation mechanism into the traditional DDSCR, and further utilizing additional parasitic bipolar junction transistors (BJTs) for diversion, the proposed device exhibits significantly improved ESD characteristics. Measurement results indicate that, compared to DDSCR, the proposed device exhibits a 27.5% reduction in trigger voltage (Vt1 ), a 96.1% improvement in holding voltage (Vh ), and achieves an equivalent human body model protection level of 11.45 kV, demonstrating exceptional design area efficiency. The experimental findings validate the effectiveness of the proposed device in 5 V photoelectric chip applications.

A Graphene Geometric Diode with the Highest Asymmetry Ratio and Three States Gate‐Tunable Rectification Ability

AbstractGraphene geometric diodes, with applications in THz detection, energy harvesting, and high‐speed rectification, have been previously constrained by graphene quality and geometry feature size. This study presents significant advancements in graphene geometric diodes by employing the h‐BN/monolayer graphene/h‐BN heterojunction and extremely precise electron beam lithography. Two distinct designs of graphene geometric diodes with neck widths of 23 and 26 nm are fabricated, the superior of which demonstrated an asymmetry ratio of 1.97, a zero bias current responsivity of 0.6 A W−1, and a voltage responsivity of 12,000 V W−1, setting new benchmarks for such devices. Integrating this device into a rectification circuit, the experimentally validate that the rectified DC output voltage can be dynamically modulated and even inverted through adjustments to the diode's gate voltage. This behavior aligns seamlessly with graphene's intrinsic tunability of charge carriers, implying promising prospects for the device's application in advanced logic circuits, bidirectional switches, and signal modulation/demodulation techniques.

A Unified Open-Circuit-Fault Diagnosis Method for Three-Level Neutral-Point-Clamped Power Converters

Fast and accurate fault diagnosis is important to enhance the reliability of power converters. Since both open-circuit faults in insulated gate bipolar translator (IGBTs) and diodes deteriorate power quality, diagnosis methods only focusing on IGBT failures are easily disturbed by diode failures. In this work, we propose a unified effective residual-based open-circuit fault diagnosis method for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">all</i> semiconductor devices including IGBTs, clamping diodes, and freewheeling diodes in three-level neutral-point-clamped power converters. The voltage and current residuals are calculated from the mismatches between the actual current path and the estimated one, requiring <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">solely</i> the already existing current measurement of the system. By analyzing the variation of the voltage and current residuals in all open-circuit failure cases, the proposed diagnosis method can locate the faulty switch within several sampling periods, i.e., less than 1 ms. Finally, the proposed diagnosis method is incorporated in the model predictive current control framework. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Both</i> experimental <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">and</i> hardware-in-the-loop results confirm the effectiveness and robustness of the proposed diagnosis method at various operation scenarios.

On the optimization of underwater quantum key distribution systems with time-gated SPADs

In this paper, we study the effect of various transmitter and receiver parameters on the quantum bit error rate (QBER) performance of underwater quantum key distribution. We utilize a Monte Carlo approach to simulate the trajectories of emitted photons transmitting in water from the transmitter towards the receiver. Based on propagation delay results, we first determine a proper value for the bit period to avoid intersymbol interference as a result of possible multiple scattering events. Then, based on the angle of arrival of the received photons, we determine a proper field of view to limit the average number of received background noise. Finally, we determine the optimal value for the single photon avalanche diode gate time in the sense of minimizing the QBER for the selected system parameters and given propagation environment.

Leakage current reduction of normally off hydrogen-terminated diamond field effect transistor utilizing dual-barrier Schottky gate

Normally Off diamond field-effect transistor (FET) is demanded for energy saving and safety for practical application. Metal/diamond Schottky junction serving as the gate is a simple and effective approach to deplete holes under the gate, whereas low Schottky barrier height (SBH) is undesirable. In this work, a dual-barrier Schottky gate hydrogen,oxygen-terminated diamond (H,O-diamond) FET (DBG-FET) with Al gate was realized. Normally Off DBG-FET with enhanced SBH and reduced leakage was achieved. H,O-diamond, which was defined by x-ray photoelectron spectroscopy (XPS) technique, was realized by ultraviolet ozone (UV/O3) treatment with nanoparticle-Al mask. The enlarged SBH of 0.94 eV owing to the C–O bond minimized the diode reverse current and nicely shut down the DBG-FET at zero gate bias. Moreover, the forward current of diode can be well-reduced by hundred times ascribed to oxidized Al nanoparticles during the UV/O3 process. Based on this diode gate structure, the maximum drain current density, transconductance, on/off ratio, and subthreshold swing of the normally off DBG-FET are 21.8 mA/mm, 9.1 mS/mm, 109, and 96 mV/dec, respectively. The DBG-FET is expected to promote the development of normally off diamond FETs.

Self-Balanced Twenty Five Level Switched Capacitor Multilevel Inverter With Reduced Switch Count and Voltage Boosting Capability

Multilevel inverters (MLI) are gaining wider popularity owing to their increasing power handling capability and improving power quality output. With an inclining trend towards renewable energy utilization, they find a vital application in wind and solar power generation systems. This article proposes a new multilevel dc–ac inverter. The proposed MLI produces a twenty five level output and offers an inherent capacitor self-balancing capability. The inherent self-balancing eliminates the requirement of auxiliary sensor circuit or capacitors voltage balancing algorithms. Dual asymmetric voltage sources and switched capacitors along with their proper charging/discharging pattern are utilized for the generation of output levels. A voltage gain of 2 and a total standing voltage (TSV) of 10 is achieved though the proposed inverter. In order to realize the merit of the proposed MLI over recently developed topologies, a comparative analysis in terms of system components such as numbers of power electronic switches, gate driver circuits, diodes, and capacitors as well as system parameters such as voltage gain, TSV and power loss is presented. The proposed MLI is developed in the laboratory and is controlled through the digital signal processor TMS320F28379D using nearest level control technique. The experimental results are acquired for different loads and under varying modulation index to validate the feasibility of the proposed inverter.

Low Switching Loss Split-Gate 4H-SiC MOSFET With Integrated Heterojunction Diode

A 4H-SiC MOSFET with p-type region injection and integrated split gate and heterojunction diode is proposed in this paper. Compared with the conventional MOSFET, the proposed structure has a lower on-resistance and switching loss. And the gate oxide layer has been well protected by the p-type region, which reduces the electric field in gate oxide layer at the off-state. The on-resistance of device can be greatly reduced by increasing the doping concentration of current spreading layer and will not cause a huge electric field in gate oxide layer. The specific on-resistance is decreased by about 27.8% and the static characteristic (BV/Ron,sp) of the device is improved about 37.3%. SiC material has a high third quadrant turn-on voltage due to its wide band gap characteristics. The use of heterojunction integration can take place of parasitic body diode and reduce its turn-on voltage, avoid the bipolar degradation effect, and improves the reverse recovery characteristics. To evaluate the dynamic performance, the reverse transmission capacitance (Crss) and gate-drain charge (Qgd) of the proposed structure have been studied in this paper via numerical simulations. Based on the simulation, the HF-FOM (Crss&#x00D7;Ron,sp) and HF-FOM (Qgd&#x00D7;Ron,sp) of the proposed structure are decreased by about 87% and 86%, respectively. Meanwhile, the reverse turn-on voltage and reverse recovery characteristics are also improved, and the total energy loss decreases by about 37.3%.

Failure Rate and Economic Cost Analysis of Clamped-Single Submodule with DC Short Current Protection for High Voltage Direct Current System

Clamped-single submodule (CSSM) has DC short circuit current protection function to improve the safety and stability of high voltage, direct current (HVDC) system. In order to carry out the protection, it needs an additional number of insulated gate bipolar transistors (IGBTs) and diodes compared to the conventional half-bridge submodule (HBSM). In general, the failure rate tends to increase in proportion to the number of circuit components. Also, complex operation of the submodule may increase the failure rate, so accurate reliability analysis considering these points is required to apply CSSM in a practical HVDC system. We estimate the failure rate and the mean time between failures (MTBF) of CSSM using a fault tree. Fault-tree analysis (FTA) is possible to analyze the failure rate more accurately than the prior part count failure analysis (PCA) that considers only the number of parts, the type of parts, and the connection status of each circuit component. To provide guidelines for submodule selection under various conditions, we compare the economic cost of a CSSM with HBSM, FBSM, and clamped-double submodule (CDSM), and analyze the failure rate according to the voltage margin of the parts.

A Novel Split-Gate-Trench MOSFET Integrated With Normal Gate and Built-In Channel Diode

A novel split-gate-trench MOSFET integrated with normal gate and built-in channel diode (BCD) in the same trench is proposed and simulated with Sentaurus TCAD in this paper. Compared with the conventional SGT MOSFET (C-SGT MOS) and conventional SGT MOSFET with built-in channel diode (CBCD-SGT MOS), the proposed MOSFET exhibits superior performances, such as smaller turn-on voltage and lower reverse recovery charges when working in the third quadrant, and reduced gate charge and gate-to-drain charge when working in the first quadrant. With the negligible degradation of the on-state resistance, significant improvements in the figures of merit can be obtained. What’s more, obvious uniform forward and reverse conduction current distribution of proposed structure is observed compared to CBCD-SGT MOS although two types of devices are both featuring BCD structure, which could increase the robustness of device when working in high-power and high-frequency applications.

Effects of constructal theory on thermal management of a power electronic system

Thermal management of power electronics (PE) systems is a long-lasting challenge in their industrial applications. It is important to provide a uniform temperature distribution on the surface of the insulated gate bipolar transistors and diodes. The thermal management of a PE module is the main objective of the present study. The flow characteristics and the effects of the constructal theory on the heat transfer performance of the cooling system have been numerically investigated. The governing equations have been discretized using the finite volume method, and validation has been done to make sure the results are reliable. The effects of different channels configurations on decreasing the chips’ temperature and uniform temperature distribution on the chips’ surface have been studied. The flow characteristics and heat transfer performance at different mass flow rates for different channel configurations have been studied by presenting the results of the average chips’ temperature, Nusselt (Nu) number, pressure loss, and standard temperature deviation. Moreover, different temperature distribution contours have been presented to show the performance of different configurations. The results revealed that by changing the channels’ configuration from the conventional straight channel to leaf-inspired channels (case B and C), the cooling performance is improved.

Photo-Triggered Logic Circuits Assembled on Integrated Illuminants and Resonant Nanowires

High-performance photo-triggered electronic devices have already become an abiding target of optoelectronics. Current results, involving high-sensitivity phototransistors with the enhancement of material properties or the modification of electrical field, need an independent external light-source system. Nevertheless, few research studies inform of circuits in which the logic channel can be directly light controlled by a fully integrated photogate. In this paper, nanowire-based photon-effect transistors (PETs) combined with organic light-emitting diode (OLED) gates, and the photo-triggered nanowire circuits (PTNCs) are exhibited. The nanowire channels are manifested as high-quality optical cavities coupled by reflective electrodes for forming standing wave resonance. With the function of resonance, the nanowire channel under the illumination of the OLED gate can reach a high on/off ratio of ∼107, and under the different interconnected configuration of OLED gates, the functions of PETs can separately be realized as P-type and N-type of CMOS-like transistors. Then, a PTNC inverter that includes two nanowire channels with the respective OLED gates is operated utilizing electrical input voltage and logic opposite output signal. NAND and NOR gates as PTNC have also been demonstrated and indicate their corresponding outstanding arithmetic logic operation. PTNCs can effectively represent an innovative step toward multipurpose photonic circuits as to programmable logic components and photo-triggered computing.

High Performance and Efficiency Resonant Photo-Effect-Transistor by Near-Field Nano-Strip-Controlled Organic Light Emitting Diode Gate.

Phototriggered devices have attracted attention due to their exceptional characteristics, advanced multifunctionalities and unprecedented applications in optoelectronic systems. Here, we report a pioneer structural device, a resonant photoeffect-transistor (RPET) with a functionalized nanowire (NW) charge transport channel, modulated by a near-field nanostrip organic light emitting diode (OLED) and controlled by a gate bias to realize exceptional photoelectric properties. The RPET presents high-quality nanowire channel characteristics due to tunable optical cavities manifesting strong standing wave resonance under controlled light emission. To enhance performance, methodical analyses were carried out to determine the effects of the structural design, electric field distribution and charge carrier generation on photoresponsivity when light traverses a single or multiple nanoslit masks. The developed RPET yields stable photocurrents in the 105 range and generates current on/off ratios upward of 106 under the influence of intense electromagnetic distribution, effectively lending itself to promising opportunities in fully integrated optoelectronic devices.

A Comparison between IGBTs and Diode Converters for DC Railway Electrification Systems

This paper describes a comparison between the specific DC railway models with insulted gate bipolar transistors rectifiers and diode rectifiers. As silicon diode was applied to railway electrification system decades ago, the IGBTs rectifiers have not obtained wide application yet. In this research, the performance of these rectifiers is presented and analysed. The power supply to the load, system losses and effects to systems are the main aspects compared in this paper. The analysis presents the possibility that new types of power converters can be adapted in DC railway electrification system. The simulations are carried out with MATLAB and Simulink.

A Universal Wideband Device-Level Parallel Simulation Method and Conducted EMI Analysis for More Electric Aircraft Microgrid

The validation of electromagnetic compatibility for the microgrid of a more electric aircraft (MEA) is an essential test item before delivery for a trial flight, and it has always been urgently expected to be involved during the design stage. This article presents a universal method for wideband modeling and simulation of the MEA microgrid system in the time domain, regardless of the fact that motors are driven by which kind of converter, e.g., modular multilevel converter (MMC), 3-L neutral-point clamped (NPC), or 2-L pulsewidth modulation (PWM) converters. The insulated gate bipolar transistor and diodes are modeled with the physics-based dynamic model to emulate not only precise system-level performance of the system, but also to get an insight into the high-frequency oscillation between junction capacitance of the semiconductor modules and the parasitic parameters and high-frequency branch of other components, such as the permanent magnet synchronous motor (PMSM), transformer, and generator. To alleviate the attendant computational challenge, which could be extremely time-consuming (if no nonconvergence problem is encountered) when solved on traditional simulation platform, circuit partition based on transmission line decoupling, Norton equivalent parameter extraction, and TLM-link decoupling of submodules from the MMC bridge arms are utilized. The simulation program is executed on GPU to achieve massively parallel and accelerated solution. The accuracy and efficiency of the GPU-based parallel algorithm are validated by the comparison with the experimentally verified model in ANSYS Simplorer.

Determination of RMS Current Load on the DC-Link Capacitor of Voltage Source Converters Using Direct Current Control

RMS current load is one of the most important design criteria for the dc-link capacitors of voltage source converters. In the literature, determination of this rms current load is well documented for state-of-the-art modulation schemes, such as space vector modulation. But the methods presented cannot be applied for direct current control algorithms. Therefore, this article introduces a new approach especially for direct current controllers, which reflects and compares to the state-of-the-art calculation method for space vector modulation. As direct current control is a feedback control, no closed-form solution can be given. Instead, the dc-link capacitor rms current load is determined by an iterative calculation scheme as a function of the modulation level and the phase angle. Although the scheme presented is applied to a three-phase two-level voltage source converter, it can be adapted to any voltage source converter topology. An example is presented applying the calculation method to one specific direct current control algorithm. The calculated results are verified via a digital simulation model as well as test bench measurements showing good correlation. For correct comparison, different effects are considered and discussed between simulation, calculation, and measurement results. These contain transients, the commutation process between insulated gate bipolar transistor (IGBT) and diode, the current-dependent voltage drop of the semiconductors, and the stationary current error of the hysteresis control. The dc-link capacitor current load for space vector modulation is calculated analytically as a reference by using the state-of-the-art method. The comparison of results obtained in this article and the reference are very similar, which is discussed in the conclusion.

A High-Voltage DC–DC Buck Converter With Dynamic Level Shifter for Bootstrapped High-Side Gate Driver and Diode Emulator

Considering the propagation delay, dVSW/dt immunity, and power dissipation issues in the bootstrapped high-side gate driver design, a monolithic high-voltage dc-dc buck converter with a high-speed dynamic level shifter and improved gate drive buffer is presented in this article. With the introduction of instantaneous dynamic current, the propagation delay of the level shifter is reduced to 1.13 ns for the high-side switch. The dVSW/dt immunity is enhanced by a dynamic current compensation during positive slewing and a diode voltage clamp during negative slewing. The average current consumption of the level shifter is only 8.45 μA at a switching frequency of 1 MHz. The proposed gate drive buffer eliminates the shoot-through current with the use of dead-time control. The compact level shifter and buffer are also used to drive an integrated p-channel mosfet transistor serving as a bootstrap diode emulator. Experimental results show that the fabricated converter with the proposed scheme regulates well with an 18 V input, 1.05 V output, and 2 A load current. Also, high efficiency of up to 93% is achieved.