Gate Diffusion Input Research Articles

Optimized Design and Applications of Arithmetic Logic Units: Addressing Power Efficiency and Performance in Diverse Computing Applications

In modern computer systems, the Arithmetic Logic Unit (ALU) is the core component of the central processing Unit (CPU) and performs basic tasks such as arithmetic operations, logic operations, and data transmission. With the development of information technology, the demand for computing is growing, the requirements for computing accuracy, speed and energy consumption are becoming more stringent. The design and optimization of ALU is directly related to the overall performance and energy efficiency of the system, so it becomes the focus of research and the key to technological breakthroughs. This paper focuses on summarizing and exploring the application scenarios, development, and optimization prospects of ALUs. This study reviews various application contexts, including embedded systems, quantum computing, and high-performance processors, highlighting how tailored ALU designs can meet the demands of each. In the field of optimization strategies, Gate Diffusion Input (GDI) technology, reversible logic, and Single Electron Transistor (SET) technology were discussed as a way to reducing power consumption and improving processing speeds.

Statement of Removal: Design and analysis of 1-bit hybrid full adder cells for fast computation

ABSTRACT This research article introduces a 1-bit Full Adder (FA) cell comprising 20 transistors, employing Gate Diffusion Input (GDI) and transmission gate logic. The FA cell is segmented into four modules: the first module encompasses an AND-OR module, followed by a module housing a Multiplexer (MUX) based on transmission gates for Carry Output generation. The remaining two modules are XOR gates dedicated to Sum Output generation. Simulation of the proposed design is conducted on the 45 nm technology node using Cadence Virtuoso and its GPDK 45 nm library. To validate the performance of the proposed design, it is compared against existing full adders. Performance parameters such as power consumption, delay and Power Delay Product (PDP) demonstrate superior performance across voltages ranging from 0.8 V–1.2 V.

Design and analysis of 1-bit hybrid full adder cells for fast computation

ABSTRACT This research article introduces a 1-bit Full Adder (FA) cell comprising 20 transistors, employing Gate Diffusion Input (GDI) and transmission gate logic. The FA cell is segmented into four modules: the first module encompasses an AND-OR module, followed by a module housing a Multiplexer (MUX) based on transmission gates for Carry Output generation. The remaining two modules are XOR gates dedicated to Sum Output generation. Simulation of the proposed design is conducted on the 45 nm technology node using Cadence Virtuoso and its GPDK 45 nm library. To validate the performance of the proposed design, it is compared against existing full adders. Performance parameters such as power consumption, delay and Power Delay Product (PDP) demonstrate superior performance across voltages ranging from 0.8 V–1.2 V.

A STUDY ON LOW-POWER ALU DESIGN LEVERAGING VARIOUS ADVANCED OPTIMIZATION METHODS

VLSI technology has advanced significantly, and there are numerous effective methods for creating VLSI circuits. PTL, GDI (Gate Diffusion Input) methods, and CMOS are a few of the styles. The weaknesses of CMOS and PTL approaches can be eliminated by using the GDI technique to create low-power digital combinatorial circuits. This method maintains a low level of logic design complexity while lowering the amount of power consumed, propagation latency, and size of digital circuits. This paper discusses the benefits and limitations of GDI compared to CMOS design by comparing the various approaches with respect to layout area, transistor count, latency, and power dissipation.

Energy-efficient design and CNFET implementation of GDI-based ternary prefix adders

Abstract Ternary adders have produced more benefits compared to binary adders i.e., the ternary adder occupies less amount of area as well as produces less interconnect complexity. However, the CMOS implementation of the ternary adders failed to perform the process when the channel length was taken as 32 nm. At 32 nm technology, the CMOS transistors exhibit undesired effects such as Short Channel Effects (SCEs), mobility degradation, high leakage current, etc. Multi-gate devices are preferred to overcome these issues. Carbon Nano-tube Field Effect Transistors (CNFETs) are one of the technologies to work efficiently when the channel length is 32 nm. In this paper, CNFET-based ternary prefix adders are designed. Power consumption is the most critical requirement for the VLSI system, as it enhances energy efficiency and reduces heat dissipation. One way to achieve this power reduction is by minimizing the number of transistors employed in the adder circuits. This study employed a reduction technique known as Gate Diffusion Input (GDI) logic included in the proposed prefix adder design. The overall experimental investigation is done with the help of the HSPICE supporting platform. The proposed adder improved by reducing the power by up to 83%, energy by up to 83%, current by up to 78%, and delay by up to 96%. Finally, the Power Delay product (PDP) was also reduced by 84% compared to existing ternary adders. The proposed design proves to be highly effective in implementing the neuron structure, with the corresponding parameters thoroughly analysed and well-documented in this study.

New Approach in Booth Decoder/Encoder and 5-2 Compressor for Multipliers

This paper proposes two novel approaches: a signed–unsigned modified Booth decoder/encoder that is used for the production of partial products and a 5-2 compressor for the addition stage of partial products. The improvement of a circuit can be done at the transistor level and the gate level. To improve the circuits at the gate level for the modified Booth decoder/encoder, a new table was designed and also the 5-2 compressor was obtained by changing the truth table. Speed, power consumption and area were improved in the proposed structures. In this paper, at the transistor level, the gate diffusion input (GDI) technique was used to implement logical gates and the gate-level delay of the GDI structures was also calculated. The results indicated that the proposed 5-2 compressor had a delay of 119 ps with a power consumption of 65[Formula: see text][Formula: see text]W, which shows a 23.5% improvement in power delay product (PDP) compared to the best structure in the comparison table, whereas the proposed Booth decoder/encoder had a delay of 257 ps with a power consumption of 61.74[Formula: see text][Formula: see text]W and shows a 63.7% improvement in PDP compared to previous studies. By using the proposed structures in the multiplier, a 22% improvement in PDP was observed. To simulate the obtained structures, the TSMC 0.18 and 0.09[Formula: see text][Formula: see text]m technologies and the HSPICE software were used. Cadence software was used to implement the layouts of the proposed structures.

Realization of a high-efficient GDI-based 4:2 compressor for sum of absolute difference detection in image and signal processing

A new 4:2 approximate compressor is designed based on gate diffusion input (GDI), which has 14 transistors and only 6 errors in its outputs. The integration of the GDI with the dynamic threshold (DT) overcomes the body effect by the selection of carbon nanotube field-effect transistors (CNTFET) technology. By embedding the proposed compressor in the 8-bit sum of absolute difference (SAD) system, an area of 284.6 µm2 is occupied and a reliable system for difference detection between two images and electrocardiogram (ECG) results. Considering the fair conditions of comparison, the proposed circuit has significant performance in terms of circuitry parameters such as power, delay, and figure of merits (FoMs). In terms of power-delay-product (PDP) and power-delay-area-product (PDAP) the proposed cell shows a saving of 27 % and 47 %, respectively. A 40 % improvement in terms of a FoM containing PDP and power signal-to-noise ratio (PSNR) compared to the closest competitor qualifies the proposed circuit over the other counterparts. The proposed cell has a high performance under the difference detection in images and ECGs.

Comparative Analysis of High Speed and Area Efficient Full-Adder using CMOS and MGDI Techniques

Extremely quick processing is crucial for very large-scale integrated (VLSI) circuits in the arithmetic logic unit. Complementary metal oxide semiconductor (CMOS) and modified gate diffusion input (MGDI) are beneficial technologies for designing high-speed circuits with better reliability and performance with regard to area and power consumption. This research work provides a comparative performance analysis of a full adder that is implemented with CMOS and MGDI technology. This work aims to develop a CMOS-based full-adder and a MGDI-based full-adder circuit for area-efficient and high-speed applications. First, the analysis and implementation of the XOR and NAND logic gates are designed using CMOS technology and the MGDI technique to create a full-adder design. The comparative analysis of integrated circuits in CMOS and MGDI technologies is primarily determined by the number of transistors and delay time. The full-adder is designed and analyzed using 90 nm technology, with performance characteristics evaluated using Cadence Virtuoso Tools.

High Efficiency Carry Save Adder using Modified–gate Diffusion Input Technique

Addition is a fundamental function in the design of a digital system, necessary for applications such as signal processing, arithmetic operations, multiplexers, and control systems. Hence, the digital system’s performance is considerably reliant on the efficiency of the adders. Therefore, designing a 4-bit carry save adder (CSA) that consumes less power, occupies a smaller area, and operates at a higher speed is proposed using the modified–gate diffusion input (MOD–GDI) technique. The primary focus is to reduce the area occupied by decreasing the transistor count as compared with other logic styles (i.e., conventional, and Boolean simplification) for CSA through Cadence Virtuoso simulation based on SilTerra 180 nm technology. Notably, the number of transistors is reduced from 42 in the conventional full adder to 11 in the proposed MOD–GDI design. As a result, the proposed 4-bit CSA with MOD–GDI technique is efficient in improving the speed of addition by reducing the area and power consumption.

Design and simulation of a new QCA-based low-power universal gate

Quantum-dot Cellular Automata (QCA) is recognized in electronics for its low power consumption and high-density capabilities, emerging as a potential substitute for CMOS technology. GDI (Gate Diffusion Input) technology is featured as an innovative approach for enhancing power efficiency and spatial optimization in digital circuits. This study introduces an advanced four-input Improved Gate Diffusion Input (IGDI) design specifically for QCA technology as a universal gate. A key feature of the proposed 10-cell block is the absence of cross-wiring, which significantly enhances the circuit’s operational efficiency. Its universal cell nature allows for the carrying out of various logical gates by merely altering input values, without necessitating any structural redesign. The proposed design showcases notable advancements over prior models, including a reduced cell count by 17%, a 29% decrease in total energy usage, and a 44% reduction in average energy loss. This innovative IGDI design efficiently executes 21 combinational and various sequential functions. Simulations in 18 nm technology, accompanied by energy consumption analyses, demonstrate this design’s superior performance compared to existing models in key areas such as multiplexers, comparators, and memory circuits, alongside a significant reduction in cell count.

A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology

Multipliers are essential components within digital signal processing, arithmetic operations, and various computational tasks, making their design and optimization crucial for improving the efficiency and performance of integrated circuits. Among multiplier architectures, Vedic multipliers stand out due to their inherent efficiency and speed, derived from ancient Indian mathematical principles. This study presents a comprehensive analysis and comparison of 4-bit Vedic multiplier designs utilizing Gate Diffusion Input (GDI), Complementary Metal-Oxide-Semiconductor (CMOS), and Transmission Gate (TG) technologies, utilizing different adder architectures such as Ripple Carry Adder (RCA), and Carry Lookahead Adder (CLA), Carry Skip Adder (CSA). The objective is to explore the performance, area, and power consumption characteristics of these multipliers across different technologies and adder implementations. Each multiplier architecture is meticulously designed and optimized to leverage the unique features of the respective technology while adhering to the principles of Vedic mathematics. The designs are evaluated based on parameters such as transistor count, delay, power dissipation, and area. The results demonstrate the effectiveness of GDI technology in terms of in tems of delay, area, power and PDP when compared with other technologies. The 4-bit Vedic multiplier has been designed using 32 nm technology within Tanner EDA software tools.

A New Approximate Sum of Absolute Differences Unit for Bioimages Processing

An inexact 6-transistor full adder (FA) cell is presented. It is low-power and gives full-swing outputs because of the applied gate diffusion input (GDI) along with the dynamic threshold (DT) techniques. The FA which has three errors is used in a 10-transistor inexact 4:2 compressor based on the stacking circuit idea. The implementation by a 16 nm carbon nanotube field-effect transistor (CNTFET) technology shows a small area of 0.027 lm2 and 0.045 lm2 for the FA and compressor, respectively. A new approximate sum of absolute differences (SAD) block is presented by the FA and compressor. The average power, power-delay-product (PDP), and peak signalto-noise ratio (PSNR) of the SAD are 6.80 mW, 33.86 nJ, and 42.98 dB, respectively, which confirm its efficiency for bioimages difference detection.

Comparison between Power Dissipation and Propagation Delay on 6T SRAM Cell Design Using GDI Logic with Transmission Gate VMSA and Voltage Divider

The rapid evolution of the semiconductor industry has witnessed shrinking portable and mobile devices alongside an increasing demand for extended battery life. Addressing the critical challenges of speed and battery life in digital devices, this paper investigated the effectiveness of innovative low-power design techniques. Focusing on the Gate Diffusion Input (GDI) approach, a recent advancement in the field, a comprehensive analysis revealed its significant potential for reducing power consumption in digital circuits. Additionally, a comparative analysis was conducted to evaluate the performance of conventional 6T GDI SRAM cells and their Modified 6T GDI SRAM with Voltage Divider, considering the influence of Sense Amplifiers. Simulation data demonstrated that Modified 6T SRAM designs, particularly the Voltage Divider and TGVMSA variants, achieved significantly lower power dissipation and delay despite having a larger cell area. Remarkably, the proposed design substantially improved power dissipation and propagation delay, achieving 1.3 ps, and 889.41mV at 1.8V shows that the suggested design enhances power dissipation and propagation delay. These findings suggest that the proposed design offers a promising strategy for enhancing power efficiency and performance in digital devices, thereby mitigating the limitations of battery life and speed in the modern technological landscape.

Design and analysis of low power high speed SBFF and MBFF for signal processing applications

Power dissipation accounts for high-performance digital systems in the deep sub-micron region. As a result, power within compact systems is vital. This paper investigates four distinct kinds of MBFF using conventional CMOS, PTL, TG, and GDI logic. In this work, a novel low-power high-speed master slave SBFF and MBFF are proposed. The recommended flip-flop design incorporates distinct latches for the master and slave components. The recommended flip-flop circuitry comprises master and slave circuits utilizing 7 PMOS and 11 NMOS transistors. The reduction in complexity is achieved by utilizing a smaller quantity of PMOS transistors. As a result, this design yields a flip-flop that is both high-speed and area-efficient. The proposed circuit under consideration functions with a singular clock. It comprises only four transistors that receive the clock signal as input—the proposed SBFF architecture comprises six inverters implemented using the Gate Diffusion Input (GDI) approach. The design of the existing and proposed SBFFs and MBFFs are simulated using 45 nm CMOS technology with Mentor Graphics EDA software. The study encompasses a wide range of process variables, including adjustments in supply voltage spanning from 0.8 V to 1.0 V and temperature changes that vary from −25 °C to 75 °C. The suggested design of the SBFF demonstrates a reduction in delay of at least 83 % and a decrease in PDP of 75 % compared to earlier reported designs. Furthermore, the proposed SBFF design accomplishes a comprehensive voltage swing by utilizing 18 transistors. The MBFF architecture under consideration demonstrates a reduction in delay of at least 79 % and a decrease in PDP of 65 % compared to earlier reported methods. Furthermore, the MBFF architecture that has been proposed successfully achieves a comprehensive voltage swing utilizing a mere 36 transistors.

Performance Analysis of Hybrid Comparator using 45nm Technology

In the present real-time world, due to the improvements and innovations of System on Chip (SoC) applications, there is a requirement to integrate multiple technology design topologies. The electronic system design is classified as analog, digital, and mixed-signal design. The comparator is the major building block used in the datapath of System on Chip (SoC) application device. The usage of these devices depends on not only functionality but also on the non-functionality parameters considering different performance estimation metrics. The nonfunctional performance metrics for a transistor level design depends on the number of transistors, switching activities of logic level voltages and delay between input and outputs. These performance metrics are improved by considering the multiple logic families for multiple output generations instead of using a single logic family topology. The comparator is the major component in the arithmetic circuits for SoC applications and can be realized by using various design topologies. The vividly used topologies are Conventional CMOS logic, Pass Transistor Logic (PTL), Gate Diffusion Input (GDI) Logic, Stacking technique, Quantum-dot cellular automata, etc. The selection of the design topology for the comparator is made based on the non-functional parameters. The performance of non-functional parameters is improved by combining the topology architectures of different design techniques. In this paper, the comparator is designed using conventional CMOS logic, PTL, GDI, and a hybridized topology for best performance and the same is implemented using 45nm technology. These circuits are designed by using Cadence Virtuoso Electronic Design Automation (EDA) design tools. Non-functional performance parameters are analyzed for different topologies. Index Terms: VLSI Design, Comparator, Datapath, EDA tools, CMOS Logic, GDI Logic, PTL Logic.

Design and Optimization of Reversible Arithmetic Unit Using Modified Gate Diffusion Input Logic

ABSTRACTIncreasing integration levels and demand for portability have made minimising the power consumption of circuits increasingly important for wide range of applications. Reversible logic is a low-power, low-loss design that can be utilised in low power CMOS, optical computing, nanotechnology, and quantum computing. Quantum machine learning Research is an area examines combining ideas from quantum computing and machine learning. In this paper, a new design of reversible logic-based arithmetic unit is demonstrated with CMOS and modified-GDI (MGDI) methodology for nanoscales using reversible gates. We provide a design for an optimized arithmetic unit, as well as some proposed methodologies for designing a reversible arithmetic unit with novel reversible gates, and compare them to existing circuits in terms of garbage output, constant input, number of reversible gates, and quantum cost, in this work. It can also be employed in Quantum computers due to its lower Quantum Cost and Garbage Output. Transistor-level implementations of the proposed arithmetic units are accomplished using Cadence Virtuoso tool GPDK 90 nm technology in combination with CMOS and MGDI techniques. Due to the optimization, the proposed arithmetic unit shows better performance in worst-case delay and power consumption than a comparable non-optimized Arithmetic Unit. According to the design and analysis of proposed Arithmetic Units. The proposed −1 design of the 4-bit Arithmetic Unit achieves optimisation by incorporating a reduced number of reversible gates and exhibiting a low quantum cost (12&40) using MGDI-FS. Similarly, the proposed −2 and 3 designs minimizes the number of transistors required, with a count of 80 and 120, and proposed −3 design, it eliminates the presence of constant inputs entirely using MGDI-FS.

Design and analysis of hybrid 10T adder for low power applications

Recently, a growing focus has been on the need for ultra-low-voltage (ULV) functioning to reduce energy usage. The full adder is a fundamental computational arithmetic unit in various image and signal processing applications. This study presents a novel architectural design for a 1-bit adder that utilizes 10 transistors. The concept relies on an energy-efficient hybrid logic multiplexer approach incorporating Gate Diffusion Input (GDI) logic. The primary goal of the suggested design for a hybrid full adder is to decrease power consumption while concurrently decreasing the required area. The suggested innovative architectural design for a full adder incorporates level restoration carry logic and ensures a complete swing output voltage. The designs have been analyzed in a standard environment using 45-nm CMOS process technology, with various supply voltages utilized. The evaluation of the adder cells focuses on speed, power consumption, power-delay-product (PDP), and space efficiency compared to the existing full adders. The recommended full adder cells were subjected to comprehensive simulation tests utilizing the Mentor Graphics environment. The results suggest that these cells surpass their counterparts, exhibiting a minimum of 80 % enhancements in their power-delay product (PDP) parameters. Also the comparisons have been made between the proposed full adders with and without level restoration techniques. The proposed level restoration technique based full adder yields better performance in terms of power and delay when compared to proposed full adder without level restoration.

Low Power Wallace Multiplier Using Gate Diffusion Input Based Full Adders

Now a days, in CMOS circuits leakage power is becoming more and more remarkable in power dissipation. Digital signal processing performs many functions including multiplication which is the prominent one. In the design of energy efficient processor multipliers play a key role in which it determines the DSP processor efficiency. A 4*4Wallace tree multiplier employs gate diffusion input technique to minimize leakage power. It is designed by adopting one bit full adder. In the proposed method, full addersare replaced by4*4 Wallace tree multiplier. Power dissipation majorly occurs in full adders. Hence, minimizing power dissipation in full adders will shrink dissipation of power in multipliers. Here, the proposed work diminishes the leakage power in comparison with the existing method. 

Simulation and Characterization of Carbon Nanotube-based 2:1 Multiplexer Electrical Properties

This paper reports on using simulation to characterize a Carbon Nanotube (CNT) based 2:1 multiplexer (MUX). This study aimed to evaluate the electrical properties, particularly the propagation delay, average power consumption, Power-Delay Product (PDP), and Energy-Delay Product (EDP). Different design approaches namely conventional CMOS, Pass Transistor Logic (PTL) approach, and Gate Diffusion Input (GDI) were adopted. The voltage supply (VDD) and diameter of the CNT are varied to see the effect on the electrical properties. The simulation was carried out using HSPICE. Through simulation, it is found that the GDI approach used the least number of transistors followed by PTL and CMOS. The calculation of the propagation delay exhibits a substantial improvement of more than 95% using the GDI approach. The average power consumption shows a 55.30% and 35.16% reduction when compared to CMOS and PTL respectively. The PDP demonstrates an improvement of more than 95% when compared with conventional CMOS and PTL approaches. The same trend of observation is also achieved for EDP. The variation of the VDD and chirality has a markable effect on the propagation delay and average power consumption. This is a preliminary attempt to evaluate the performance of CNT implementation in MUX. The outcome can become the guideline for engineers working in circuit design using emerging materials for future nanoelectronics applications.

High-efficient reversible full adder realized by dynamic threshold-based gate diffusion input logics

A new 12-transistor reversible full adder (FA) is designed based on carbon-nanotube-field effect transistors (CNTFETs) with 32 nm channel length and an area of 0.2204 μm2, 1 constant input (CI), and 3 garbage outputs (GO). The FA has 3 reversible logic gates in two of its stages that are realized by the gate diffusion input (GDI) technique. In the FA, 2 Toffoli gates with 1 CI and 1 new GDI-reversible-multiplexer are used to generate Sum and Cout, respectively. The multiplexer is 3*3, with two GOs, and a significant area reduction by only two transistors. The inputs of the circuit prevent the excessive increase of GOs and CIs. The Monte Carlo analysis using the HSPICE simulator indicates a better sensitivity of the FA versus fabrication with 6.45%, 1.86%, and 8.01% improvements of maximum values of power, delay, and power-delay-product (PDP). The FA is implemented in a 4-bit, 8-bit, 16-bit, and 32-bit ripple carry adder (RCA), and its superior results are seen. Under 32-bit RCA, the proposed circuit with 4956.30 fJ shows more energy savings compared to most competitors. The extracted results, the different figure of merits (FoMs), and reversibility features represent the proposed circuit as a desirable procedure for future works.