Gate Dielectric Stack Research Articles

Charge trapping gate stack enabled non-recessed normally off AlGaN/GaN HEMT with high threshold voltage stability

This paper reports a non-recessed normally off AlGaN/GaN high-electron-mobility transistor (HEMT) with a charge trapping gate dielectric stack. The charge trapping gate dielectric stack featuring a low density of fixed positive charges consists of an O3-based Al2O3 tunneling layer and an O3-based HfO2 blocking layer, both deposited via atomic layer deposition. For HEMT with a 15 nm AlGaN barrier layer, a threshold voltage of 2.57 V and an on-resistance of 8.50 Ω × mm are achieved. For positive bias temperature instability (PBTI) testing, the electric field provided by the 15 nm AlGaN layer serves as a barrier to channel carriers, significantly enhancing the PBTI test stability. The optimized gate dielectric stack enables the fabrication of the non-recessed normally off metal–insulator–semiconductor-HEMT with enhanced threshold voltage (Vth) stability.

Investigation on palladium gate electrode-based SOI junctionless FET for hydrogen gas sensing

This study provides a comprehensive investigation on palladium (Pd) gate electrode-based silicon on insulator (SOI) junctionless field-effect transistor (JLFET) for hydrogen gas (H2) sensing (Pd–SOI-JLFET). The device has a gate dielectric stack consisting of silicon dioxide (SiO2) and hafnium dioxide (HfO2). An extensive analysis was conducted to detect and identify the presence of hydrogen gas by examining several electrical characteristics such as drain current (IDS), transconductance (gm), output conductance (gd), energy band diagram (E), gate-to-source capacitance (CGS), and surface potential (Φs). Furthermore, a comprehensive investigation was conducted to examine the impact of the presence of H2 gas and variations in temperature on important parameters associated with the short channel effects (SCEs) including off-state current (IOFF), on-state current (ION), subthreshold swing (SS) and threshold voltage (Vth). In addition, the sensitivity analysis of the off-state current (IOFF) by considering process variation effect has been done. Sensitivity is also calculated at various temperatures for the detection of hydrogen gas molecule. At the temperature of 300K, the sensitivity values were obtained as 1.50083, 3.21754, 27.71483, 152.39617 and 2052.8 for pressure values 10−14 Torr, 10−13 Torr, 10−12 Torr, 10−11 Torr and 10−10 Torr, respectively. This analysis provides a thorough examination of the performance and efficacy of the Pd–SOI-JLFET hydrogen gas sensor highlighting its potential for a wide range of hydrogen sensing applications.

Improved performance of H-diamond MOSFETs with ZrO2/Al2O3 gate dielectric stacks deposited by electron beam method

H-diamond MOSFETs with ZrO2/Al2O3 gate dielectric stacks were fabricated using an electron beam (EB) evaporation technique. The fixed positive charge in the ZrO2 contact layer depleted the two-dimensional hole gas to achieve normally off operation. Thanks to the leakage suppression of Al2O3 blocking layer, the device exhibited a considerably low gate leakage current of 1.8 × 10−6 A/cm2 at VGS = −5 V. Contributed from the relatively lower estimated interfacial state density (1.45 × 1012 cm−2 eV−1) and uncontaminated ZrO2/Al2O3 gate interface, the maximum mobility was estimated to be 345.8 cm2/V·s at VGS of −2 V, indicating excellent interfacial property of ZrO2/H-diamond. The hole mobility remains an almost constant of about 150 cm2/V·s for −4 V ≤ VGS ≤ −7 V. The maximum drain current density with 6 μm-gate length was −112 mA/mm at VGS of −7 V. These results will provide an approach for fabricating high-performance H-diamond FETs.

(Invited) Sequential 3D Integration of Ge Transistors on Si CMOS

In order to keep the scaling progress going is to go 3D. This paper outlines some technology challenges and solutions to integrate Ge p-type MOSFETs sequentially on Si CMOS. Such a solution addresses the grand challenge to enable increased device density. However, the device itself does not have to scale but at the same time innovative solutions are suggested for low supply voltage operation enabling energy efficient integrated circuits (ICs) that will not be dominated by energy consumption in interconnects.By stacking the transistors on top of each other, and connect them with inter-tier via, the density of transistors per unit area increases. This approach demands that transistors are fabricated at a lower temperature compared to today’s Si CMOS technology. Therefore, we have focused on Ge based transistors, which has an inherently lower process temperature compared to Si transistors.In this paper several technological and design breakthroughs towards realizing Ge based sequential 3D circuits will be shown. We will present: A process to realize thin single crystalline Ge layers on planarized wafers with metal layers in lower tiers.A gate dielectric stack (Ge/Si/TmSiO/Tm2O3/HfO2/TiN) on Ge that enables adequately low defect densities at the dielectric/Ge interface allowing predictable and reliable Ge transistorsFully depleted Ge pFET devices fabricated at a low temperature compatible with sequential 3D. The devices exhibits 60% higher mobility compared to reference Si devices.3D digital circuits with pFETs on top of nFETs can enable area reduction by 30-50% depending on cell type.3D standard cells with lower parasitic capacitance (~30%) compared to 2D cells, enabling lower dynamic power consumption and more energy efficient integrated circuits.

(Invited) Leading-Edge Diamond FET, MEMS, and Photodetector Devices

Diamond is a candidate material for next-generation power electronics, micro-electro mechanical systems (MEMS), and solar-blind deep-ultraviolet (DUV) photodetector devices with excellent thermal stability and radiation hardness, which operate under extreme environment. In order to use an advantage of high-density hole channel of hydrogenated diamond (H-diamond) surface, we have developed the high-k stack gate dielectrics and AlN heterojuction gate for H-diamond FETs, such as HfO2/HfO2, LaAlO3/Al2O3 Ta2O5/Al2O3, and ZrO2/Al2O3, AlN/Al2O3 prepared by a combination of sputter-deposition (SD) and atomic layer deposition (ALD) techniques [1,2]. We also demonstrated the artificial diamond Fin-FETs with high-current level [3] and the nanolaminate insulator gate metal-oxide-gate FETs (MOSFETs) with k value as high as 100 [4], and the new transistor concept named by metal-insulator-metal-semiconductor field-effect transistor (MIMS-FET) to achieve normally-off operation by combining the advantages of MOSFET and metal-semiconductor FET [5]. In addition, we developed the routine ion-implantation process for preparing the diamond cantilever with a resonant frequency quality factor as high as one million [6,7]. We have also developed thermally stable Schottky barrier photodiode (SPD), metal-semiconductor-metal photodetector (MSMPD), and MSM-type SPD (IDF-SPD) with a large photoconductivity gain in DUV wavelength and a large discrimination ratio between DUV/visible light responsivity [8,9]. In this presentation, we will review the comprehensive our work on the diamond FET, MEMS, and photodetector devices. Acknowledgements: This work was in collaboration with J-W. Liu, M. Imura, M-Y. Liao, J. Alvarez in NIMS and A. Ouchiero and E. Obaldia in University of Taxes, Dallas, and partly supported by JSPS KAKENHI Grant Number 20H00313.

The Structural Performance of a Novel Double‐Stacked Heterogeneous Gate Heterojunction Tunneling Field‐Effect Transistor

In this work, an original Si/SiGe heterojunction tunneling field‐effect transistor which has a double‐stacked heterogeneous oxide gate (HfO2/Al2O3) structure (DSG–HJ–TFET) is designed and investigated by Sentaurus technology computer aided design (TCAD) simulation software. To ensure good interface quality, a stacked oxide gate dielectric of Al2O3 and HfO2 is proposed. The on‐state current (Ion) is increased though improving the carrier mobility degradation caused by the poor quality of interface between the high‐κ dielectric and semiconductor. Moreover, a heterojunction with SiGe (source)/Si (channel) and pocket layer which is inserted between the source region and the channel is adopted to reduce the tunneling barrier and improve the Ion. Therefore, the higher Ion is obtained by the proposed DSG–HJ–TFET. In the simulation results, it is shown that Ion of DSG–HJ–TFET is increased by three orders of magnitude compared with that of the conventional high‐κ gate dielectric TFET structure. In addition, the off‐state current (Ioff) of 4.91 × 10−11 μA μm−1, the minimum subthreshold swing of 14 mV dec−1, the Ion/Ioff ratio of 1.13 × 1012, transconductance of 260 μS μm−1, fT of 49.8 GHz, and gain bandwidth product (GBW) of 7.2 GHz are obtained. The propose DSG–HJ–TFET is favored in ultralow‐power applications for the rather good performance.

Physics-based analytical model for trap assisted biosensing in dual cavity negative capacitance junctionless accumulation mode FET

The design of a ferroelectric-based biosensor for detecting various biomolecules like proteins and DNA has captivated the interest of researchers in early disease diagnostics and treatment monitoring. Doomed by this interest, an analytical model for trap-assisted biosensing in Dual Cavity Negative Capacitance Junctionless Accumulation Mode FET is proposed for detecting various biomolecules. The biomolecules are treated as traps that tunnel through the biosensor's ferroelectric layer. The analytical model is validated through extensive numerical device simulations. The device incorporates the detection of charged and uncharged biomolecules in terms of dielectric constants and biomolecule concentration. The nano-cavities are created inside the gate dielectric stack to collect biomolecules like proteins and DNA. As the biomolecules are infused as traps in cavity areas, electrical properties of the biosensor, like input characteristics, transconductance, threshold voltage, on-state current, and subthreshold swing change. The sensitivity obtained for the proposed biosensor is compared with the existing biosensor and found that it is best suited for susceptible biosensing applications.

Performance evaluation of split high–K material based stacked hetero-dielectrics tunnel FET

This research investigates the performance evaluation of a double gate TFET (DGTFET) by employing a hetero-dielectric gate structure featuring distinct high-K dielectrics with different work functions in a dual-material gate configuration. The gate dielectric stack is comprised of split high–K materials placed on the SiO2 dielectric. An outline of the analytical model for the validation of the novel device is developed and 2D simulations-based analysis and investigation are carried out. The impact of different high-K dielectric materials layered on top of silicon dioxide (SiO2) is examined; its effect on transfer characteristics, subthreshold swing (SS), minimum tunneling width, ratio of ON to OFF currents ION/IOFF, and energy band bending are investigated. The work functions optimization for the auxiliary and tunnel gates are made in this work to minimize OFF current, to reduce ambipolar phenomena and to enhance tunnel rate. The effects of gate potentials, source/ drain doping concentrations on the results are further studied. The threshold voltage of DGTFET is also modelled and computed for the proposed structures. The present findings revealed that the low OFF current (10−17 A μm−1) is provided by the proposed device structure, improved ratio of ION/IOFF (1011), and lowered subthreshold swing required for future era.

Bilayer HfO2/Sb2O3 gate dielectric stacks for transistors with 2D semiconducting channels

Bilayer HfO2/Sb2O3 gate dielectric stacks for transistors with 2D semiconducting channels

Determination of Type and Concentration of Traps in Nanoscale-Thick HfO2 Films Applicable for Gate Dielectric Stacks

Determination of Type and Concentration of Traps in Nanoscale-Thick HfO₂ Films Applicable for Gate Dielectric Stacks

A simple figure of merit to identify the first layer to degrade and fail in dual layer SiOx/HfO2 gate dielectric stacks

Understanding the degradation dynamics and the breakdown sequence of a bilayer high-k (HK) gate dielectric stack is crucial for the improvement of device reliability. We present a new Figure of Merit (FoM), the IL/HK Degradation Index, that depends on fundamental materials properties (the dielectric breakdown strength and the dielectric constant) and can be used to easily and quickly identify the first layer to degrade and fail in a bilayer SiO2/HK dielectric stack. Its dependence on IL and HK material parameters is investigated and its validity is demonstrated by means of accurate physics-based simulations of the degradation process. The proposed FoM can be easily used to understand the degradation dynamics of the gate dielectric stack, providing critical insights for device reliability improvement.

Saturation Thickness of Stacked SiO2 in Atomic-layer-deposited Al2O3 Gate on 4H-SiC

Abstract High-k materials as an alternative dielectric layer for SiC power devices have the potential to reduce interfacial state defects and improve MOS channel conduction capability. Besides, under identical conditions of gate oxide thickness and gate voltage, the high-k dielectric enables a greater charge accumulation in the channel region, resulting in a larger number of free electrons available for conduction. However, the lower energy band gap of high-k materials leads to significant leakage currents at the interface with SiC, which greatly affects device reliability. By inserting a layer of SiO2 between the high-k material and SiC, the interfacial barrier can be effectively widened and hence the leakage current will be reduced. In this study, the optimal thickness of the intercalated SiO2 was determined by investigating and analyzing the gate dielectric breakdown voltage and interfacial defects of a dielectric stack composed by atomic-layer-deposited Al2O3 layer and thermally nitride SiO2. Current-voltage and high-frequency capacitance-voltage measurements were performed on metal-oxide-semiconductor test structures with 35 nm thick Al2O3 stacked on 1-, 2-, 3-, 6-, or 9 nm thick nitride SiO2. Measurement results indicate that the current conducted through the oxides was affected by the thickness of the nitride oxide and the applied electric field. Finally, a saturation thickness of stacked SiO2 that contributed to dielectric breakdown and interfacial band offsets was identified. The findings in this paper provides guideline for the SiC gate dielectric stack design with the breakdown strength and the interfacial state defects considered.

White X-Ray Radiation Effects in MOS Capacitors With Atomic Layer Deposited HfO2/Al2O3 and Al2O3/HfO2/Al2O3 Gate Dielectric Stacks for High Total Doses

White x-ray radiation effects in metal-oxide- semiconductor (MOS) capacitors with HfO2/Al2O3 (H/A) two-layer and Al2O3/HfO2/Al2O3 (A/H/A) three-layer gate dielectric stacks are investigated at high total dose levels of approximately 10, 50, and 100 Mrad(Si), based on capacitance-voltage (C-V) and current-voltage (I-V) measurements before and after irradiations, and the annealing behaviors at ambient temperature of the irradiated MOS capacitors are also observed over a long time. The H/A and A/H/A stacks are grown by atomic layer deposition (ALD), and have the same physical and equivalent oxide thicknesses. The C-V results indicate that the H/A and A/H/A-stack capacitors have almost an identical radiation response up to 50 Mrad(Si), and hole trapping is the main damage mechanism for the stacks. An anomalous C-V rebound for the A/H/A-stack capacitor after 100 Mrad(Si) is attributed to the existence of the potential well in the A/H/A stack, considering the continuously increased C-V shift for the H/A-stack capacitor with doses. In addition, radiation-induced interface traps lead to a significant C-V stretch-out even after 10 Mrad(Si), and multi-photon absorption is proposed for the production of the interface traps due to white x-ray irradiation at a high dose rate. Meanwhile, the I-V results show that the leakage current of the tested capacitors is increased after irradiation, and the A/H/A-stack capacitor has a much smaller leakage current than the A/H-stack capacitor, both before and after irradiation, because of its stack structure advantage in suppressing the leakage current. The primary mechanism for the leakage current is analyzed using the Frenkel-Poole model.

High Ion/Ioff ratio 4H-SiC MISFETs with stable operation at 500 °C using SiO2/SiNx/Al2O3 gate stacks

In this work, 4H-SiC lateral metal-insulator-semiconductor field-effect transistors (MISFETs) were demonstrated to operate up to 500 °C with a high on/off current ratio (over 109). A low off-state current of 3.6 × 10−9 mA/mm at 500 °C was obtained in SiC MISFET with a ring structure. The MISFETs with SiO2/SiNx/Al2O3 gate dielectric stack showed minimum subthreshold swings of 155 and 240 mV/dec at room temperature and 500 °C, respectively, indicating good thermal stability of this gate dielectric stack on SiC. An interface trap density of 1.3 × 1011 cm−2 eV−1 at E − EV = 0.2 eV was extracted from the Capacitance–Voltage (CV) measurements at room temperature, which confirms excellent dielectric interface. The electron mobility increases with increasing temperature and reaches 39.4 cm2/V s at 500 °C. These results indicate that SiC MISFETs with triple layer dielectrics and ring structure have a high potential in extreme-temperature electronics.

Improvement of electrical properties of ZnO TFT with NbLaO-based stacked gate dielectrics

The double-stacked gate dielectrics (DSGD), which consisted of either NbLaO/Al2O3 or NbLaO/SiO2, were used to improve the electrical performance of zinc oxide thin-film transistor (ZnO-TFT) with single-layer NbLaO gate dielectric (SLGD). Compared to ZnO-TFT with SLGD, the ZnO-TFTs with DSGD exhibit better electrical performance, specifically for the device with the NbLaO/SiO2 DSGD, with an increase of the field-effect mobility from 5.77 cm2V[Formula: see text]s[Formula: see text] to 39.64 cm2V[Formula: see text]s[Formula: see text], an enhancement of the on/off current ratio by two orders of magnitude, a reduction of the subthreshold slope from 110 mV/decade to 70 mV/decade. The performance enhancements are attributed to a low root-mean-square surface roughness of less than 0.3 nm and a low trap-state density of less than [Formula: see text] cm[Formula: see text] (even [Formula: see text] cm[Formula: see text] for the NbLaO/SiO2 DSGD) in the bulk of the channel and at the ZnO/NbLaO interface. The results imply that ZnO-TFTs with DSGD have the potential for the application of high-resolution flat panel display.

Influence of polarization Coulomb field scattering on the electrical properties of normally-off recessed gate AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistor with ALD-Al2O3 gate dielectric stack

In this study, normally-off recessed gate AlGaN/GaN MIS-HEMT with ALD-Al2O3 gate dielectric stack was fabricated. The influence of polarization Coulomb field (PCF) scattering on electrical properties of normally-off recessed gate AlGaN/GaN MIS-HEMTs with ALD-Al2O3 gate dielectric stack was studied. Based on the measured I-V data, the electrical parameters such as additional polarization charge (ΔρG), electron mobility (μ), gate-source (G-S) parasitic resistance (RS) and gate-drain (G-D) parasitic resistance (RD) were obtained by iterative calculation method. Through systematic analyzed of these results, it was found that the positive G-S voltage (VGS) induces tensile strain in the ultra-thin AlGaN barrier layer, which was AlGaN remaining after etching and existsed between the gate dielectric and the GaN channel, resulting in positive ΔρG under the gate. With the increase of VGS, the inverse piezoelectric effect in the ultra-thin AlGaN layer increases and the amount of ΔρG increases. At the same time, the positive VGS induces two-dimensional electron gas (2DEG) underneath the gate, which is also positively correlated with the VGS. Compared withΔρG, the 2DEG density (n2DEG) has a greater effect on the PCF scattering strength. We also found that the influence of PCF scattering on RS and RD is different, which is related to the difference between G-S distance and G-D distance. This study provides a new theoretical basis for normally-off recessed gate AlGaN/GaN MIS-HEMTs to improving μ and reducing parasitic resistance.

Synaptic array using multi-level AND flash memory cells for hardware-based neural networks

We propose an AND array architecture in which bit-lines (BLs) and source-lines (SLs) of thin film transistor (TFT)-type flash memory cells used as synapses are arranged in parallel, and show the fabricated device and array characteristics. A top gate dielectric stack and a bottom gate dielectric stack serve to store a synaptic weight and select excitatory or inhibitory synapses, respectively. Multi-level (>5-bit) synaptic weight states and selective write operations in the AND array architecture are achieved by utilizing a simple update pulse scheme. Furthermore, weighted sum operation in a fabricated 9 × 3 AND flash synaptic array is successfully carried out by measuring BL currents when input pulses are applied to multiple word-lines (WLs) for hardware-based neural networks (HNNs).

Wafer‐Scale PLD‐Grown High‐κ GCZO Dielectrics for 2D Electronics (Adv. Electron. Mater. 12/2022)

High-κ Gate Dielectrics In article number 2200580, Jing Yu, Wei Han, Francis Chi-Chung Ling, and co-workers prepare large-size (Ga, Cu) co-doped ZnO films with super-high dielectric constant (κ > 50) and good homogeneity by a pulsed laser deposition (PLD) method. The performance of SnS2 field-effect transistor reveals that high-κ Al2O3/GCZO gate dielectric stack is suitable for 2D electronic devices. The success in fabrication of GCZO films not only show higher κ than other conventional dielectrics in terms of compatibility to CMOS processes, but also keep their comparative advantages in the fabrication of high-performance electronic devices over conventional dielectrics.

Interface Engineering for Steep Slope Cryogenic MOSFETs

In this work, we study experimentally the impact of different gate dielectric stacks on the subthreshold behavior of cryogenic MOSFETs. While in room temperature devices, silicon nitride deteriorates the off-state of MOSFETs it turns out that at cryogenic temperatures an appropriately thin, grown silicon nitride layer in combination with a high-k gate dielectric counteracts the saturation of the inverse subthreshold slope and inflection phenomena. As a result, steep slope cryogenic MOSFETs with strongly improved subthreshold behavior are demonstrated.

Estimation of hole mobility in hydrogen-terminated diamond MOSFET with high-k stacked gate dielectrics

In order to control the accumulated two-dimensional hole gas (2DHG) of high density in hydrogen-terminated diamond (H-diamond) metal oxide–semiconductor field effect transistors (MOSFETs), the high-k stacked gate dielectric is extensively explored. However, the stacked gate dielectric introduces additional remote Coulomb scattering (RCS) and remote interface roughness scattering (RIRS) to 2DHG, which result from the fixed charges in the stacked gate dielectric and the rough interface between stacked gate dielectrics. Therefore, we model the RCS and RIRS in H-diamond MOSFETs with high-k stacked gate dielectrics for the first time and investigate their dependences on structural and physical parameters of the devices. Our research may provide some instructions on the understanding of the carrier transport properties in H-diamond MOSFETs.