Gate Dielectric Capacitance Research Articles

Reaction/annealing pathways for forming ultrathin silicon nitride films for composite oxide–nitride gate dielectrics with nitrided crystalline silicon–dielectric interfaces for application in advanced complementary metal–oxide–semiconductor devices

Aggressive scaling of complementary metal–oxide–semiconductor (CMOS) devices requires gate dielectrics with an oxide equivalent thickness, tox,eq∼1 nm or less by the product introduction year 2012. Direct tunneling presents a significant performance limitation in field-effect transistors (FETs) with homogeneous oxide gate dielectrics <1.7 nm. Boron diffusion from p+ poly-Si gate electrodes in p-channel FETs leads to additional electrical problems for oxide thicknesses <3 nm. Interfacial nitridation improves reliability in n-channel FETs; however, by itself, it is not effective in p-type metal–oxide–semiconductor FETs due to boron pileup at the Si–dielectric interface. Proposed solutions include top-oxide surface nitridation and the integration of composite oxide–nitride dielectrics into CMOS devices. This review discusses the integration of hydrogenated silicon nitride films, prepared by remote plasma-enhanced chemical-vapor deposition, into electrical devices with composite oxide–nitride (ON) gate dielectrics. FET devices with ON dielectrics having the same oxide-equivalent thickness, tox-eq and gate dielectric capacitance as devices with homogeneous oxide gate dielectrics display improved performance and reliability. However, reductions in direct tunneling current due to increased physical thickness are below expectations based on tunneling calculations which assume the tunneling mass of electrons in nitride films is approximately the same as in SiO2. The combination of a lower electron tunneling mass and a reduced conduction-band offset energy (i) places important limitations on the extent to which devices with ON gate dielectrics can meet the aggressive scaling needed in advanced CMOS devices, and (ii) raises important questions that have to be addressed when evaluating alternative high-K dielectrics such as Ta2O5, TiO2, and Al2O3. However, tunneling can be reduced by combining monolayer interface nitridation with ON stacks.

Bonding constraint-induced defect formation at Si-dielectric interfaces and internal interfaces in dual-layer gate dielectrics

As aggressive scaling of integrated circuits continues into the next century, insulators with dielectric constants higher than SiO2 with different local bonding arrangements will be required to increase gate dielectric capacitance in field effect transistor devices. An important issue in semiconductor device physics is determining whether differences between the bonding at (i) Si–SiO2 interfaces and (ii) interfaces between crystalline Si and alternative gate dielectric materials will result in increased densities of electrically active defects at the alternative dielectric interfaces, thereby limiting targeted levels of performance and reliability. In particular, it is important to understand from a chemical bonding perspective why Si–SiO2 interfaces display both low defect densities and high reliability, while other interfaces such as Si–Si3N4 with similar bonding chemistry, display defect densities that are at least two orders of magnitude higher. Building on previously established criteria for formation of low defect density glasses and thin films, constraint theory is extended to crystalline Si-dielectric interfaces that go beyond Si–SiO2 through development of a model that is based on the average bonding coordination at these interfaces. This approach identifies quantitative bonding criteria that distinguish between device-quality and highly defective interfaces. This extension of constraint theory is validated by its application to interfaces between Si and stacked silicon oxide/nitride dielectrics which demonstrates that as in bulk glasses and thin films an average coordination, Nav>3 yields increasingly defective interfaces. Finally, the universality of this application of constraint theory is demonstrated by showing that defect densities scale with overcoordination in the same way in thin films and at interfaces.

A novel method to characterize MOS transistors with mixed gate dielectric technologies

The authors have developed an extraction technique suitable for studying mixed dielectric systems in MOS transistors. The method gives accurate modeling parameters for low-field mobility and surface roughness scattering, and it removes the dependence of gate dielectric capacitance on the results. The technique has been implemented in interpretive BASIC written on a desk-top HP9000 computer, and the program is easily adapted to other automated data acquisition systems since advanced numerical methods are not necessary. A set of I/sub DS/-V/sub GS/ measurements taken at different bulk biases is required, along with the value of effective gate capacitance. The usefulness of this extraction method is demonstrated by application to ONO and pure oxide gate dielectric transistors of differing compositions and thicknesses. The utility of this method lies in the ease of implementation, and the ability to remove the gate dielectric capacitance in extracting accurate modeling parameters. >

Analysis of the channel inversion layer capacitance in the very thin-gate IGFET

As the gate insulator thickness approaches the channel thickness, the gate capacitance is speculated to be smaller than its gate insulator capacitance. The gate capacitance of the thin-gate IGFET is calculated using Maxwell-Boltzmann and Fermi-Dirac statistics and is experimentally measured. The results show that the gate capacitance approaches the gate insulator capacitance regardless of the gate thickness within the practical range ( T_{ox} > 50 A). To explain why the channel thickness is not reflected in the measured gate capacitance, the channel inversion layer capacitance is analyzed numerically. Based on that, its effects on the gate capacitance are discussed quantitatively and an equivalent circuit is proposed.

Surface state related [formula omitted] noise in MOS transistors

The theory of surface state effects on 1 ƒ noise in p− n junctions is extended to explain low-frequency excess noise in MOS transistors. Experimental results are critically compared to theory. The results show that low-frequency excess noise in MOS transistors is due to the fluctuation of charge density in the conduction channel caused by the surface potential fluctuation. The fluctuation of the surface potential is introduced by the random charge occupancy of surface states. The low-frequency excess noise in MOS transistors is found to be proportional to the surface state density and the square of the transconductance of the device, and inversely proportional to the gate area and the square of the unit area gate-insulator capacitance. It is also shown that the surface state density when the surface is strongly inverted can be obtained from noise measurements. Finally it is shown that by proper heat treatment it is possible to reduce the low-frequency excess noise of MOS transistors.