Gate Bias Research Articles

Ferroelectric‐Switchable Single Photodetector Implementing Complex Optoelectronic Logics

AbstractOptoelectronic logic gates (OELGs) are promising building blocks of edge extraction, image recognition, and data encryption in logic circuits. However, implementing complex OELGs based on CMOS devices needs additional circuit configuration due to the fixed photodetection mode, which inevitably makes the manufacturing process of chip complicated and large. This work proposes a ferroelectric‐switchable photodetector (FeS‐PD) in 2D α‐In2Se3/WSe2 heterojunction, which can implement the complex OELG functions. The FeS‐PD exhibits the ferroelectric‐tunability between the photovoltaic and photoconductive mode via the sign and amplitude of polarization voltage, as well as accompanied by a high current photo/dark ratio. Moreover, the non‐volatile‐tunability of photovoltaic voltage (opening circuit voltage) distinctively enables the bias one input of logics, which enables a single device to implement the complex XOR and AND logic functions via programming gate pulse voltage, light input, and bias. Compared to the traditional CMOS‐based logic gate, FeS‐PD significantly reduces the transistor number by 91.7% and 50% for nonlinear XOR and linear AND logics, respectively. The research provides a simple platform for on‐chip optoelectronic‐logic computing circuits.

Hetero dielectric based dual material gate AlGaN channel MISHEMT for enhanced electrical characteristics

Herein, we report an AlGaN channel metal insulator semiconductor high electron mobility transistor (MISHEMT) in dual material gate (DMG) architecture with two different dielectrics as gate insulator for enhancing the DC performance of the device. The use of a high-k dielectric material as gate insulator below gate metal 1 and a low-k dielectric below gate metal 2 results in significant threshold voltage variation along the channel. This contributes to improved average carrier velocity which in turn results in better current drive. The proposed device exhibits a peak current of 162 mA/mm at zero gate bias, whereas, the DMG and single material gate (SMG) AlGaN channel HEMTs offer currents of 137 mA/mm and 125 mA/mm respectively. The peak transconductances are about 24.66 mS/mm, 23.68 mS/mm and 22.71 mS/mm respectively for the proposed device, DMG and SMG HEMTs. The proposed device reduces the OFF current by an order of 106 compared to that of DMG HEMT.

Impact of 6.5-kV SiC MOSFET Gate Bias on Reverse Recovery Over a Wide Temperature Range

Impact of 6.5-kV SiC MOSFET Gate Bias on Reverse Recovery Over a Wide Temperature Range

Impact of negative gate stress on the reliability of p-GaN gate HEMT devices under dynamic switching operation

Abstract In this study, we investigated the impact of single stress (negative gate bias stress) and combined stress (both negative gate bias stress and drain voltage stress) on the instability of the threshold voltage (VTH) on p-GaN gate HEMT devices during dynamic switching operation. The dynamic VTH shift during pulsed negative gate bias stress was investigated for the first time. The VTH exhibits an initial rapid increase upon the initiation of stress and a slight decrease with increasing stress time. For the applied stresses of VGS = -1/-2/-3 V, the VTH shift values were, respectively, 0.12/0.16/0.19 V at the stress time of 100 s. Under the stress of VGS = -3 V and VDS = 100 V, the shift value of VTH was 0.61 V. After the combined stress, the saturation and off-state leakage currents exhibited a significant reduction, with the latter decreasing by one order of magnitude after the reverse voltage stress. When only a negative gate bias stress is applied, the degradation of the device can recover quickly after the stress is removed. In contrast, the positive shift in VTH caused by the drain-voltage stress is difficult to recover. Furthermore, the mechanisms underlying the VTH shift mentioned above were explored. Under single-stress conditions, the shift in VTH is associated with shallow traps that trap electrons. Meanwhile, under the combined stress, the degradation of Vth was also affected by the deep-level traps.

Gate Oxide Reliability in Silicon Carbide Planar and Trench Metal-Oxide-Semiconductor Field-Effect Transistors Under Positive and Negative Electric Field Stress

This work investigates the gate oxide reliability of commercial 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The performance of threshold voltage (Vth) and gate leakage current (Igss) in SiC MOSFETs is evaluated under positive and negative gate voltage stress. The oxide lifetimes of SiC planar and trench MOSFETs at 150 °C are measured using constant voltage Time-Dependent Dielectric Breakdown (TDDB) testing. From the test results, it is found that electron trapping and hole trapping in SiO2 caused by oxide electric field (Eox) stress affect the Vth of SiC MOSFETs. The saturation and turnaround behavior of the Vth shift during positive and negative gate voltage stresses indicates that the influence of charge trapping in the gate oxide varies with stress time. The Igss under positive and negative gate voltages depends on the tunneling barrier height for electrons and holes, respectively, which can be calculated using the Fowler–Nordheim (FN) tunneling mechanism. Moreover, the presence of near-interface traps (NITs) affects the barrier height for holes under negative gate voltages. The behavior of Vth shift and Igss under high-temperature gate bias reflects the charge trapping occurring in different regions of the gate oxide. In addition, compared to SiC planar MOSFETs, SiC trench MOSFETs with thicker gate oxide tend to exhibit higher lifetimes in TDDB tests.

Automatic Obstacle Avoidance Trolley System Based on Two-Dimensional ReS2/WSe2 Heterojunction Photodetector.

With the continuous advancement of intelligent vehicle technology, automatic obstacle avoidance (AOA) has become a crucial component of in-vehicle systems. This study introduces an AOA trolley system based on ReS2/WSe2 heterojunction photodetectors. The device with type-II band alignment exhibits an impressive on/off current ratio of 7.14 × 104, along with a rapid impulse response time of 32.3/24.4 μs, a detectivity of 2.0 × 1013 Jones, and an anisotropic ratio of 4.2 under 532 nm illumination. Additionally, the device is electrically tunable under an appropriate gate bias. These characteristics are ascribed to the engineering of the heterojunction interface between ReS2 and WSe2. Furthermore, this device was successfully integrated into an AOA system for autonomous vehicles. The system utilizes the high sensitivity and fast response features of two-dimensional materials, allowing it to effectively identify and avoid obstacles in real time, thereby enhancing driving safety.

Al modification layer method for enhancing InAlZnO transistors

In this work, a surface engineering method is proposed to boost electrical performance and stability of the InAlZnO (IAZO) transistors, of which an Al modification layer is deposited on surface of the IAZO channel layer. Through analysed by transmission electron microscope and X-ray photoelectron spectroscopy, the IAZO thin film with Al modification layer undergoes a reduction reaction to generate more oxygen vacancies. Hall effects measurement further demonstrates that IAZO thin films with Al modification layer exhibit higher carrier concentrations than the ones without Al modification layer. The IAZO transistors with Al modification layer exhibit better performance and stability, including a field-effect mobility of 4.36 cm2 V−1s−1 (an improvement of about three-fold), a small subthreshold swing of 105.23 mV/decade, a high on-to-off current ratio greater than 107, and a threshold voltage shift of less than 0.50 V under positive and negative gate bias stress. Moreover, the IAZO transistors with Al modification layer demonstrate high thermal stability under 400 °C for 120 min in air atmosphere. Based on this method, the IAZO inverters have been implemented with high voltage gain of 87.55 V/V. This surface engineering technology paves the way for application of high-performance oxide transistors for advanced monolithic three-dimensional integration.

Impact of post-deposition annealing on SiO2/SiC interfaces formed by plasma nitridation of the SiC surface and SiO2 deposition

Abstract We examined the impact of post-deposition annealing (PDA) on SiO2/SiC structures formed by plasma nitridation of the SiC surface followed by sputter deposition of SiO2. The interface state density near the conduction band edge of SiC was reduced from about 2 × 1012 to 1 × 1011 eV−1 cm−2 as the CO2-PDA temperature increased from 1050 °C to 1250 °C. In addition, the sample treated by CO2-PDA exhibited substantially higher immunity against positive gate bias stress than the standard NO nitridation. Our findings indicate that defect passivation by CO2-PDA plays a crucial role in improving the performance and reliability of SiC MOS devices formed by sputter-SiO2 deposition.

Study on the influence mechanism of gate oxide degradation on DM EMI signals in SiC MOSFET

This paper investigates gate oxide degradation and its influence on Differential Mode(DM) EMI signals. The study reveals that changes in the parasitic capacitance within the chip, resulting from gate oxide degradation, can modify the amplitude-frequency characteristics of DM EMI signals, leading to unexpected transmission outcomes. This paper subjects SiC MOSFET modules to periodic high-temperature gate bias stress, extracts the spectrum characteristics of DM EMI, and assesses the impact of junction temperature. The analysis explores the impact of gate oxide degradation on low and high frequency DM EMI signals. Experimental results reveal distinct sensitivities of amplitude-frequency characteristics in the DM EMI signals to temperature variations and responses to gate oxide degradation at various frequency bands. The extrapolation of the correlation between the frequency-domain characteristics of the DM EMI signals and the degree of gate oxide degradation introduces a novel approach to evaluate the lifespan of power electronic devices.

Engineered interface charges and traps in GaN metal-oxide-semiconductor field-effect transistors providing high channel mobility and E-mode operation

Abstract This review focuses on controlling interface charges and traps to obtain minimal channel resistance and stable enhancement-mode operation in GaN metal-oxide-semiconductor field-effect transistors. Interface traps reduce the free electron density and act as Coulomb scattering centers, thus reducing the channel mobility. Oxide traps cause instability of threshold voltage (V th) by trapping electrons or holes under gate bias. In addition, the V th is affected by the overall distribution of interface charges. The first key is a design of a bilayer structure to simultaneously obtain good insulating properties and interface properties. The other key is the optimization of post-deposition annealing to minimize oxide traps and interface fixed charges. Consequently, the gate structure of an AlSiO/AlN/p-type GaN has been designed. Reductions in V th as a result of polarization charges can be eliminated by using an m-plane trench channel, resulting in a channel mobility of 150 cm2V–1s–1 and V th of 1.3 V.

Optoelectronic Reconfigurable Logic Gates Based on Two-Dimensional Vertical Field-Effect Transistors.

Optoelectronic reconfigurable logic gates are promising candidates to meet the multifunctional and energy-efficient requirements of integrated circuits. However, complex device architectures need more power and hinder multifunctional device applications. Here, we design vertical field-effect transistors (VFET) based on the two-dimensional (2D) graphene/MoS2/WSe2/graphene van der Waals heterojunction forming ohmic and Schottky contact. The modulation of the Schottky barrier via gate bias enables the device to switch between positive and negative photocurrents, which can effectively achieve optoelectronic reconfigurable logic gates (XNOR, NOR, NAND, AND, OR, and Inhibit) in a single device. Particularly, the transistor number is reduced by 75% for ("XNOR", "NOR", "NAND") and 83% for ("AND", "OR") gates compared to traditional logic circuits. This work provides a promising route for using a single device to realize optoelectronic reconfigurable logic gates, which can advance the development of high-speed, high-throughput, and intricate data processing in future optical computing applications.

Ultrathin α-Bi2O3 Thin-Film Transistor for Cost-Effective Oxide-TFT Inverters.

Electronics is advancing toward greater diversity and sustainability by prioritizing energy efficiency and cost-effectiveness. Metal oxide thin-film transistor (TFT) represents a technology at the forefront of advancing next-generation sustainable electronics, and exploring oxide channel compositions is a crucial step in opening opportunities for developing next-generation device applications. This study presents the first development of n-channel α-Bi2O3-TFTs using a 4 nm ultrathin channel prepared by a cost-effective vacuum-free and solvent-free liquid metal printing method in ambient air. Even the pristine device exhibited a clear TFT action but required a large negative gate bias to turn off due mainly to excess carriers from oxygen vacancy in the α-Bi2O3 channel. Oxygen-containing post-annealing reduced both channel carrier and subgap defect densities, enabling the development of depletion and enhancement-type α-Bi2O3-TFTs with the saturation mobility of 2-4 cm2 V-1 s-1. Two types of oxide-TFT-based inverter circuits, zero-VGS-NMOS and CMOS inverters, were fabricated by using α-Bi2O3-TFTs, operating in a high voltage gain of over 130. This work demonstrates the potential of oxide semiconductor materials toward the development of next-generation sustainable electronics.

Physical Reservoir Computing Using Tellurium-Based Gate-Tunable Artificial Photonic Synapses.

We report tellurium (Te) thin-film-based artificial photonic synapses and their application to physical reservoir computing (PRC). The Te-based artificial photonic synapses were fabricated by using sputtered Te thin films and spray-coated MXene (Ti3C2) electrodes. A thorough investigation of the field-dependent persistent photoconductivity (PPC) of the Te channel revealed that the relaxation speed of the transient photocurrent depended on the gate bias. Utilizing the PPC property, the Te device served as an excellent photonic synapse under light pulse stimulus, exhibiting multiple synaptic characteristics such as excitatory postsynaptic current and paired-pulse facilitation, as well as highly linear potentiation-depression characteristics; a simulation-based study further confirmed the effectiveness of the device. Most importantly, by exploiting the nonlinear and fading memory characteristics of the Te photonic synapse, we demonstrate two advanced examples of PRC. In classifying handwritten digits, our system carried out successful digit recognition without binarization or another simplification process with reduced computational cost compared to conventional systems. To solve second-order nonlinear equations, we introduce the strategy of utilizing historical nodes. The combination of historical nodes and the gate-tunable responses of the photonic synapses, which provide an enriched reservoir state, yielded excellent prediction accuracy. Overall, this work will offer an understanding of Te-based optoelectronic devices and their synergetic integration with neuromorphic devices and PRC.

Impact of bias stress and endurance switching on electrical characteristics of polycrystalline ZnO-TFTs with Al2O3 gate dielectric

Abstract This study experimentally investigates electrical characteristics and degradation phenomena in polycrystalline zinc oxide thin-film transistors (ZnO-TFTs). ZnO-TFTs with Al2O3 gate dielectric, Al-doped ZnO (AZO) source–drain contacts, and AZO gate electrode are fabricated using remote plasma-enhanced atomic layer deposition at a maximum process temperature of 190 °C. We employ positive bias stress (PBS), negative bias stress (NBS), and endurance cycling measurements to evaluate the ZnO-TFT performance and examine carrier dynamics at the channel-dielectric interface and at grain boundaries in the polycrystalline channel. DC transfer measurements yield a threshold voltage of −5.95 V, a field-effect mobility of 53.5 cm2/(V∙s), a subthreshold swing of 136 mV dec−1, and an on-/off-current ratio above 109. PBS and NBS measurements, analysed using stretched-exponential fitting, reveal the dynamics of carrier trapping and de-trapping between the channel layer and the gate insulator. Carrier de-trapping time is 88 s under NBS at −15 V, compared to 1856 s trapping time under PBS at +15 V. Endurance tests across 109 cycles assess switching characteristics and temporal changes in ZnO-TFTs, focusing on threshold voltage and field-effect mobility. The threshold voltage shift observed during endurance cycling is similar to that of NBS due to the contrast in carrier trapping/de-trapping time. A measured mobility hysteresis of 19% between the forward and reverse measurement directions suggests grain boundary effects mediated by the applied gate bias. These findings underscore the electrical resilience of polycrystalline ZnO-TFTs and the aptitude for 3D heterogeneous integration applications.

Electrical Control of Valley Polarized Charged Exciton Species in Monolayer WS2.

Excitons are key to the optoelectronic applications of van der Waals semiconductors, with the potential for versatile on-demand tuning of properties. Yet, their electrical manipulation remains challenging due to inherent charge neutrality and the additional loss channels induced by electrical doping. We demonstrate the dynamic electrical control of valley polarization in charged excitonic states of monolayer tungsten disulfide, achieving up to a 6-fold increase in the degree of circular polarization under off-resonant excitation. In contrast to the weak direct tuning of excitons typically observed using electrical gating, the charged exciton photoluminescence remains stable, even with increased scattering from electron doping. By exciting at the exciton resonances, we observed the reproducible nonmonotonic switching of the charged state population as the electron doping is varied under gate bias, indicating a resonant interplay between neutral and charged exciton states.

Numerical Simulation on the Impact of Back Gate Voltage in Thin Body and Thin Buried Oxide of Silicon on Insulator (SOI) MOSFETs

Silicon-on-Insulator (SOI) technology provides a solution for controlling Short-Channel Effects (SCEs) and enhancing the performance of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). However, scaling down SOI MOSFETs to a nanometer scale does not necessarily yield further scaling benefits. Introducing multiple gates, such as a double gate configuration, can effectively mitigate SCEs. Nonetheless, fabricating a flawless double gate structure is an exceedingly challenging endeavor that remains unrealized. The adoption of a back gate bias, with an asymmetrical thickness arrangement between the front and back gates, mimicking the behavior of a double gate, offers an alternative approach. This approach has the potential to modify the electrical characteristics of the device, thus potentially leading to improved control over SCEs. In this study, we employed 2D simulations using Atlas to investigate the influence of back gate biases, namely, -2.0 V, 0 V, and 2.0 V on a 10 nm silicon thickness at the top and a 20 nm buried oxide thickness for n-channel MOSFETs. We focused on key parameters, including threshold voltage (VTh), Drain Induced Barrier Lowering (DIBL), and Subthreshold Swing (SS). The results demonstrate that a negative back gate bias is the most favorable configuration, as it yields superior performance. This translates into more effectively controlled SCEs across all the parameters of interest.

Ultra-Low Power Consumption Artificial Photoelectric Synapses Based on Lewis Acid Doped WSe2 for Neuromorphic Computing.

Capitalizing on the extensive spectral capacity and minimal crosstalk properties inherent in optical signals, photoelectric synapses are poised to assume a pivotal stance in the realm of neuromorphic computation. Herein, a photoelectric synapse based on Lewis acid-doped semiconducting tungsten diselenide (WSe2) is introduced, exhibiting tunable short-term and long-term plasticity. The device consumes a mere 0.1 fJ per synaptic operation, which is lower than the energy required by a single synaptic event observed in the human brain. Furthermore, these devices demonstrate high-pass filtering capabilities, highlighting their potential in image-sharpening applications. In particular, by synergistically modulating the photoconductivity and electrical gate bias, versatile logic capabilities are demonstrated within a single device, enabling it to flexibly perform both Boolean AND and OR gate operations. This work demonstrates a viable approach for Lewis acid-treated TMDs to realize multifunctional photoelectric synapses for neuromorphic computing.

Threshold voltage instability of SiC MOSFETs under very‐high temperature and wide gate bias

AbstractThreshold voltage (VTH) instability affects the reliability of silicon carbide (SiC) MOSFETs. In this article, the influence of gate bias (VGS) and high temperature on VTH instability is investigated under wide VGS and very‐high temperature range (150°C to 275°C). The degradation mechanism of gate oxide under coupling of different electrical and thermal stress is revealed. When the device is subjected to +VGS, the relationship between VTH shift and temperature is not monotonic and there is a temperature turning point. This is mainly related to the capture/release and generation of electron traps. However, the VTH shift increases sharply and gate oxide breakdown for the device bias at +35 V, which is related to Fowler–Nordheim (F–N) tunnelling effect. For a large −VGS, the VTH shift is very small. Moreover, when the negative VGS decreases, the VTH shift is positively correlated with temperature, which may result from the activation and charge exchange of hole traps. However, the influence of moving ions changes the temperature dependence of VTH shift for the device bias at −30 V. Finally, the devices of different manufacturers are studied and similar change patterns are found. This finding provides guidance for the further application of SiC MOSFETs under high temperatures and different voltages.

Dual-gate AlGaN channel HEMTs: advancements in E-mode performance with N-shaped graded composite barriers

Abstract This work evaluates the performance of dual gate AlGaN channel HEMTs on SiC substrate. The study analyzes two HEMT structures that differ only in barrier design, one design consists of fixed composite barriers (FCB-HEMT) i.e. there is fixed Aluminum composition x = 0.48 in the first Al x Ga1−x N barrier and x = 0.42 in the second Al x Ga1−xN barrier while the other design comprises N-shaped graded composite barriers (NGCB-HEMT) i.e. the Aluminum content varies gradually from 0.4 to 0.48 in the first AlGaN barrier and from 0.34 to 0.42 in the second AlGaN barrier. The paper concentrates on energy band diagrams, electron concentration profile, electric field distribution, drain and transfer characteristics, and the effects of high temperature on drain characteristics and mobility of the NGCB-HEMT. It has been reported that at zero gate bias, the FCB-HEMT has a drain current density of 0.137 A mm−1 while it decreases to 0.0058 A mm−1 in the case of NGCB-HEMT, thus presenting a novel approach towards enhancement-mode AlGaN HEMTs. Hence, grading can be optimized in the composite barriers to achieve enhancement mode operation of AlGaN channel HEMTs. Furthermore, the study reveals that the critical electric field of FCB-HEMT is 6.9975 M V cm−1, while that of NGCB-HEMT is 5.3124 M V cm−1, demonstrating their usefulness in electronic devices that operate at high voltages and harsh temperatures. Moreover, at higher temperatures, the phenomenon of optical phonon scattering leads to decreased mobilities, which in turn causes low drain currents relative to the drain voltage.

Ammonia gas sensors based on multi-wall carbon nanofiber field effect transistors by using gate modulation

Ammonia gas sensors play a critical role in environmental monitoring and healthcare applications due to the harmful effects of ammonia exposure. In this study, I present a novel approach to ammonia detection using field-effect transistors (FETs) based on Multi-Wall Carbon Nanofibers (MWCNFs), known for their outstanding electrical properties. I fabricate and characterize MWCNF-FET sensors, utilizing interdigitated Source-Drain electrodes directly deposited onto aligned semiconducting MWCNFs. By systematically investigating the effect of gate bias on sensor performance, I demonstrate that applying a positive gate voltage enhances the sensor's gas response by up to 55 % across varying concentrations of ammonia. Additionally, I show that appropriate gate modulation significantly improves the device's reversibility, ensuring reliable, repeatable measurements. These findings highlight the potential of MWCNF-FETs in developing high-performance, gate-tunable ammonia gas sensors for real-world applications.