Gate Bias Polarity Research Articles

Charge Buildup and Leakage Current in Gold/Parylene-C/ Pentacene Capacitor under Constant-Voltage Stress

Degradation of metal-insulator-semiconductor (MIS) capacitors of gold/Parylene-C/Pentacene under constant voltage stress (CVS) was investigated to explore the electrical stability and reliability of Parylene C as a gate dielectric in flexible electronics. A stress voltage of fixed magnitude as high as 20 V, both negative and positive in polarity, was applied to each MIS capacitor at room temperature for a fixed duration as long as 10 s. The CVS effects on the capacitance-voltage curve-shift, the time-dependent leakage current and the time-dependent dielectric breakdown were measured and analyzed. CVS is observed to induce charge in Parylene-C and its interfaces with gold and Pentacene. The net induced charge is positive and negative for, respectively, negative and positive gate bias polarity during CVS. The magnitude of the charge accumulated following positive gate CVS is significantly higher than that following negative gate bias CVS in the range of 4 to 25 nC cm−2. In contrast, the leakage current during the negative gate stress is three orders of magnitude higher than that during the positive gate stress for the same bias stress magnitude. The charge buildup and leakage current are due to the trapping of electrons and holes near the Parylene-C/Pentacene interface as well as in the Parylene-C layer.Before the application of the CVS, a dielectric breakdown occurs at an electric field of 1.62 MV cm−1. After the application of the CVS, the breakdown voltage decreases and the density of the trapped charges increases as the stress voltage increases in magnitude, with the polarity of the trapped charges opposite to that of the stress voltage. The magnitude and direction of the capacitance-voltage curve-shift depend on the trapping and recombination of electrons and holes in the Parylene-C layer and in the proximity of the Parylene-C/Pentacene interface during CVS.

Deep-ultraviolet sensing characteristics of transparent and flexible IGZO thin film transistors

Recently, deep-ultraviolet (DUV) photodetectors with useful functions including transparency and flexibility have been developed for a real-time environmental monitoring, a wearable monitoring system, transparent wireless communication, and a smart window system. In this study, we investigate the DUV sensing characteristics of transparent and flexible IGZO thin-film transistors (TFTs) fabricated by a dry transfer printing, which is a very promising technique affording the device fabrication on unconventional surfaces. The fabricated TFT devices show high mechanical stability even at a bending radius of 1.4 mm, and the repeatable and gate bias-dependent DUV photoresponse characteristics. The gate bias-dependent photocurrent (Iph) decay characteristics are likely attributed to the different surface re-adsorption rates of oxygen molecules depending on the gate bias polarity, which are qualitatively described based on energy band diagrams. In addition, the wavelength-dependent photoresponse characteristics of the IGZO TFT device upon UV illumination with λ = 245 nm show a 10 times faster Iph decay behavior than that upon UV illumination with λ = 365 nm. The result implies that the dissociative oxygen arising from the DUV illumination could accelerate the Iph decay due to the increased surface adsorption.

Gate field controlled and temperature dependent quantum transport in (10,0) carbon nanotube field effect transistor

The cylindrically gated (10,0) carbon nanotube field effect transistor having n-i-n device structure has been simulated by using the non-equilibrium Green function method and self-consistent calculations. The gate bias polarity and device temperature have been found to significantly influence the drain current obtained from energy-position resolved current spectrum under ballistic transport limit through simulations. The effect of temperature on drain current is seen to be more pronounced in thermionic emission as compared to band-to-band tunnelling.

Photoresponse of an oxide semiconductor photosensor

The authors investigated the photoresponse of a double-layer oxide semiconductor (GaInZnO–InZnO) thin-film transistor (TFT) under illumination, where the photocurrent in the negative gate bias region increased significantly without a negative shift in the threshold voltage. In particular, in the forward gate bias sweep direction (from −VG to +VG), the hysteresis of the transfer curves of the photosensor TFT became pronounced when the negative gate bias and its duration were increased. Additionally, the photocurrent level of the TFT remained almost the same as the level measured using a DC reverse gate bias sweep mode (from +VG to −VG). An analysis of the transfer curves, capacitance–voltage curves, and energy band diagrams indicates that the hysteresis characteristics can be explained by the competing effects of electrical-stress-induced defect generation and the screening of the negative gate bias by doubly positively charged oxygen vacancies depending on the gate bias polarity. In particular, the origin of the photoresponse of the photosensor TFT under illumination was studied intensively by qualitative analysis.

Fabrication and Characterization of Solution Processed Top-Gate-Type Organic Light-Emitting Transistor

Tris(8-hydroxyquinolinato) aluminium (Alq3 based top-gate-type organic light emitting-transistors (OLETs) have been fabricated by using a simple solution process. The OLET consists of a bulk layer of indium-tin oxide (ITO) and hole injection layer of poly(2,3-dihydrothieno-1,4-dioxin)– poly(styrenesulfonate) (PEDOT:PSS) as an anode (source), organic electroluminescent layer of Alq3 and aluminium (Al) as cathode (drain) and gate. A Current–voltage–luminance (J–V–L) characteristic of the OLETs shows that the current density is depended on polarity of gate bias. Initial internal electric field contributes to the charge diffusion between gate and cathode channel. A vice versa characteristic observed for luminance at cathode–anode and gate–anode channels.

Passivation effect on gate-bias stress instability of carbon nanotube thin film transistors

A prior requirement of any developed transistor for practical use is the stability test. Random network carbon nanotube-thin film transistor (CNT-TFT) was fabricated on SiO2/Si. Gate bias stress stability was investigated with various passivation layers of HfO2 and Al2O3. Compared to the threshold voltage shift without passivation layer, the measured values in the presence of passivation layers were reduced independent of gate bias polarity except HfO2 under positive gate bias stress (PGBS). Al2O3 capping layer was found to be the best passivation layer to prevent ambient gas adsorption, while gas adsorption on HfO2 layer was unavoidable, inducing surface charges to increase threshold voltage shift in particular for PGBS. This high performance in the gate bias stress test of CNT-TFT even superior to that of amorphous silicon opens potential applications to active TFT industry for soft electronics.

Relaxation dynamics of ionic liquid—VO2 interfaces and influence in electric double-layer transistors

Oxide semiconductor systems are often electrostatically doped with ionic liquids as gate insulators towards modulating carrier density and inducing phase transitions, while simultaneously serving as a means to probe their electronic phase diagram. The electronic and electrochemical properties of ionic liquid/correlated oxide interfaces are, therefore, important in interpreting such field-effect phenomena. Here, we use DEME-TFSI and VO2 as a model system to investigate the interface properties, slow relaxations, as well as field-effect in electric double layer transistor geometry. The stability of these interfaces is probed by combination of current-voltage measurements, x-ray photoelectron spectroscopy, impedance spectroscopy, and constant current charging. Three-terminal field effect transistor-type devices fabricated by photolithography are used to investigate kinetics of channel resistance modulations under varying gate bias polarity. Bias regions for reversible modulation of channel conductance have been determined. A time-dependent transconductance effect and as large as 20× increase in conductance are observed.

Effect of post oxidation annealing on electrical characteristics of Ni/SiO2/4H-SiC capacitor with varying oxide thickness

This paper describes an experimental observation of post oxidation annealing (POA) treatment on current-voltage and capacitance-voltage characteristics of Ni/SiO2/4H-SiC system with varying oxide thickness. The leakage current of fabricated structures shows an asymmetric behavior having noticeable effect of POA with the polarity of gate bias (+V or −V at the anode). When compared with the conventional wet oxidation, the POA processes greatly reduce interface-state density and enhance reliability of devices. An extensive increment in the barrier height at SiO2/4H-SiC interface was observed due to POA, which resulted into lower forward leakage current. A significant improvement in the oxide charges are also demonstrated using C-V characteristics of POA treated structures.

Gate bias polarity dependent H migration and O vacancy generation through Si=O–H complex formation in SiO2/Si(100)

We studied H-atom migration in SiO${}_{2}$/Si systems triggering O vacancy generation based on first-principles calculations. The migrating H atoms in SiO${}_{2}$ have been found to be mostly negatively charged irrespective of the charge-state polarity in the systems because strong charge transfer from the Si to the O atoms substantially increases the O 2$p$ energy levels. Although the SiO${}_{2}$ systems with no defect are not degraded by the migrating H atoms, 2Si$=$O--H complex formation in the SiO${}_{2}$/Si systems has been found to generate an O vacancy via H${}_{2}$O molecule desorption after alternate electron transfer between the 2Si$=$O--H complex and the Si substrate, leading to the final electrical breakdown of SiO${}_{2}$ films. The migration of negatively charged H atoms and their degradation agree well with the recently observed gate bias polarity dependent SiO${}_{2}$ film degradation.

Conductance modulation in graphene nanoribbon under transverse asymmetric electric potential

This paper presents a theoretical study of the effect of transverse electric potentials on the transport properties of armchair graphene nanoribbons (AGNRs), formed by pairs of asymmetric gates placed along the side of the ribbon. Single-pair and dual-pair configurations are considered. The effect of hollows (spatial regions void of carbon atoms) in the AGNR channels is also examined. The use of hollowed AGNRs in the dual-pair configuration allows for significant modulation of the transport gap when the two pairs have opposite gate bias polarity. Furthermore, for the dual-gate system, hollowed AGNR channels exhibit the optimal ratio of on-state to off-state conductance, due to the smaller off-state conductance compared with spatially homogenous AGNR channels. Our results indicate that transverse gate technology coupled with careful engineering of hollow geometry may lead to possible applications in graphene-based electronic devices.

Experimental analysis of I‐V and C‐V characteristics of Ni/SiO2/4H‐SiC system with varying oxide thickness

PurposeThe purpose of this paper is to electrically examine the quality of thin thermally grown SiO2 with thickness variation, on Si‐face of 4H‐SiC <0001> (having 50 μm epitaxial layer) by current‐voltage (I‐V) and capacitance‐voltage (C‐V) methods.Design/methodology/approachMetal‐oxide‐silicon carbide (MOSiC) structures with varying oxide thickness have been fabricated on device grade 4H‐SiC substrate. Ni has been used for gate metal on thermally oxidized Si‐face and a composite layer of Ti‐Au has been used for Ohmic contact on the highly doped C‐face of the substrate. Each structure was diced and bonded on a TO‐8 header with a suitable wire bonding for further testing using in‐house developed LabVIEW‐based computer aided measurement setup.FindingsThe leakage current of fabricated structures shows an asymmetric behavior with the polarity of gate bias ( + V or −V at the anode). A strong relation of oxide thickness and temperature on effective barrier height at SiO2/4H‐SiC interface as well as on oxide charges have been established and reported in this paper.Originality/valueThe paper focuses on the development of 4H‐SiC based device technology in the fabrication of MOSiC‐based integrated structures.

Gate Bias Instability under Light Irradiation in Polycrystalline Silicon Thin-Film Transistors

We have investigated the charge trapping phenomena that occur in gate insulator biased under back-light irradiation of a liquid-crystal display. Two types of gate insulators (SiO2 and SiNx/SiO2) were evaluated. In both cases, it was found that electron trapping in the insulators is caused by light irradiation under gate bias stress and that the locations of the electron trapping in gate insulator vary according to the kind of insulator and the polarity of gate bias. As for the dependence of degradation on stress time and luminance, the phenomena can be explained by an approximate equation derived from first-order rate equation. Furthermore, it was found that the analysis of the light-induced degradation is valid for evaluation of insulator quality. We confirmed that gate insulators formed in different deposition conditions have different light-induced degradation rates.

Organic Thin-Film Transistor Memory with Nanocrystal Carbon Dots

Organic thin-film transistor (OTFT) memory devices were fabricated with nanocrystal carbon (nc-C) dots incorporated into the pentacene/oxide interface in the active layer. The nc-C dots were arranged precisely in order on the OTFT channel region by a focused ion beam (FIB) technique using low-energy Ga + ions and phenanthrene as the carbon source. The structural information of nc-C dot arrays was obtained by scanning ion microscopy (SIM) and atomic force microscopy (AFM). These images indicate that the nc-C dot array was successfully formed on the oxide layer. The density of the two-dimensional nc-C dots was 1.3-1.5A—108 cm-2. The current-voltage (I-V ) characteristics showed that the OTFTs exhibit memory behavior upon the application of forward and reverse gate bias stresses. Depending on the polarity of gate bias, write and erase modes were induced, and a maximum threshold voltage shift I”Vth of 0.97 V was obtained. © The Surface Science Society of Japan.

Transparent indium gallium zinc oxide transistor based floating gate memory with platinum nanoparticles in the gate dielectric

A transparent memory device has been developed based on an indium gallium zinc oxide thin film transistor by incorporating platinum nanoparticles in the gate dielectric stack as the charge storage medium. The transfer characteristics of the device show a large clockwise hysteresis due to electron trapping and are attributed to the platinum nanoparticles. Effect of the gate bias stress (program voltage) magnitude, duration, and polarity on the memory window characteristics has been studied. Charge retention measurements were carried out and a loss of less than 25% of the trapped elec-trons was observed over 104 s indicating promising application as nonvolatile memory.

Stress-Induced Positive Charge in Hf-Based Gate Dielectrics: Impact on Device Performance and a Framework for the Defect

A Hf-based dielectric has been selected to replace SiON for CMOS technologies. When compared with SiON, Hf dielectrics can suffer from higher instability. Previous attentions were focused on electron trapping, and positive charging received less attention. The objective of this paper is to study the impact of positive charging on device performance and to provide a framework for the defect. Three components of threshold voltage instability Delta Vth are unambiguously identified for pMOSFETs, i.e., loop, loop-shift, and up-loop. The loop dominates Delta Vth at a relatively short time (< 1 s). After stressing for a longer time, the whole loop is shifted in the negative direction. Unlike the loop, the up-loop cannot readily be recharged after recovery. In addition to the generated interface states, three different types of positive charges are formed in the Hf-based stacks, i.e., cyclic positive charges (CPC), antineutralization positive charges (ANPC), and as-grown hole trapping (AHT). Each type of defect has its unique signatures and properties. CPC can repeatedly be charged and discharged by alternating the gate bias polarity. ANPC is more difficult to neutralize, whereas AHT is harder to charge. Both the generated interface states and the AHT saturate at longer stress time, but ANPC does not. ANPC reduces at higher measurement temperature, but CPC is insensitive to temperature. The relation between each type of defect and each component of Delta Vth is clarified.

A novel channel-program–erase technique with substrate transient hot carrier injection for SONOS NAND flash application

A novel channel-program and erase method is presented to replace the FN tunneling operation for SONOS cells in NAND architecture for the first time [Hsu TH, Wu JY, King YC, Lue HT, Shih YH, Lai EK, et al. A novel channel-program–erase technique with substrate transient hot carrier injection for SONOS memory application. In: Tech digest 2006 European solid-state device research conference (ESSDERC); 2006. p. 222–5], [1]. The proposed operation utilizes substrate transient hot electron (STHE) injection and substrate transient hot-hole (STHH) injection for programming and erasing, respectively. Gate bias polarity serves to control whether hot electrons or hot holes are injected into the nitride storage layer. More efficient program and erase operations are achieved compared to the conventional Fowler–Nordheim (FN) tunneling method. The new technique operates at lower programming voltages and with shorter duration pulses, thus increases the programming throughput. Moreover, good program/erase disturb immunity, cycling endurance and data retention are demonstrated.

Impact of Polarity of Gate Bias and Hf Concentration on Breakdown of HfSiON/ $\hbox{SiO}_{2}$ Gate Dielectrics

We have investigated the impact of polarity of gate bias and Hf concentration on HfSiON/SiO2 gate dielectric breakdown (DB) with time-zero DB (TZDB) and time-dependent DB (TDDB). At TZDB, the gate leakage currents at breakdown (BD) under negative bias are much smaller than those with positive bias without regard to accumulation or inversion states. Since the electric fields at BD are not all the same, the BD mechanism cannot be explained with a simple thermochemical model for all types of stress for HfSiON gate dielectric. With TDDB, the electric-field acceleration constant is dependent on the Hf concentration. Calculated active dipole moments in HfSiON have been shown to be similar to theoretical values for nMOS but not pMOS. Thermochemic BD of HfSiON, itself (not interface SiO2), is adequate to describe nMOS in the inversion state. On the other hand, the BD of pMOS in the inversion state is affected by the carrier currents and not the electric fields as the TZDB. The BD mechanisms are strongly dependent on both the polarity of the gate bias and the Hf concentration.

Impact of floating gate dry etching on erase characteristics in NOR flash memory

We report the effects of plasma process-induced damage during floating gate (FG) dry-etching process on the erase characteristics of NOR flash cells. As compared to flash cells processed in a stable plasma condition, it is found that flash cells processed in the nonoptimized ambient show significantly degraded erase characteristics under a negative gate Fowler-Nordheim (FN) bias, exhibiting a fast-erasing bit in the distribution of erased bits. However, little differences are found in their tunneling characteristics under a positive gate biasing. The gate bias polarity dependence of FN tunneling indicates that positive charges are created near the poly-Si/SiO/sub 2/ interface during the FG dry-etching, prior to the backend processes such as metal- or via-etch.

Hysteresis caused by defects in buffer layer of metal-ferroelectric-insulator-semiconductor (MFIS) devices

We have investigated the roles of buffer layer in the Pt/SBT-Y2O3/p-Si (MFIS) capacitors. We found that the insertion of Y2O3 buffer layer prevents the charge injection from the Si substrate to ferroelectric layer. However, negative charges with the effective density of 3.21×1012/cm2 were generated due to the additional process step for Y2O3 deposition. We suggested that the asymmetrical increase of a memory window is due to the domain pinning caused by negative charges in buffer layer. In addition, we reported that the mobile positive charges in ferroelectric layer can induce the shift of the hysteresis loops depending on the gate-bias polarity and a ramp rate during the capacitance-voltage (C-V) measurement. Since Y2O3 buffer layer minimize the charge injection, the shift of the hysteresis loops was asymmetrical.

Stress-induced leakage current in p/sup +/ poly MOS capacitors with poly-Si and poly-Si/sub 0.7/Ge/sub 0.3/ gate material

The gate bias polarity dependence of stress-induced leakage current (SILC) of PMOS capacitors with a p/sup +/ polycrystalline silicon (poly-Si) and polycrystalline Silicon-Germanium (poly-Si/sub 0.7/Ge/sub 0.3/) gate on 5.6-nm thick gate oxides has been investigated. It is shown that the SILC characteristics are highly asymmetric with gate bias polarity. This asymmetric behavior is explained by the occurrence of a different injection mechanism for negative bias, compared to positive bias where Fowler-Nordheim (FN) tunneling is the main conduction mechanism. For gate injection, a larger oxide field is required to obtain the same tunneling current, which leads to reduced SILC at low fields. Moreover, at negative gate bias, the higher valence band position of poly-SiGe compared to poly-Si reduces the barrier height for tunneling to traps and hence leads to increased SILC. At positive gate bias, reduced SILC is observed for poly-SiGe gates compared to poly-Si gates. This is most likely due to a lower concentration of Boron in the dielectric in the case of poly-SiGe compared to poly-Si. This makes Boron-doped poly-SiGe a very interesting gate material for nonvolatile memory devices.