Gate Array VLSI Research Articles

Tolerance of holographic polymer-dispersed liquid crystal memory for gamma-ray irradiation.

The radiation-hardened characteristics of holographic polymer-dispersed liquid crystal (HPDLC) memory are discussed in the application for an optically reconfigurable gate array. The radiation experiments are conducted using a cobalt 60 gamma radiation source to examine the tolerance of a 100Mrad total ionizing dose for the HPDLC memory. The optical properties are compared in the conditions before and after gamma-ray irradiation for the fabricated HPDLC gratings. The effects of gamma-ray irradiation on the internal grating structure are also investigated by polarization optical microscopy and scanning electron microscopy observations. The HPDLC memory irradiated by a 100Mrad total ionizing dose demonstrates the implementation of the optical reconfiguration in a gate-array VLSI.

Effects of multi-context information recorded at different regions in holographic polymer-dispersed liquid crystal on optical reconfiguration

A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by constructing a laser illumination system to implement successive laser exposures at different small regions in a glass cell filled with LC composites. The context pattern arrangements for circuit information are designed in a 3 × 3 in.2 photomask by electron beam lithography, and they are recorded as laser interference patterns at nine regions separated in an HPDLC sample by a laser interferometer composed of movable pinhole and photomask plates placed on motorized stages. The multi-context information reconstructed from the different regions in the HPDLC is written to a photodiode array in a gate-array VLSI by switching only the position of laser irradiation using the displacement of the pinhole plate under the control of a personal computer (PC). The effects of multi-context information recorded at different regions in the HPDLC on optical reconfiguration are discussed in terms of the optical system composed of ORGA VLSI and HPDLC memory. The internal structures in the HPDLC memory formed by multi-context recording are investigated by scanning electron microscopy (SEM) observation, and the configurations composed of LC and polymer phases are revealed at various regions in the HPDLC memory.

Formation of holographic polymer-dispersed liquid crystal memory by angle-multiplexing recording for optically reconfigurable gate arrays.

Formation of holographic polymer-dispersed liquid crystal (HPDLC) memory for an optically reconfigurable gate array is discussed for angle-multiplexing recording by controlling the laser interference exposure in LC composites. The successive laser illumination system to record the various configuration contexts at the specified region and angle in HPDLC memory is constructed by using the combination of a half-mirror and a photomask placed on the motorized stages under the control of a personal computer. The effect of laser exposure energy on the formation of holographic memory is investigated by measuring diffraction intensity as a function of exposure energy during the grating formation process and observing the internal grating structure by scanning electron microscopy. The optical reconfiguration in the gate-array VLSI is executed for configuration contexts of OR and NOR operations shown as logical operators that are reconstructed by laser irradiation at different incident angles for a specified region in the HPDLC memory.

0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI

Currently, demand for high-speed dynamic reconfiguration of a programmable device is increasing for the purpose of increasing the performance of such devices. To support the high speed dynamic reconfiguration, optially reconfigurable gate arrays (ORGAs) have been developed up to now. An ORGA consists of a holographic memory, a laser array, and an optially reconfigurable gate array VLSI. The holographic memory can store many configuration contexts. In addition, its large bandwidth optical connection enables high speed reconfiguration. However, photodiode sensitivities of conventional ORGAs were not good. This paper therefore presents a newly fabriated 0.18πm CMOS process optially reconfigurable gate array VLSI chip with highly sensitive photociruits.

Fast Optical Reconfiguration of a Nine-Context DORGA Using a Speed Adjustment Control

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous reconfiguration contexts. However, fast reconfiguration and numerous reconfiguration contexts share a trade-off relation on current VLSIs. Therefore, Optically Reconfigurable Gate Arrays (ORGAs) have been developed to resolve this dilemma. An ORGA architecture allows many configuration contexts by exploiting the large storage capacity of a holographic memory and fast reconfiguration using wide-bandwidth optical connections between a holographic memory and a programmable gate array VLSI. In addition, Dynamic Optically Reconfigurable Gate Arrays (DORGAs) using a photodiode memory architecture have already been developed to realize a high-gate-density VLSI. Therefore, this article presents the first demonstration of a nanosecond-order configuration of a nine-context DORGA architecture. Moreover, this article presents a proposal of a reconfiguration period adjustment technique to control each reconfiguration period to its best setting.

Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability

We present a proposal of a partial reconfiguration architecture for optically reconfigurable gate arrays and present an 11,424 gate dynamic optically reconfigurable gate array VLSI chip that was fabricated on a 96.04 mm(2) chip using an 0.35 μm three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2.21 μs partial reconfiguration.

Superimposing acceleration and optimization method of optical reconfiguration speed without any increase of laser power

This paper proposes a method of superimposing acceleration and optimizing the optical reconfiguration speed while requiring no increase of laser power. Using this technique, the optical reconfiguration speed is increased by superimposing multiple configuration contexts. Simultaneously, optimization of the number of configuration contexts and reconfiguration speed is possible. A full four-context optically reconfigurable gate array system consisting of an optically reconfigurable gate array VLSI, an easily rewritable liquid crystal holographic memory, and four vertical-cavity surface-emitting lasers was constructed to demonstrate this method. This paper clarifies the method's benefits using experimental results obtained from the demonstration system.

Programmable optically reconfigurable gate array architecture and its writer

Recently, optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser array, have been developed to achieve huge virtual gate counts that vastly surpass those of currently available VLSIs. By exploiting the large storage capacity of a holographic memory, VLSIs with more than 1 teragate counts will be producible. However, compared with current field programmable gate arrays, conventional ORGAs have one important shortcoming: they cannot be reprogrammed after fabrication. To reprogram ORGAs, a holographic memory must be disassembled from its ORGA package, then reprogrammed outside of the ORGA package using a holographic memory writer. It must then be implemented onto the ORGA package with high precision techniques beyond that which can be provided by manual assembly. Therefore, to improve this shortcoming, this paper proposes what is believed to be the world's first programmable ORGA architecture with no disassembly. Finally, the availability of this architecture is discussed based on the experimental results.

A Dynamic Optically Reconfigurable Gate Array—Perfect Emulation

This paper presents a perfect dynamic optically reconfigurable gate array (DORGA) architecture emulation using a holographic memory and a conventional ORGA-VLSI. In ORGAs, although a large virtual gate count can be realized by exploiting the large-capacity storage capability of a holographic memory, the actual gate count, which is the gate count of a programmable gate array VLSI, is important to increase the instantaneous performance. Nevertheless, in previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context consumed a large implementation area of the ORGA-VLSIs and prevented the realization of large-gate-count ORGA-VLSIs. Therefore, a DORGA architecture has been proposed in order to increase the gate density. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, demonstration of a perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. Therefore, in this study, the DORGA architecture was perfectly emulated, and the performance, particularly the reconfiguration context retention time, was measured experimentally. The advantages of this architecture are discussed in relation to the results.

A 10K-Gate CMOS Gate Array Based on a Gate Isolation Structure

This paper describes an effect of the "gate isolation" technique and its application to a 10K-gate CMOS gate-array VLSI chip. This gate array is fabricated using a 2-/spl mu/m n-well CMOS technology, with double-level metallization. As an example, a 32-bit parallel array multiplier is designed using a fully automatic CAD system. The density of CMOS gate arrays using gate isolation is estimated to be 1.10 to 1.26 times greater than that of the arrays using several types of oxide isolation, when implementing circuits with complexities on the order of 10K gates.

A 10K-gate CMOS gate array based on a gate isolation structure

This paper describes an effect of the technique and its application to a 10K-gate CMOS gate-array VLSI chip. This gate array is fabricated using a 2-µm n-well CMOS technology, with double-level metallization. As an example, a 32-bit parallel array multiplier is designed using a fully automatic CAD System. The density of CMOS gate arrays using gate isolation is estimated to be 1.10 to 1.26 times greater than that of the arrays using several types of oxide isolation, when implementing circuits with complexities on the order of 10K gates.