Gate Array Chip Research Articles

An efficient Radix-4 butterfly structure based on the complex binary number system and distributed arithmetic

Complex number arithmetic is pivotal in various applications, requiring the selection of an efficient multiplier for high-performance computations. Fast Fourier transform (FFT)-based multipliers are widely employed for computing complex number products, but their reliance on using dedicated multipliers and treating the real and imaginary parts as two entities significantly add to the cost and complexity of the system. Distributed arithmetic (DA) is a technique that replaces complex multiplications with a bit-level shift and addition mechanism. The complex binary number system (CBNS) utilizes binary arithmetic, which treats the real and imaginary parts as a single entity, which can simplify complex number arithmetic and computations. This paper introduces an approach integrating the CBNS with DA in a Radix-4 decimation in time FFT 8-bit and 16-bit butterfly structure. The proposed design significantly reduces arithmetic computations and eliminates dedicated multipliers, demonstrating a reduction in power consumption, area size, and lookup tables, as well as increasing overall clock performance compared to the conventional FFT architecture on Artix-7, Kintex-7, and Virtex-7 field-programmable gate array chips.

Field-Programmable Gate Array-Based True Random Number Generator Using Capacitive Oscillators

In this paper, novel architecture of the true random number generator (TRNG) is presented. The proposed TRNG uses jitter in capacitive oscillators as a source of entropy. These capacitive oscillators exploit the input/output (I/O) buffers of a field-programmable gate array (FPGA) chip. A specific connection between these buffers allows cyclical charging and discharging of a parasitic capacitance associated with an external FPGA pin. If a few pins of an FPGA chip are not connected to any external components, they can be targeted to build the TRNG. The proposed TRNG requires only three external FPGA pins dedicated to capacitive oscillators, as well as 18 look-up tables (LUTs) and 20 flip-flops (FFs). Its throughput amounts to 11–13 Mbit/s. To pass all NIST SP800-22 statistical tests for a wide range of operating temperatures, the TRNG requires a post-processing circuit. The characteristic feature of the proposed TRNG is that it internally generates a signal indicating that a random bit was just produced. Therefore, no external clock signal is needed to sample the output.

A digital neuromorphic system for working memory based on spiking neuron-astrocyte network

Among various types of memory, working memory (WM) plays a crucial role in reasoning, decision-making, and behavior regulation. Neuromorphic computing is a well-established engineering approach that offers promising avenues for advancing our understanding of WM processes by mimicking the structure and operation of the human brain using electronic technology. In this work, a digital neuromorphic system is proposed and then implemented in hardware to illustrate the real-time WM process based on the spiking neuron-astrocyte network (SNAN). The implemented SNAN utilizes a bidirectional neuron-astrocyte interaction to realize the WM process, allowing for a more brain-like memory emulation. Various hardware optimization methods, including piecewise linear approximation, double buffering, and time multiplexing are recruited to minimize the area and power consumption and facilitate the implementation of the WM concept on a single field programmable gate array (FPGA) chip. The proposed neuromorphic system is evaluated by testing its capacity for multi-item memory formation, an essential characteristic of human WM. The results show that the time duration between the store and recall phases is a critical parameter for acceptable retrieval performance. Additionally, the results demonstrate that the proposed neuromorphic system for WM is resilient to noise. Finally, the design modularity of the system facilitates easy extension for implementing larger networks and adapting to real-world applications.

Demonstration of a low-complexity real-time FBMC transmitter for a spectral-efficiency IMDD system.

Filter bank multi-carriers (FBMC) have higher spectral efficiency, lower out-of-band spectrum leakage, and stronger ability to resist synchronization errors compared to orthogonal frequency-division multiplexing (OFDM), which has been widely considered as a promising solution for short-reach applications, such as passive optical networks. However, the traditional fast Fourier transform (FFT)-based FBMC scheme has quite high implementation complexity for high-speed optical communications. In this work, we proposed a low-complexity real-time FBMC transmitter scheme enabled by a single fully parallel pruned inverse FFT and simplified short prototype filter-based polyphase networks for a low-cost intensity-modulation and direct-detection (IMDD) system. Compared to the OFDM transmitter, the proposed FBMC one occupies a similar number of look-up tables and registers but saves 21% of real multipliers, reduces latency by 16.2%, and increases the data rate by 12.5%. The real-time FBMC/OFDM signals are generated with a field programmable gate array chip and 6-bit 30-GSa/s digital-to-analog converter and are experimentally demonstrated in an IMDD system. After a 20-km standard single-mode fiber transmission, the negligible power penalty can be achieved with the proposed FBMC transmitter scheme at the bit error rate of 3.8e-3 compared to the OFDM counterpart.

The concept of multicore computing and processing in a field-programmable gate array chip

The article concerns the issue of multicore processing and implementation. The topic is introduced considering the functional division of various architectures. Examples of large-scale multicore architectures (with 144 and 1024 computational cores) are also presented. The main goal of the authors is to present the concept of implementing a multicore architecture in a Field-programmable gate array (FPGA). An available solution of the Nios II processor from the Intel library in the Quartus environment is presented. Additionally, the authors discuss their own concept of a computational core, outlining key assumptions, advantages and disadvantages, as well as potential issues.

Fully Parallel Stochastic Computing Hardware Implementation of Convolutional Neural Networks for Edge Computing Applications.

Edge artificial intelligence (AI) is receiving a tremendous amount of interest from the machine learning community due to the ever-increasing popularization of the Internet of Things (IoT). Unfortunately, the incorporation of AI characteristics to edge computing devices presents the drawbacks of being power and area hungry for typical deep learning techniques such as convolutional neural networks (CNNs). In this work, we propose a power-and-area efficient architecture based on the exploitation of the correlation phenomenon in stochastic computing (SC) systems. The proposed architecture solves the challenges that a CNN implementation with SC (SC-CNN) may present, such as the high resources used in binary-to-stochastic conversion, the inaccuracy produced by undesired correlation between signals, and the complexity of the stochastic maximum function implementation. To prove that our architecture meets the requirements of edge intelligence realization, we embed a fully parallel CNN in a single field-programmable gate array (FPGA) chip. The results obtained showed a better performance than traditional binary logic and other SC implementations. In addition, we performed a full VLSI synthesis of the proposed design, showing that it presents better overall characteristics than other recently published VLSI architectures.

Multiloop Control With Two Duty-Ratio Feedforward Current Loops via Sensing Series-Capacitor Current for Voltage Doubler PFC Converter

In this paper, the voltage doubler PFC converter with two boost inductors and one series-capacitor is studied. Only when both symmetrical duty ratios are larger than 0.5, the conventional multiloop control with one inner current loop and one voltage loop can be directly applied to the voltage doubler PFC converter due to its topology asymmetry. To remove this duty-ratio limit, the multiloop control with two duty-ratio feedforward current loops is proposed where the series-capacitor current is sensed to reconstruct two inductor currents. It follows that the number of sensor in the proposed control is three equal to the number of sensor in the conventional multiloop control. The proposed method is implemented in a Field Programmable Gate Array (FPGA) chip. The provided simulation and experimental results validate the effectiveness.

Hardware in the Loop-Based Testing of Three Schemes for Mitigation the Effect of Unsymmetrical Grid Faults on DFIG

This paper presents three-proposed schemes to mitigate the effect of unsymmetrical voltage sag fault on a wind-driven grid-connected Double Fed Induction Generator (DFIG). The first tested scheme comprises a static compensator (STATCOM) connected to the DFIG stator, while a three-phase parallel RL external impedance is connected to the rotor circuit in the second scheme. The STATCOM and the added rotor impedance are connected simultaneously in the third scheme. The effect of applying the three schemes on the responses of the stator and rotor voltages and currents, the dc-link voltage and current, the electrical torque, and the rotor speed during an unsymmetrical voltage sag are presented and compared at sub-and super-synchronous speeds. All systems were emulated, implemented, and tested through an OPAL RT-4510 Digital Real-Time Simulator (DRTS) in a Hardware-In-the-Loop (HIL) application. The internal Field-Programmable Gate Array (FPGA) chip assisted in using this platform as a Rapid Control Prototyping (RCP) for virtual mitigation control and testing. The Matlab/ Simulink RT-lab software packages combination helped in the RT development environment. All real-time waveforms of parameters for the proposed scenarios were monitored through the HIL-controller and data acquisition interface and then compared with the simulated results. The results reveal that the simulation waveforms and the real time waveforms are congruent. Results prove the better performance of the DFIG during unsymmetrical voltage sag for sub-synchronous speed when applying both protection schemes, while best results are obtained when using only the rotor impedance at super-synchronous speed operation of the DFIG.

Optimal Design of Electromagnetic Tomography Flaw Detection System for Train Wheel Based on FPGA

Electromagnetic tomography (EMT) is a new type of nondestructive testing technology that can be used for metal flaw detection. The implementation of the signal demodulation and filtering algorithm of the current electromagnetic tomography flaw detection system relies on the microprocessor MCU, and the reliability is low in real time. To improve the reliability and system integration of signal processing and transmission of the electromagnetic tomography flaw detection system, this paper uses the field programmable gate array chip to integrate the excitation signal generation module and the digital demodulation module based on the EMT train wheel flaw detection system. A digital filter is designed, and the filter parameters are adjusted to achieve a signal-to-noise ratio of 15 dB. UDP communication protocol is utilized to realize Ethernet communication between FPGA and upper computer. Using three algorithms on the host computer for image reconstruction, the train wheel defect information is visualized. The experimental results show that the FPGA chip improves the immunity of the train wheel flaw detection system, realizes the high integration of the system, and achieves the purpose of train wheel defect detection.

IRIS: An embedded secure boot for IoT devices

This study proposes a hardware secure boot solution, an instant retrieval information system (IRIS) that is suitable for integrating Internet of Things (IoT) devices. IRIS can boot a Linux kernel image pre-stores in removable media and comprises a data verifier securing the authenticity, integrity, and confidentiality of the boot process. IRIS is fully developed as a hardware module and the results reveal short boot-up times and a small hardware footprint when implemented on field programmable gate array chips. In addition, IRIS is an open-source generic solution that can be adapted to multiple architectures and includes a crypto-core called E-LUKS that can be used outside the boot-loading process to add confidentiality, integrity, and authenticity to data stored on off-chip storage like a flash device.IRIS shows a reduction in lookup tables footprint when compared to other IoT solutions consuming from 90% to 750% less resources and only slightly greater, around 30%, with solutions that only cover authentication and integrity.

Research on the Deployment Strategy of Big Data Visualization Platform by the Internet of Things Technology

INTRODUCTION: To improve the big data visualization platform's performance and task scheduling capability, a big data visualization platform is constructed based on Field Programmable Gate Array (FPGA) chip application power equipment.OBJECTIVES: This study proposes to combine a genetic algorithm and an ant colony scheduling (ACOS) algorithm to design a big data visualization platform deployment strategy based on an improved ACOS algorithm.METHODS: Firstly, big data technology is analyzed. Then, the basic theory of the ant colony algorithm is studied. According to the basic theory of ACOS and genetic algorithm, an improved ACOS algorithm model is constructed. The improved ACOS algorithm scheduler is compared with the other three schedulers. Under the same environment, the completion time of scheduling the same job and different task amounts are analyzed. The Central Processing Unit (CPU) utilization is analyzed when different schedulers have entirely different workloads. RESULTS: The results show that the constructed big data visualization platform based on the improved ACOS algorithm model has higher task scheduling efficiency than other schedulers and can greatly shorten the data processing time. The experimental results show that under the homogeneous cluster, the completion time of the improved ACOS algorithm generally lags the capacity scheduler and the fair scheduler. Under the heterogeneous cluster, the improved ACOS algorithm scheduler can reasonably allocate tasks to nodes with different performances, reducing the task completion time. When the number of completed tasks increases from 50 to 200, the time increases by 45s, and the completion time is shorter than other schedulers. The CPU utilization of different task volumes is the highest, and the utilization rate increases from 81% to 95%. CONCLUSION: The improved ACOS algorithm scheduler has the shortest data processing time and the highest efficiency. This work provides a specific reference value for optimizing the big data visualization platform's deployment strategy and improving the platform's performance.

Scalable serial hardware architecture of multilayer perceptron neural network for automatic wheezing detection

This paper proposes a serial hardware architecture of a multilayer perceptron (MLP) neural network for real-time wheezing detection in respiratory sounds. As an established classification tool, the MLP has proven its ability to identify complex patterns within respiratory sounds. The proposed fully serial architecture uses a single calculation unit, independently of the number of neurons in the MLP network. It is also a fully scalable architecture that permits to implement MLP networks, of any size, easily and efficiently without modifying the design or wiring. The proposed serial architecture has been implemented on a low-cost and power-efficient field programmable gate array (FPGA) chip using a high-level programming tool. The respiratory sounds classification rates are evaluated in terms of sensitivity, specificity, performance, and accuracy. The proposed serial architecture reaches the same classification performances as the parallel one, but it presents the main advantage of using much fewer hardware resources.

Unequal Duty-Ratio Feedforward Control to Extend Balanced-Currents Input Voltage Range for Series-Capacitor-Based Boost PFC Converter

In this letter, the series-capacitor-based boost power factor correction (PFC) converter (or called the voltage doubler PFC converter) is studied. It possesses the voltage doubler and intrinsic current balancing characteristics only when their equal duty ratios are larger than 0.5. Thus, for PFC application, the balanced-currents input voltage should be smaller than the quarter (1/4) output dc voltage. To extend the balanced-currents input voltage range, the unequal duty-ratio feedforward control is proposed in this letter. For the case of dc output voltage 400 V, the maximum input voltage with balanced inductor currents increased from 100 V (the quarter output dc voltage) to 200 V. The proposed control method is implemented in the field programmable gate array chip to evaluate its performance.

FPGA-based implementation of deep neural network using stochastic computing

A serious challenge in artificial real-time applications is the hardware implementation of deep neural networks (DNN). Among various methods, stochastic computing (SC)-based implementations received tremendous attention due to the low hardware overhead. However, the slow convergence rate is a major problem in SC-based neural networks’ implementation, and millions of clock cycles are required to generate a relatively accurate output. The reconfigurability and parallel nature of field programmable gate array (FPGA) chips make them a preferable platform for SC-based DNN implementation. A fully or semi-parallel implementation of DNNs requires extensive hardware resources. In this paper, an efficient method for DNN implementation on an FPGA chip is presented to address these problems. The FPGA chip reconfiguration feature allows a DNN with several different neurons and topologies to be implemented on a single chip. Convergence time is significantly reduced by limiting the length of the stochastic bitstreams and establishing synchronization between the processing units based on precise timing. Furthermore, due to the limited number of input–output pins in the FPGA chip, a sequential architecture is proposed wherein the DNN inputs enter through only three 8-bit ports. This makes it possible to implement DNNs for image-processing applications. The proposed method is implemented using the Verilog hardware description language on the Xilinx FPGA Virtex-7 xc7v2000t chip. The results show a more than 82% reduction in hardware resources and the minimum rate of power consumption compared to state-of-the-art methods. In addition, the average error rate of the implemented DNN is reduced by 2%.

Artificial intelligence techniques for encrypt images based on the chaotic system implemented on field-programmable gate array

<span lang="EN-US">Image encryption is an important issue in protecting the content of images and in the area of information security. This article proposes a novel method for image encryption and decryption using the structure of the artificial neural network (ANN)-based chua chaotic system (CCS). This structure was efficiently designed on a field-programmable gate array (FPGA) chip utilizing the xilinx system generator (XSG) tool with the IEEE-754-1985 32-bit floating-point number format. For ANN-based CCS design, a multilayer feed forward neural network (FFNN) structure with three inputs and three outputs was created. This structure consists of one hidden layer with four neurons, each of which has a Tangent Sigmoid activation function. The training of ANN-based CCS yielded a 3.602e-13 mean square error (MSE) value. After successfully training the ANN-based CCS, the design was carried out on FPGA, utilizing the ANN structure's bias and weight values as a reference. The xilinx vivado (2017.4) design suite was used to synthesis and test the ANN-based CCS on the FPGA. The histogram, correlation coefficient, and entropy are used to perform security analysis on various images. Finally, FPGA hardware co-simulation using a Xilinx Artix7 xc7a100t-1csg324 chip was utilized to verify that the encryption and decryption of the images were successful.</span>

All-digital transmit beamformer for portable high-frequency ultrasound imaging systems.

To meet the requirements of high-frequency ultrasound imaging systems, a transmit-beamforming integrated circuit with higher delay resolution than conventional transmit-beamforming circuits, which are typically implemented using field-programmable gate array chips, is presented. It also requires smaller volumes, allowing for portable applications. Its proposed design includes two all-digital delay-locked loops providing a specified digital control code for a counter-based beamforming delay chain (CBDC) to generate stable and suitable delays for exciting the array transducer elements without variations in process, voltage, and temperature. Moreover, to maintain the duty cycle of long propagation signals, this novel CBDC requires only a few delay cells, significantly reducing hardware costs and power consumption. Simulations were conducted, revealing a maximum time delay of 451.9ns with a time resolution of 652ps and a maximum lateral resolution error of 0.04mm at 6.8mm.

Highly Concurrent TCP Session Connection Management System on FPGA Chip

Transmission Control Protocol (TCP) is a connection-oriented data transmission protocol, and it is also the main communication protocol used for end-to-end data transmission in the current Internet. At present, the mainstream TCP protocol processing service is implemented by software running on the Central Processing Unit (CPU). However, with the rapid growth of transmission bandwidth and the number of connections, the software-based processing method is not ideal in terms of delay and throughput, and also affects the processing performance of the CPU in other applications such as virtualization services. Moreover, other hardware solutions can only support a limited number of TCP session connections. In order to improve the processing efficiency of the TCP protocol and achieve highly concurrent network services, this paper proposes a TCP offload engine (TOE) prototype system based on field programmable gate array (FPGA) chips. It not only provides hardware-based data path processing, but also realizes hardware management of large-scale TCP session connection status through a multi-level cache management mechanism. Studies have shown that this solution can support 100 Gbps high-performance throughput characteristics, and allow concurrent processing of hundreds to 250,000 TCP connection state hardware maintenance on a single network node, improving the overall performance of the network system.

Implementation of encoder and decoder for low-density parity-check codes in continuous-variable quantum key distribution on a field programmable gate array

Quantum key distribution (QKD) can provide an unconditionally secure communication encryption method. Continuous-variable QKD (CVQKD) requires extracting the key from the noisy channel, leading to higher requirements for the error-correcting codes used in multidimensional reconciliation. We extend the quasi-cyclic low-density parity-check of the radio design for the global 5G mobile communication technology standard to achieve error correction under lower signal-to-noise ratio on integrated hardware. A field programmable gate array (FPGA) chip is used to realize the approximate lower triangular matrix encoding algorithm, and the core module only has the circular shift register, which reduces the encoding complexity, improves the encoding efficiency, and reduces the hardware resource consumption. For extended super-long code words, the decoding algorithm requires additional hardware resources to implement, which the previous algorithm cannot meet. Therefore, we present a hardware implementation of offset minimum sum algorithm (OMSA), which can avoid operations of complex mathematical formula. The offset factor of OMSA reduce the error caused by the low accuracy of calculation on the hardware. The update of the decoding information is layered in a partially parallel way in the matrix to achieve the cross processing of node information. It speeds up the transmission of information between different nodes and the convergence of decoding algorithm of low-complexity parallel structure. Simulation results show that the maximum theoretical coordination efficiency is 85% when the code with block length is 69632 at a bit rate of 22/68 and the signal-to-noise ratio asymptotic threshold is 0.7. Using an FPGA, ∼0.1 frame error rate was achieved, but with a zero-bit error rate, the optimal achievable secret key rate is about 200 Kbps at 30-km distance theoretically. For a 200-MHz system clock on the successfully decoded block, 125 Gbps encoding throughput and 472 Kbps decoding throughput was achieved, better than the theoretical key rate of prototype of CVQKD.

A Real-Time Data Acquisition System for Single-Band Bathymetric LiDAR

Bathymetric light detection and ranging (LiDAR), which uses a laser with narrow pulse width and a high-repetition-rate, requires a real-time data acquisition system (RTDAQS) for quickly transmitting data with the characteristic of high sampling rates, high resolution and high accuracy. However, none of the RTDAQS in the world has reached these requirements. For this reason, this paper presents a RTDAQS with high speed SerDes data transfer technology based on the architecture of ADC+FPGA+ZYNQ. This RTDAQS consists of acquisition board and storage board. The acquisition board integrates high-speed analog-to-digital converter (ADC) acquisition module, Input/Output (I/O) control module, data transmission module, and Field Programmable Gate Array (FPGA) chip module. The storage board integrates FPGA Mezzanine Card (FMC) interface, solid state and ZYNQ chips. The corresponding software includes configuration for high-speed ADC acquisition module, I/O control module, data transmission module, and FMC interface module. The RTDAQS, which is embedded in the LiDAR with laser pulses width of 2.5ns ± 0.2ns and frequency of 500 Hz, has been verified by the experiments in indoor sink, outdoor pond, river, reservoir, Beihai Bay of the Pacific Ocean. The experimental results and comparison experiments demonstrate that the presented RTDAQS can reach a sampling rate of 2 GSPS and a sampling resolution of 14 bits and a sampling accuracy of 6 LSB with an acquisition error within 0.1 m, which meet the demands of high sampling rate with high accuracy data acquisition and quick data transmission in practice and can be applied to various devices.

Self-Alignment FSOC System With Miniaturized Structure for Small Mobile Platform

This paper presents a miniaturized equipment used in tracking and pointing, and provides a method for free space optical communication among small platform. This scheme uses simple scan mirror and receiver with single photo detector to achieve tracking function. Signal beacon is controlled to rotate around target receiver. Transmitter constantly adjusts emitting direction to track receiver according to received signal intensity, which is send back by reverse laser link. The prototype system is successfully established and its transmitting part consisted by directly modulated laser diode, mechanical collimation lens, and scan mirror is also proved. The receiving end is mainly composed of large area photo detector and short-focal lens. Field-programmable gate array chips set in both ends are used to implement tracking algorithm. This system can track target at speed of 40 mm/s within 2 m distance in an angle range of ±30°. For further application, the system has great potential for miniaturization because of elimination of motors, beacons and cameras in its scheme.